mirror of https://github.com/wolfSSL/wolfBoot.git
127 lines
3.8 KiB
Plaintext
127 lines
3.8 KiB
Plaintext
ARCH?=AARCH64
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TARGET?=zynq
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WOLFBOOT_VERSION?=0
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# RSA 4096-bit with SHA3-384
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SIGN?=RSA4096
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HASH?=SHA3
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IMAGE_HEADER_SIZE?=1024
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# Hashing Option
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# 1. ARMv8+Crypto Assembly: HW_SHA3=0 and NO_ARM_ASM=0 (default)
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# 2. CSU SHA3 hardware acceleration HW_SHA3=1 and NO_ARM_ASM=1
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# 3. C Only HW_SHA3=0 and NO_ARM_ASM=1
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NO_ARM_ASM?=0
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HW_SHA3?=0
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# XMSS/XMSS^MT is a post-quantum, stateful, hash-based signature scheme.
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# Use the helper script `tools/xmss/xmss_siglen.sh`
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# to calculate your signature length given an xmss parameter string.
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#SIGN?=XMSS
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#HASH?=SHA256
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#XMSS_PARAMS='XMSS-SHA2_10_256'
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#IMAGE_SIGNATURE_SIZE=2500
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#IMAGE_HEADER_SIZE?=5000
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# LMS/HSS is a post-quantum, stateful, hash-based signature scheme.
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# Use the helper script `tools/lms/lms_siglen`
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#SIGN?=LMS
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#HASH?=SHA256
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#LMS_LEVELS=2
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#LMS_HEIGHT=5
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#LMS_WINTERNITZ=8
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#IMAGE_SIGNATURE_SIZE=2644
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#IMAGE_HEADER_SIZE?=5288
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DEBUG?=0
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DEBUG_SYMBOLS=1
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DEBUG_UART=1
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CFLAGS_EXTRA+=-DDEBUG_ZYNQ=1
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#OPTIMIZATION_LEVEL=2
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=0
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DUALBANK_SWAP?=0
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PKA?=0
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WOLFTPM?=0
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EXT_FLASH?=1
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SPI_FLASH?=0
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NO_XIP=1
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USE_GCC=1
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ELF?=1
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#DEBUG_ELF?=1
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# Native gzip decompression for FIT subimages (set GZIP=0 to disable)
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GZIP?=1
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# Flash Sector Size
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WOLFBOOT_SECTOR_SIZE=0x20000
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# Application Partition Size
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WOLFBOOT_PARTITION_SIZE=0x2A00000
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# Location in Flash for wolfBoot
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WOLFBOOT_ORIGIN=0x0
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# Location in Flash for Primary Boot Partition
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x800000
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# Load Partition to RAM Address
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WOLFBOOT_LOAD_ADDRESS?=0x10000000
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# Location in Flash for Secondary Partition
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x3A00000
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# Location to store wolfBoot state
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x63E0000
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# DTS (Device Tree)
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x11800000
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WOLFBOOT_DTS_BOOT_ADDRESS?=0x7B0000
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WOLFBOOT_DTS_UPDATE_ADDRESS?=0x39B0000
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# Optional: program the PL from an "fpga" sub-image in the FIT before boot
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# (handed to the PMU firmware via PM_FPGA_LOAD). Requires GZIP=1 when the
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# bitstream node uses compression="gzip" (the typical mkimage output). The
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# fpga node usually has no `load` property, so set a DDR staging address
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# clear of the FIT (0x10000000), kernel (0x200000), and DTS (0x11800000).
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#FPGA_BITSTREAM?=1
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#WOLFBOOT_LOAD_FPGA_ADDRESS?=0x40000000
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CROSS_COMPILE=aarch64-none-elf-
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#CROSS_COMPILE=aarch64-linux-gnu-
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# Speed up reads from flash by using larger blocks
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CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
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# QSPI Reference Clock: Ref (125MHz default)
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#CFLAGS_EXTRA+=-DGQSPI_CLK_REF=300000000
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# QSPI Bus Divisor: (2 << div) = BUS (0=div2, 1=div4, 2=div8)
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#CFLAGS_EXTRA+=-DGQSPI_CLK_DIV=0
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# QSPI force IO mode (default is faster DMA mode)
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#CFLAGS_EXTRA+=-DGQSPI_MODE_IO
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# Optional: Ethernet PHY init over GEM MDIO.
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# Replays a board-specific "mii"/"mw" register sequence (normally run from
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# U-Boot) so the PHY is configured before the OS starts. wolfBoot has no
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# network stack; this drives only the MDIO management plane.
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#CFLAGS_EXTRA+=-DWOLFBOOT_ZYNQMP_PHY_INIT
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# Defaults (hal/zynq.h) target the ZCU102 PHY (DP83867 at MDIO 0x0C on GEM3)
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# and just read the PHY ID. For another board, keep its values in a small
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# header and select it with one line (this keeps the efficient step array):
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#CFLAGS_EXTRA+=-DZYNQMP_PHY_INIT_HEADER='"myboard_phy.h"'
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# where myboard_phy.h #defines any of:
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# ZYNQMP_GEM_BASE GEM register base (default 0xFF0E0000 = GEM3)
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# ZYNQMP_PHY_ADDR PHY MDIO address (default 0x0C)
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# ZYNQMP_PHY_GPIO_ADDR PL register poked by a GPIO step; 0 disables it
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# ZYNQMP_GEM_MDC_DIV NWCFG MDC divisor selector (default 5 = pclk/96)
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# ZYNQMP_PHY_INIT_STEPS the {op,arg0,arg1} sequence rows
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# Simple scalars can also be set directly, e.g.:
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#CFLAGS_EXTRA+=-DZYNQMP_GEM_BASE=0xFF0B0000UL
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# A PHY behind the PL only responds once the FPGA bitstream is loaded, so the
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# boot image (BOOT.BIN) must include it (bootgen [destination_device=pl]).
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