mirror of https://github.com/wolfSSL/wolfBoot.git
587 lines
20 KiB
C
587 lines
20 KiB
C
/* startup_arm.c
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*
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* Test bare-metal blinking led application
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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extern unsigned int _stored_data;
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extern unsigned int _start_data;
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extern unsigned int _end_data;
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extern unsigned int _start_bss;
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extern unsigned int _end_bss;
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extern unsigned int _end_stack;
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extern unsigned int _start_heap;
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#ifdef TARGET_stm32f4
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extern void isr_tim2(void);
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#else
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#define isr_tim2 isr_empty
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#endif
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#ifdef TARGET_stm32h5
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extern void isr_usart3(void);
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#endif
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#ifdef TARGET_s32k1xx
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extern void isr_lpuart1(void);
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#endif
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#if defined(TARGET_va416x0) || defined(TARGET_lpc55s69)
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#define isr_systick SysTick_Handler
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#elif !defined(APP_HAS_SYSTICK)
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#define isr_systick isr_empty
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#endif
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extern void isr_systick(void);
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#ifndef STACK_PAINTING
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#define STACK_PAINTING 0
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#endif
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static volatile unsigned int avail_mem = 0;
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#if STACK_PAINTING
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static unsigned int sp;
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#endif
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extern void main(void);
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void isr_reset(void) {
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register unsigned int *src, *dst;
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#if defined(WOLFBOOT_TIME_TEST) && defined(TARGET_stm32h5)
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extern void boot_time_pin_on_early(void);
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boot_time_pin_on_early();
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#endif
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src = (unsigned int *) &_stored_data;
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dst = (unsigned int *) &_start_data;
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while (dst < (unsigned int *)&_end_data) {
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*dst = *src;
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dst++;
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src++;
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}
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dst = &_start_bss;
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while (dst < (unsigned int *)&_end_bss) {
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*dst = 0U;
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dst++;
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}
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avail_mem = &_end_stack - &_start_heap;
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#if STACK_PAINTING
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{
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asm volatile("mrs %0, msp" : "=r"(sp));
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dst = ((unsigned int *)(&_end_stack)) - (8192 / sizeof(unsigned int)); ;
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while ((unsigned int)dst < sp) {
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*dst = 0xDEADC0DE;
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dst++;
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}
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}
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#endif
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main();
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}
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void isr_fault(void)
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{
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/* Panic. */
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while(1) ;
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}
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void isr_memfault(void)
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{
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/* Panic. */
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while(1) ;
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}
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void isr_busfault(void)
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{
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/* Panic. */
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while(1) ;
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}
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void isr_usagefault(void)
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{
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/* Panic. */
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while(1) ;
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}
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void isr_empty(void)
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{
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}
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__attribute__ ((section(".isr_vector")))
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void (* const IV[])(void) =
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{
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(void (*)(void))(&_end_stack),
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isr_reset, // Reset
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isr_fault, // NMI
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isr_fault, // HardFault
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isr_memfault, // MemFault
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isr_busfault, // BusFault
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isr_usagefault, // UsageFault
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0, // SecureFault
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0, // reserved
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0, // reserved
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0, // reserved
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isr_empty, // SVC
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isr_empty, // DebugMonitor
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0, // reserved
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isr_empty, // PendSV
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isr_systick, // SysTick
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/* Device specific IRQs for LM3S */
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#ifdef LM3S
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isr_empty, // GPIO Port A
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isr_empty, // GPIO Port B
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isr_empty, // GPIO Port C
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isr_empty, // GPIO Port D
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isr_empty, // GPIO Port E
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isr_empty, // UART0 Rx and Tx
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isr_empty, // UART1 Rx and Tx
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isr_empty, // SSI0 Rx and Tx
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isr_empty, // I2C0 Master and Slave
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isr_empty, // PWM Fault
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isr_empty, // PWM Generator 0
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isr_empty, // PWM Generator 1
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isr_empty, // PWM Generator 2
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isr_empty, // Quadrature Encoder 0
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isr_empty, // ADC Sequence 0
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isr_empty, // ADC Sequence 1
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isr_empty, // ADC Sequence 2
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isr_empty, // ADC Sequence 3
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isr_empty, // Watchdog timer
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isr_empty, // Timer 0 subtimer A
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isr_empty, // Timer 0 subtimer B
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isr_empty, // Timer 1 subtimer A
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isr_empty, // Timer 1 subtimer B
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isr_empty, // Timer 2 subtimer A
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isr_empty, // Timer 3 subtimer B
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isr_empty, // Analog Comparator 0
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isr_empty, // Analog Comparator 1
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isr_empty, // Analog Comparator 2
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isr_empty, // System Control (PLL, OSC, BO)
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isr_empty, // FLASH Control
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isr_empty, // GPIO Port F
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isr_empty, // GPIO Port G
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isr_empty, // GPIO Port H
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isr_empty, // UART2 Rx and Tx
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isr_empty, // SSI1 Rx and Tx
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isr_empty, // Timer 3 subtimer A
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isr_empty, // Timer 3 subtimer B
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isr_empty, // I2C1 Master and Slave
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isr_empty, // Quadrature Encoder 1
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isr_empty, // CAN0
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isr_empty, // CAN1
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isr_empty, // CAN2
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isr_empty, // Ethernet
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isr_empty, // Hibernate
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#elif (defined(TARGET_stm32l5) ||defined(TARGET_stm32u5) || defined(TARGET_stm32u3)) /* Fill with extra unused handlers */
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isr_empty, // WWDG_IRQHandler
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isr_empty, // PVD_PVM_IRQHandler
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isr_empty, // RTC_IRQHandler
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isr_empty, // RTC_S_IRQHandler
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isr_empty, // TAMP_IRQHandler
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isr_empty, // TAMP_S_IRQHandler
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isr_empty, // FLASH_IRQHandler
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isr_empty, // FLASH_S_IRQHandler
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isr_empty, // GTZC_IRQHandler
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isr_empty, // RCC_IRQHandler
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isr_empty, // RCC_S_IRQHandler
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isr_empty, // EXTI0_IRQHandler
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isr_empty, // EXTI1_IRQHandler
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isr_empty, // EXTI2_IRQHandler
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isr_empty, // EXTI3_IRQHandler
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isr_empty, // EXTI4_IRQHandler
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isr_empty, // EXTI5_IRQHandler
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isr_empty, // EXTI6_IRQHandler
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isr_empty, // EXTI7_IRQHandler
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isr_empty, // EXTI8_IRQHandler
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isr_empty, // EXTI9_IRQHandler
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isr_empty, // EXTI10_IRQHandler
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isr_empty, // EXTI11_IRQHandler
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isr_empty, // EXTI12_IRQHandler
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isr_empty, // EXTI13_IRQHandler
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isr_empty, // EXTI14_IRQHandler
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isr_empty, // EXTI15_IRQHandler
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isr_empty, // DMAMUX1_IRQHandler
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isr_empty, // DMAMUX1_S_IRQHandler
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isr_empty, // DMA1_Channel1_IRQHandler
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isr_empty, // DMA1_Channel2_IRQHandler
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isr_empty, // DMA1_Channel3_IRQHandler
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isr_empty, // DMA1_Channel4_IRQHandler
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isr_empty, // DMA1_Channel5_IRQHandler
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isr_empty, // DMA1_Channel6_IRQHandler
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isr_empty, // DMA1_Channel7_IRQHandler
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isr_empty, // DMA1_Channel8_IRQHandler
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isr_empty, // ADC1_2_IRQHandler
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isr_empty, // DAC_IRQHandler
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isr_empty, // FDCAN1_IT0_IRQHandler
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isr_empty, // FDCAN1_IT1_IRQHandler
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isr_empty, // TIM1_BRK_IRQHandler
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isr_empty, // TIM1_UP_IRQHandler
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isr_empty, // TIM1_TRG_COM_IRQHandler
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isr_empty, // TIM1_CC_IRQHandler
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isr_empty, // TIM2_IRQHandler
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isr_empty, // TIM3_IRQHandler
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isr_empty, // TIM4_IRQHandler
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isr_empty, // TIM5_IRQHandler
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isr_empty, // TIM6_IRQHandler
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isr_empty, // TIM7_IRQHandler
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isr_empty, // TIM8_BRK_IRQHandler
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isr_empty, // TIM8_UP_IRQHandler
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isr_empty, // TIM8_TRG_COM_IRQHandler
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isr_empty, // TIM8_CC_IRQHandler
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isr_empty, // I2C1_EV_IRQHandler
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isr_empty, // I2C1_ER_IRQHandler
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isr_empty, // I2C2_EV_IRQHandler
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isr_empty, // I2C2_ER_IRQHandler
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isr_empty, // SPI1_IRQHandler
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isr_empty, // SPI2_IRQHandler
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isr_empty, // USART1_IRQHandler
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isr_empty, // USART2_IRQHandler
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isr_empty, // USART3_IRQHandler
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isr_empty, // UART4_IRQHandler
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isr_empty, // UART5_IRQHandler
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isr_empty, // LPUART1_IRQHandler
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isr_empty, // LPTIM1_IRQHandler
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isr_empty, // LPTIM2_IRQHandler
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isr_empty, // TIM15_IRQHandler
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isr_empty, // TIM16_IRQHandler
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isr_empty, // TIM17_IRQHandler
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isr_empty, // COMP_IRQHandler
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isr_empty, // USB_FS_IRQHandler
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isr_empty, // CRS_IRQHandler
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isr_empty, // FMC_IRQHandler
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isr_empty, // OCTOSPI1_IRQHandler
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isr_empty, // 0
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isr_empty, // SDMMC1_IRQHandler
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isr_empty, // 0
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isr_empty, // DMA2_Channel1_IRQHandler
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isr_empty, // DMA2_Channel2_IRQHandler
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isr_empty, // DMA2_Channel3_IRQHandler
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isr_empty, // DMA2_Channel4_IRQHandler
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isr_empty, // DMA2_Channel5_IRQHandler
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isr_empty, // DMA2_Channel6_IRQHandler
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isr_empty, // DMA2_Channel7_IRQHandler
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isr_empty, // DMA2_Channel8_IRQHandler
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isr_empty, // I2C3_EV_IRQHandler
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isr_empty, // I2C3_ER_IRQHandler
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isr_empty, // SAI1_IRQHandler
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isr_empty, // SAI2_IRQHandler
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isr_empty, // TSC_IRQHandler
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isr_empty, // AES_IRQHandler
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isr_empty, // RNG_IRQHandler
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isr_empty, // FPU_IRQHandler
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isr_empty, // HASH_IRQHandler
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isr_empty, // PKA_IRQHandler
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isr_empty, // LPTIM3_IRQHandler
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isr_empty, // SPI3_IRQHandler
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isr_empty, // I2C4_ER_IRQHandler
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isr_empty, // I2C4_EV_IRQHandler
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isr_empty, // DFSDM1_FLT0_IRQHandler
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isr_empty, // DFSDM1_FLT1_IRQHandler
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isr_empty, // DFSDM1_FLT2_IRQHandler
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isr_empty, // DFSDM1_FLT3_IRQHandler
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isr_empty, // UCPD1_IRQHandler
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isr_empty, // ICACHE_IRQHandler
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isr_empty, // OTFDEC1_IRQHandler
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//
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#elif defined(TARGET_stm32h5)
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isr_empty, // WWDG_IRQHandler
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isr_empty, // PVD_PVM_IRQHandler
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isr_empty, // RTC_IRQHandler
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isr_empty, // RTC_S_IRQHandler
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isr_empty, // TAMP_IRQHandler
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isr_empty, // RAMCFG_IRQHandler
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isr_empty, // FLASH_IRQHandler
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isr_empty, // FLASH_S_IRQHandler
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isr_empty, // GTZC_IRQHandler
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isr_empty, // RCC_IRQHandler
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isr_empty, // RCC_S_IRQHandler
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isr_empty, // EXTI0_IRQHandler
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isr_empty, // EXTI1_IRQHandler
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isr_empty, // EXTI2_IRQHandler
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isr_empty, // EXTI3_IRQHandler
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isr_empty, // EXTI4_IRQHandler
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isr_empty, // EXTI5_IRQHandler
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isr_empty, // EXTI6_IRQHandler
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isr_empty, // EXTI7_IRQHandler
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isr_empty, // EXTI8_IRQHandler
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isr_empty, // EXTI9_IRQHandler
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isr_empty, // EXTI10_IRQHandler
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isr_empty, // EXTI11_IRQHandler
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isr_empty, // EXTI12_IRQHandler
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isr_empty, // EXTI13_IRQHandler
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isr_empty, // EXTI14_IRQHandler
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isr_empty, // EXTI15_IRQHandler
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isr_empty, // GPDMA1CH0_IRQHandler
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isr_empty, // GPDMA1CH1_IRQHandler
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isr_empty, // GPDMA1CH2_IRQHandler
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isr_empty, // GPDMA1CH3_IRQHandler
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isr_empty, // GPDMA1CH4_IRQHandler
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isr_empty, // GPDMA1CH5_IRQHandler
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isr_empty, // GPDMA1CH6_IRQHandler
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isr_empty, // GPDMA1CH7_IRQHandler
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isr_empty, // IWDG_IRQHandler
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isr_empty, // SAES_IRQHandler
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isr_empty, // ADC1_IRQHandler
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isr_empty, // DAC1_IRQHandler
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isr_empty, // FDCAN1_IT0_IRQHandler
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isr_empty, // FDCAN1_IT1_IRQHandler
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isr_empty, // TIM1_BRK_IRQHandler
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isr_empty, // TIM1_UP_IRQHandler
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isr_empty, // TIM1_TRG_COM_IRQHandler
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isr_empty, // TIM1_CC_IRQHandler
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isr_empty, // TIM2_IRQHandler
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isr_empty, // TIM3_IRQHandler
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isr_empty, // TIM4_IRQHandler
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isr_empty, // TIM5_IRQHandler
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isr_empty, // TIM6_IRQHandler
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isr_empty, // TIM7_IRQHandler
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isr_empty, // I2C1_EV_IRQHandler
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isr_empty, // I2C1_ER_IRQHandler
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isr_empty, // I2C2_EV_IRQHandler
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isr_empty, // I2C2_ER_IRQHandler
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isr_empty, // SPI1_IRQHandler
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isr_empty, // SPI2_IRQHandler
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isr_empty, // SPI3_IRQHandler
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isr_empty, // USART1_IRQHandler
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isr_empty, // USART2_IRQHandler
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isr_usart3, // USART3_IRQHandler
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isr_empty, // UART4_IRQHandler
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isr_empty, // UART5_IRQHandler
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isr_empty, // LPUART1_IRQHandler
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isr_empty, // LPTIM1_IRQHandler
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isr_empty, // TIM8_BRK_IRQHandler
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isr_empty, // TIM8_UP_IRQHandler
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isr_empty, // TIM8_TRG_COM_IRQHandler
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isr_empty, // TIM8_CC_IRQHandler
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isr_empty, // ADC2_IRQHandler
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isr_empty, // LPTIM2_IRQHandler
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isr_empty, // TIM15_IRQHandler
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isr_empty, // TIM16_IRQHandler
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isr_empty, // TIM17_IRQHandler
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isr_empty, // USB_FS_IRQHandler
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isr_empty, // CRS_IRQHandler
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isr_empty, // UCPD1_IRQHandler
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isr_empty, // FMC_IRQHandler
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isr_empty, // OCTOSPI1_IRQHandler
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isr_empty, // SDMMC1_IRQHandler
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isr_empty, // I2C3_EV_IRQHandler
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isr_empty, // I2C3_ER_IRQHandler
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isr_empty, // SPI4_IRQHandler
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isr_empty, // SPI5_IRQHandler
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isr_empty, // SPI6_IRQHandler
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isr_empty, // USART6_IRQHandler
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isr_empty, // USART10_IRQHandler
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isr_empty, // USART11_IRQHandler
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isr_empty, // SAI1_IRQHandler
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isr_empty, // SAI2_IRQHandler
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isr_empty, // GPDMA2CH0_IRQHandler
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isr_empty, // GPDMA2CH1_IRQHandler
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isr_empty, // GPDMA2CH2_IRQHandler
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isr_empty, // GPDMA2CH3_IRQHandler
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isr_empty, // GPDMA2CH4_IRQHandler
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isr_empty, // GPDMA2CH5_IRQHandler
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isr_empty, // GPDMA2CH6_IRQHandler
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isr_empty, // GPDMA2CH7_IRQHandler
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isr_empty, // UART7_IRQHandler
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isr_empty, // UART8_IRQHandler
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isr_empty, // UART9_IRQHandler
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isr_empty, // UART12_IRQHandler
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isr_empty, // SDMMC2_IRQHandler
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isr_empty, // FPU_IRQHandler
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isr_empty, // ICACHE_IRQHandler
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isr_empty, // DCACHE_IRQHandler
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isr_empty, // ETH1_IRQHandler
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isr_empty, // DCMI_PSSI_IRQHandler
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isr_empty, // FDCAN2_IT0_IRQHandler
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isr_empty, // FDCAN2_IT1_IRQHandler
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isr_empty, // CORDIC_IRQHandler
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isr_empty, // FMAC_IRQHandler
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isr_empty, // DTS_IRQHandler
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isr_empty, // RNG_IRQHandler
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isr_empty, // OTFDEC1_IRQHandler
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isr_empty, // AES_IRQHandler
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isr_empty, // HASH_IRQHandler
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isr_empty, // PKA_IRQHandler
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isr_empty, // CEC_IRQHandler
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isr_empty, // TIM12_IRQHandler
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isr_empty, // TIM13_IRQHandler
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isr_empty, // TIM14_IRQHandler
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isr_empty, // I3C1_EV_IRQHandler
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isr_empty, // I3C1_ER_IRQHandler
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isr_empty, // I2C4_EV_IRQHandler
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isr_empty, // I2C4_ER_IRQHandler
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isr_empty, // LPTIM3_IRQHandler
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isr_empty, // LPTIM4_IRQHandler
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isr_empty, // LPTIM5_IRQHandler
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isr_empty, // LPTIM6_IRQHandler
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#elif defined(TARGET_s32k1xx) /* For NXP S32K1xx */
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isr_empty, // DMA0 0
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isr_empty, // DMA1 1
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isr_empty, // DMA2 2
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isr_empty, // DMA3 3
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isr_empty, // DMA4 4
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isr_empty, // DMA5 5
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isr_empty, // DMA6 6
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isr_empty, // DMA7 7
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isr_empty, // DMA8 8
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isr_empty, // DMA9 9
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isr_empty, // DMA10 10
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isr_empty, // DMA11 11
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isr_empty, // DMA12 12
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isr_empty, // DMA13 13
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isr_empty, // DMA14 14
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isr_empty, // DMA15 15
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isr_empty, // DMA_Error 16
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isr_empty, // MCM 17
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isr_empty, // FTFC 18
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isr_empty, // Read_Collision 19
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isr_empty, // LVD_LVW 20
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isr_empty, // FTFC_Fault 21
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isr_empty, // WDOG_EWM 22
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isr_empty, // RCM 23
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isr_empty, // LPI2C0_Master 24
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isr_empty, // LPI2C0_Slave 25
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isr_empty, // LPSPI0 26
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isr_empty, // LPSPI1 27
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isr_empty, // LPSPI2 28
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isr_empty, // Reserved29 29
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isr_empty, // Reserved30 30
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isr_empty, // LPUART0_RxTx 31
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isr_empty, // Reserved32 32
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isr_lpuart1, // LPUART1_RxTx 33
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isr_empty, // Reserved34 34
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isr_empty, // LPUART2_RxTx 35
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isr_empty, // Reserved36 36
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isr_empty, // Reserved37 37
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isr_empty, // ADC0 38
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isr_empty, // ADC1 39
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isr_empty, // CMP0 40
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isr_empty, // Reserved41 41
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isr_empty, // Reserved42 42
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isr_empty, // ERM_single 43
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isr_empty, // ERM_double 44
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isr_empty, // RTC 45
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isr_empty, // RTC_Seconds 46
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isr_empty, // LPIT0_Ch0 47
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isr_empty, // LPIT0_Ch1 48
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isr_empty, // LPIT0_Ch2 49
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isr_empty, // LPIT0_Ch3 50
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isr_empty, // PDB0 51
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isr_empty, // Reserved52 52
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isr_empty, // Reserved53 53
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isr_empty, // Reserved54 54
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isr_empty, // Reserved55 55
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isr_empty, // SCG 56
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isr_empty, // LPTMR0 57
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isr_empty, // PORTA 58
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isr_empty, // PORTB 59
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isr_empty, // PORTC 60
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isr_empty, // PORTD 61
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isr_empty, // PORTE 62
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isr_empty, // Reserved63 63
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isr_empty, // PDB1 64
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isr_empty, // FLEXIO 65
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isr_empty, // CAN0_ORed 66
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isr_empty, // CAN0_Error 67
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isr_empty, // CAN0_Wake_Up 68
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isr_empty, // CAN0_MB0_15 69
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isr_empty, // CAN0_MB16_31 70
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isr_empty, // FTM0_Ch0_Ch1 71
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isr_empty, // FTM0_Ch2_Ch3 72
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isr_empty, // FTM0_Ch4_Ch5 73
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isr_empty, // FTM0_Ch6_Ch7 74
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isr_empty, // FTM0_Fault 75
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isr_empty, // FTM0_Ovf_Reload 76
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isr_empty, // FTM1_Ch0_Ch1 77
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isr_empty, // FTM1_Ch2_Ch3 78
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isr_empty, // FTM1_Ch4_Ch5 79
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isr_empty, // FTM1_Ch6_Ch7 80
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isr_empty, // FTM1_Fault 81
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isr_empty, // FTM1_Ovf_Reload 82
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isr_empty, // FTM2_Ch0_Ch1 83
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isr_empty, // FTM2_Ch2_Ch3 84
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isr_empty, // FTM2_Ch4_Ch5 85
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isr_empty, // FTM2_Ch6_Ch7 86
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isr_empty, // FTM2_Fault 87
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isr_empty, // FTM2_Ovf_Reload 88
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#elif defined(STM32) /* For STM32 */
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isr_empty, // NVIC_WWDG_IRQ 0
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isr_empty, // PVD_IRQ 1
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isr_empty, // TAMP_STAMP_IRQ 2
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|
isr_empty, // RTC_WKUP_IRQ 3
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|
isr_empty, // FLASH_IRQ 4
|
|
isr_empty, // RCC_IRQ 5
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|
isr_empty, // EXTI0_IRQ 6
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isr_empty, // EXTI1_IRQ 7
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|
isr_empty, // EXTI2_IRQ 8
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|
isr_empty, // EXTI3_IRQ 9
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|
isr_empty, // EXTI4_IRQ 10
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|
isr_empty, // DMA1_STREAM0_IRQ 11
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|
isr_empty, // DMA1_STREAM1_IRQ 12
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|
isr_empty, // DMA1_STREAM2_IRQ 13
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|
isr_empty, // DMA1_STREAM3_IRQ 14
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|
isr_empty, // DMA1_STREAM4_IRQ 15
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|
isr_empty, // DMA1_STREAM5_IRQ 16
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|
isr_empty, // DMA1_STREAM6_IRQ 17
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|
isr_empty, // ADC_IRQ 18
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|
isr_empty, // CAN1_TX_IRQ 19
|
|
isr_empty, // CAN1_RX0_IRQ 20
|
|
isr_empty, // CAN1_RX1_IRQ 21
|
|
isr_empty, // CAN1_SCE_IRQ 22
|
|
isr_empty, // EXTI9_5_IRQ 23
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|
isr_empty, // TIM1_BRK_TIM9_IRQ 24
|
|
isr_empty, // TIM1_UP_TIM10_IRQ 25
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|
isr_empty, // TIM1_TRG_COM_TIM11_IRQ 26
|
|
isr_empty, // TIM1_CC_IRQ 27
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|
isr_tim2, // TIM2_IRQ 28
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|
isr_empty, // TIM3_IRQ 29
|
|
isr_empty, // TIM4_IRQ 30
|
|
isr_empty, // I2C1_EV_IRQ 31
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|
isr_empty, // I2C1_ER_IRQ 32
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|
isr_empty, // I2C2_EV_IRQ 33
|
|
isr_empty, // I2C2_ER_IRQ 34
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|
isr_empty, // SPI1_IRQ 35
|
|
isr_empty, // SPI2_IRQ 36
|
|
isr_empty, // USART1_IRQ 37
|
|
isr_empty, // USART2_IRQ 38
|
|
isr_empty, // USART3_IRQ 39
|
|
isr_empty, // EXTI15_10_IRQ 40
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|
isr_empty, // RTC_ALARM_IRQ 41
|
|
isr_empty, // USB_FS_WKUP_IRQ 42
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|
isr_empty, // TIM8_BRK_TIM12_IRQ 43
|
|
isr_empty, // TIM8_UP_TIM13_IRQ 44
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|
isr_empty, // TIM8_TRG_COM_TIM14_IRQ 45
|
|
isr_empty, // TIM8_CC_IRQ 46
|
|
isr_empty, // DMA1_STREAM7_IRQ 47
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|
|
|
#endif
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|
};
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