mirror of https://github.com/wolfSSL/wolfBoot.git
426 lines
18 KiB
C
426 lines
18 KiB
C
/* stm32n6.h
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*
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* Copyright (C) 2025 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef STM32N6_DEF_INCLUDED
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#define STM32N6_DEF_INCLUDED
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/* Assembly helpers */
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#ifndef DMB
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#define DMB() __asm__ volatile ("dmb")
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#endif
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#ifndef ISB
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#define ISB() __asm__ volatile ("isb")
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#endif
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#ifndef DSB
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#define DSB() __asm__ volatile ("dsb")
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#endif
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/* TrustZone secure/non-secure detection.
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* When compiled with -mcmse (TZEN=1) and not building the non-secure app,
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* TZ_SECURE() is 1 and we use secure peripheral aliases (0x5xxxxxxx).
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* Otherwise we use non-secure aliases (0x4xxxxxxx). */
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#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && \
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!defined(NONSECURE_APP))
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# define TZ_SECURE() (1)
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#else
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# define TZ_SECURE() (0)
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#endif
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/*** RCC (Reset and Clock Control) ***/
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#if TZ_SECURE()
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#define RCC_BASE (0x56028000UL) /* AHB4 secure */
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#else
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#define RCC_BASE (0x46028000UL) /* AHB4 non-secure */
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#endif
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/* RCC_CR: control register (read), CSR: set register, CCR: clear register */
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x000))
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#define RCC_CSR (*(volatile uint32_t *)(RCC_BASE + 0x800))
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#define RCC_CCR (*(volatile uint32_t *)(RCC_BASE + 0x1000))
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#define RCC_CR_LSION (1 << 0)
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#define RCC_CR_LSEON (1 << 1)
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#define RCC_CR_MSION (1 << 2)
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#define RCC_CR_HSION (1 << 3)
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#define RCC_CR_HSEON (1 << 4)
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#define RCC_CR_PLL1ON (1 << 8)
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#define RCC_CR_PLL2ON (1 << 9)
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#define RCC_CR_PLL3ON (1 << 10)
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#define RCC_CR_PLL4ON (1 << 11)
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/* RCC_SR: status register — ready flags */
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#define RCC_SR (*(volatile uint32_t *)(RCC_BASE + 0x04))
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#define RCC_SR_LSIRDY (1 << 0)
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#define RCC_SR_LSERDY (1 << 1)
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#define RCC_SR_MSIRDY (1 << 2)
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#define RCC_SR_HSIRDY (1 << 3)
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#define RCC_SR_HSERDY (1 << 4)
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#define RCC_SR_PLL1RDY (1 << 8)
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#define RCC_SR_PLL2RDY (1 << 9)
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#define RCC_SR_PLL3RDY (1 << 10)
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#define RCC_SR_PLL4RDY (1 << 11)
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/* RCC_CFGR1: clock switching */
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#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x20))
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#define RCC_CFGR1_CPUSW_SHIFT (16)
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#define RCC_CFGR1_CPUSW_MASK (0x3 << 16)
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#define RCC_CFGR1_CPUSWS_SHIFT (20)
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#define RCC_CFGR1_CPUSWS_MASK (0x3 << 20)
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#define RCC_CFGR1_SYSSW_SHIFT (24)
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#define RCC_CFGR1_SYSSW_MASK (0x3 << 24)
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#define RCC_CFGR1_SYSSWS_SHIFT (28)
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#define RCC_CFGR1_SYSSWS_MASK (0x3 << 28)
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/* RCC_CFGR2: AHB/APB prescalers */
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#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x24))
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#define RCC_CFGR2_PPRE1_SHIFT (0)
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#define RCC_CFGR2_PPRE1_MASK (0x7 << 0)
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#define RCC_CFGR2_PPRE2_SHIFT (4)
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#define RCC_CFGR2_PPRE2_MASK (0x7 << 4)
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#define RCC_CFGR2_PPRE4_SHIFT (12)
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#define RCC_CFGR2_PPRE4_MASK (0x7 << 12)
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#define RCC_CFGR2_PPRE5_SHIFT (16)
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#define RCC_CFGR2_PPRE5_MASK (0x7 << 16)
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#define RCC_CFGR2_HPRE_SHIFT (20)
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#define RCC_CFGR2_HPRE_MASK (0x7 << 20)
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/* PLL1 Configuration registers */
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#define RCC_PLL1CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x80))
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#define RCC_PLL1CFGR1_DIVN_SHIFT (8) /* bits [19:8]: VCO multiplication */
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#define RCC_PLL1CFGR1_DIVN_MASK (0xFFF << 8)
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#define RCC_PLL1CFGR1_DIVM_SHIFT (20) /* bits [25:20]: reference divider */
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#define RCC_PLL1CFGR1_DIVM_MASK (0x3F << 20)
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#define RCC_PLL1CFGR1_SEL_SHIFT (28) /* bits [30:28]: PLL source */
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#define RCC_PLL1CFGR1_SEL_MASK (0x7 << 28)
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#define RCC_PLL1CFGR1_BYP (1 << 27) /* PLL bypass (ref clock passthrough) */
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#define RCC_PLL1CFGR1_SEL_HSI (0x0 << 28)
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#define RCC_PLL1CFGR1_SEL_HSE (0x1 << 28)
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#define RCC_PLL1CFGR1_SEL_MSI (0x2 << 28)
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#define RCC_PLL1CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x84))
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/* PLL1CFGR2: fractional DIVN only (bits [23:0]) */
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#define RCC_PLL1CFGR3 (*(volatile uint32_t *)(RCC_BASE + 0x88))
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#define RCC_PLL1CFGR3_PDIV2_SHIFT (24) /* bits [26:24]: output post-divider 2 (1-7) */
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#define RCC_PLL1CFGR3_PDIV2_MASK (0x7 << 24)
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#define RCC_PLL1CFGR3_PDIV1_SHIFT (27) /* bits [29:27]: output post-divider 1 (1-7) */
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#define RCC_PLL1CFGR3_PDIV1_MASK (0x7 << 27)
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#define RCC_PLL1CFGR3_MODSSRST (1 << 0) /* spread spectrum modulation reset */
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#define RCC_PLL1CFGR3_MODSSDIS (1 << 2) /* spread spectrum disable */
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#define RCC_PLL1CFGR3_PDIVEN (1 << 30) /* post-divider + PLL output enable */
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/* IC (Interconnect Clock) dividers */
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#define RCC_IC1CFGR (*(volatile uint32_t *)(RCC_BASE + 0xC4))
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#define RCC_IC2CFGR (*(volatile uint32_t *)(RCC_BASE + 0xC8))
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#define RCC_IC3CFGR (*(volatile uint32_t *)(RCC_BASE + 0xCC))
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#define RCC_IC4CFGR (*(volatile uint32_t *)(RCC_BASE + 0xD0))
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#define RCC_IC5CFGR (*(volatile uint32_t *)(RCC_BASE + 0xD4))
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#define RCC_IC6CFGR (*(volatile uint32_t *)(RCC_BASE + 0xD8))
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#define RCC_IC7CFGR (*(volatile uint32_t *)(RCC_BASE + 0xDC))
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#define RCC_IC8CFGR (*(volatile uint32_t *)(RCC_BASE + 0xE0))
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#define RCC_IC9CFGR (*(volatile uint32_t *)(RCC_BASE + 0xE4))
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#define RCC_IC10CFGR (*(volatile uint32_t *)(RCC_BASE + 0xE8))
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#define RCC_IC11CFGR (*(volatile uint32_t *)(RCC_BASE + 0xEC))
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/* IC divider register fields:
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* ICxINT [23:16] = integer division factor
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* ICxSEL [29:28] = source: 0=PLL1, 1=PLL2, 2=PLL3, 3=PLL4
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*/
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#define RCC_ICCFGR_INT_SHIFT (16)
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#define RCC_ICCFGR_INT_MASK (0xFF << 16)
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#define RCC_ICCFGR_SEL_SHIFT (28)
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#define RCC_ICCFGR_SEL_MASK (0x3 << 28)
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#define RCC_ICCFGR_SEL_PLL1 (0x0 << 28)
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#define RCC_ICCFGR_SEL_PLL2 (0x1 << 28)
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#define RCC_ICCFGR_SEL_PLL3 (0x2 << 28)
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#define RCC_ICCFGR_SEL_PLL4 (0x3 << 28)
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/* Divider enable: direct, set (+0x800), clear (+0x1000) */
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#define RCC_DIVENR (*(volatile uint32_t *)(RCC_BASE + 0x240))
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#define RCC_DIVENSR (*(volatile uint32_t *)(RCC_BASE + 0xA40))
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#define RCC_DIVENCR (*(volatile uint32_t *)(RCC_BASE + 0x1240))
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#define RCC_DIVENR_IC1EN (1 << 0)
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#define RCC_DIVENR_IC2EN (1 << 1)
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#define RCC_DIVENR_IC3EN (1 << 2)
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#define RCC_DIVENR_IC4EN (1 << 3)
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#define RCC_DIVENR_IC5EN (1 << 4)
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#define RCC_DIVENR_IC6EN (1 << 5)
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#define RCC_DIVENR_IC11EN (1 << 10)
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/* Clock enable registers */
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#define RCC_MISCENR (*(volatile uint32_t *)(RCC_BASE + 0x248))
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#define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x250))
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#define RCC_AHB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x254))
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#define RCC_AHB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x258))
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#define RCC_AHB4ENR (*(volatile uint32_t *)(RCC_BASE + 0x25C))
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#define RCC_AHB5ENR (*(volatile uint32_t *)(RCC_BASE + 0x260))
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#define RCC_APB1ENR1 (*(volatile uint32_t *)(RCC_BASE + 0x264))
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#define RCC_APB1ENR2 (*(volatile uint32_t *)(RCC_BASE + 0x268))
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x26C))
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#define RCC_APB4ENR1 (*(volatile uint32_t *)(RCC_BASE + 0x274))
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#define RCC_APB5ENR (*(volatile uint32_t *)(RCC_BASE + 0x27C))
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/* GPIO clock enable bits in RCC_AHB4ENR */
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#define RCC_AHB4ENR_GPIOAEN (1 << 0)
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#define RCC_AHB4ENR_GPIOBEN (1 << 1)
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#define RCC_AHB4ENR_GPIOCEN (1 << 2)
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#define RCC_AHB4ENR_GPIODEN (1 << 3)
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#define RCC_AHB4ENR_GPIOEEN (1 << 4)
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#define RCC_AHB4ENR_GPIOFEN (1 << 5)
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#define RCC_AHB4ENR_GPIOGEN (1 << 6)
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#define RCC_AHB4ENR_GPIOHEN (1 << 7)
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#define RCC_AHB4ENR_GPIONEN (1 << 13)
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#define RCC_AHB4ENR_GPIOOEN (1 << 14)
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#define RCC_AHB4ENR_GPIOPEN (1 << 15)
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#define RCC_AHB4ENR_GPIOQEN (1 << 16)
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#define RCC_AHB4ENR_PWREN (1 << 18)
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/* XSPI clock enable in RCC_AHB5ENR */
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#define RCC_AHB5ENR_XSPI1EN (1 << 5)
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#define RCC_AHB5ENR_XSPI2EN (1 << 12)
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#define RCC_AHB5ENR_XSPIMEN (1 << 13)
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/* XSPI PHY compensation clock in RCC_MISCENR */
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#define RCC_MISCENR_XSPIPHYCOMPEN (1 << 3)
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/* USART clock enable */
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#define RCC_APB2ENR_USART1EN (1 << 4)
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/*** PWR (Power Control) — base 0x56024800 (secure) ***/
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#if TZ_SECURE()
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#define PWR_BASE (0x56024800UL) /* secure */
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#else
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#define PWR_BASE (0x46024800UL) /* non-secure */
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#endif
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#define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
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#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
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#define PWR_CR3 (*(volatile uint32_t *)(PWR_BASE + 0x08))
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#define PWR_CR4 (*(volatile uint32_t *)(PWR_BASE + 0x0C))
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#define PWR_VOSCR (*(volatile uint32_t *)(PWR_BASE + 0x20))
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/* PWR_VOSCR: Voltage scaling controls max CPU frequency.
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* Scale 1 (VOS=0, default): up to 600 MHz CPU.
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* Scale 0 (VOS=1): up to 800 MHz CPU. */
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#define PWR_VOSCR_VOS (1 << 0)
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#define PWR_VOSCR_VOSRDY (1 << 1)
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/* PWR Supply Voltage Monitoring Control Registers */
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#define PWR_SVMCR1 (*(volatile uint32_t *)(PWR_BASE + 0x34))
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#define PWR_SVMCR2 (*(volatile uint32_t *)(PWR_BASE + 0x38))
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#define PWR_SVMCR3 (*(volatile uint32_t *)(PWR_BASE + 0x3C))
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/* SVMCR1: VDDIO4 supply valid (bit 8) */
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#define PWR_SVMCR1_VDDIO4SV (1 << 8)
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/* SVMCR2: VDDIO5 supply valid (bit 8) */
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#define PWR_SVMCR2_VDDIO5SV (1 << 8)
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/* SVMCR3: VDDIO2 supply valid (bit 8), VDDIO3 supply valid (bit 9).
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* VDDIOxVRSEL: 0 = 3.3V range, 1 = 1.8V range (must match physical supply). */
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#define PWR_SVMCR3_VDDIO2SV (1 << 8)
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#define PWR_SVMCR3_VDDIO3SV (1 << 9)
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#define PWR_SVMCR3_VDDIOVRSEL (1 << 24)
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#define PWR_SVMCR3_VDDIO2VRSEL (1 << 25)
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#define PWR_SVMCR3_VDDIO3VRSEL (1 << 26)
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/* RCC AHB5 reset registers (set = assert, clear = release) */
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#define RCC_AHB5RSTSR (*(volatile uint32_t *)(RCC_BASE + 0xA20))
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#define RCC_AHB5RSTCR (*(volatile uint32_t *)(RCC_BASE + 0x1220))
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#define RCC_AHB5RSTR_XSPI2RST (1 << 12)
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#define RCC_AHB5RSTR_XSPIMRST (1 << 14)
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/*** GPIO ***/
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#if TZ_SECURE()
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#define GPIOA_BASE (0x56020000UL)
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#define GPIOB_BASE (0x56020400UL)
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#define GPIOC_BASE (0x56020800UL)
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#define GPIOD_BASE (0x56020C00UL)
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#define GPIOE_BASE (0x56021000UL)
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#define GPIOF_BASE (0x56021400UL)
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#define GPIOG_BASE (0x56021800UL)
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#define GPIOH_BASE (0x56021C00UL)
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#define GPION_BASE (0x56023400UL)
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#define GPIOO_BASE (0x56023800UL)
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#define GPIOP_BASE (0x56023C00UL)
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#define GPIOQ_BASE (0x56024000UL)
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#else
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#define GPIOA_BASE (0x46020000UL)
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#define GPIOB_BASE (0x46020400UL)
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#define GPIOC_BASE (0x46020800UL)
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#define GPIOD_BASE (0x46020C00UL)
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#define GPIOE_BASE (0x46021000UL)
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#define GPIOF_BASE (0x46021400UL)
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#define GPIOG_BASE (0x46021800UL)
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#define GPIOH_BASE (0x46021C00UL)
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#define GPION_BASE (0x46023400UL)
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#define GPIOO_BASE (0x46023800UL)
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#define GPIOP_BASE (0x46023C00UL)
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#define GPIOQ_BASE (0x46024000UL)
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#endif
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/* GPIO register offsets — GPIO_ODR, GPIO_BSRR, GPIO_MODE_* come from
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* spi_drv_stm32.h. Define the rest that aren't in the shared header. */
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#define GPIO_MODER(base) (*(volatile uint32_t *)((base) + 0x00))
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#define GPIO_OTYPER(base) (*(volatile uint32_t *)((base) + 0x04))
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#define GPIO_OSPEEDR(base) (*(volatile uint32_t *)((base) + 0x08))
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#define GPIO_PUPDR(base) (*(volatile uint32_t *)((base) + 0x0C))
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#define GPIO_IDR(base) (*(volatile uint32_t *)((base) + 0x10))
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#define GPIO_AFRL(base) (*(volatile uint32_t *)((base) + 0x20))
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#define GPIO_AFRH(base) (*(volatile uint32_t *)((base) + 0x24))
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/* GPIO speed values */
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#define GPIO_SPEED_LOW 0x0
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#define GPIO_SPEED_MEDIUM 0x1
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#define GPIO_SPEED_HIGH 0x2
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#define GPIO_SPEED_VERY_HIGH 0x3
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/*** OCTOSPI (XSPI2) — register definitions from hal/spi/spi_drv_stm32.h ***/
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/* Set base address before including shared OCTOSPI register macros.
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* STM32N6 XSPI2 uses the same IP block as OCTOSPI (identical register layout).
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*/
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/* XSPI2 controller registers: accessed via the NS alias regardless of
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* TZ state. The XSPI2 peripheral is left non-secure by the Boot ROM
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* (RIFSC.RISC_SECCFGR2 bit 23 = 0); accessing it via the secure alias
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* fails. Both wolfBoot (running Secure) and the NS application drive
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* the same controller through 0x4802xxxx -- a secure CPU's access to
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* an NS peripheral via the NS alias is permitted. */
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#define OCTOSPI_BASE (0x4802A000UL) /* AHB5 non-secure */
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#define OCTOSPI_MEM_BASE (0x70000000UL) /* XSPI2 mmap, S-IDAU alias */
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#define OCTOSPI_MEM_BASE_NS (0x90000000UL)
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#define OCTOSPI_MEM_BASE_S (0x70000000UL)
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#define OCTOSPI_MEM_SIZE (0x04000000UL) /* 64 MB */
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#include "hal/spi/spi_drv_stm32.h"
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/* OCTOSPI bits not defined in spi_drv_stm32.h */
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#define OCTOSPI_CR_FMODE_MMAP OCTOSPI_CR_FMODE(3) /* Memory-mapped mode */
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#define OCTOSPI_SR_TEF (1 << 0) /* Transfer Error Flag */
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#define OCTOSPI_FCR_CTEF (1 << 0) /* Clear Transfer Error Flag */
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#define OCTOSPI_FCR_CTCF (1 << 1) /* Clear Transfer Complete Flag */
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#define OCTOSPI_FCR_CSMF (1 << 3) /* Clear Status Match Flag */
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#define OCTOSPI_DCR1_DLYBYP (1 << 3) /* Bypass delay block (N6-specific) */
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/*** XSPI1 (control register only -- we use it to gate XSPIM_CR writes) ***/
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#if TZ_SECURE()
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#define XSPI1_BASE (0x58025000UL)
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#else
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#define XSPI1_BASE (0x48025000UL)
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#endif
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#define XSPI1_CR (*(volatile uint32_t *)(XSPI1_BASE + 0x00))
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#define XSPI_CR_EN (1 << 0)
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/*** XSPIM (XSPI I/O Manager) ***/
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#define XSPIM_BASE (0x5802B400UL)
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#define XSPIM_CR (*(volatile uint32_t *)(XSPIM_BASE + 0x00))
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/*** NOR Flash Commands (Macronix MX25UM51245G) ***/
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/* Same commands as src/qspi_flash.c, using 4-byte address variants
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* (0x0C/0x12/0x21) instead of entering 4-byte address mode. */
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#define WRITE_ENABLE_CMD 0x06U
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#define READ_SR_CMD 0x05U
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#define FAST_READ_4B_CMD 0x0CU
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#define PAGE_PROG_4B_CMD 0x12U
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#define SEC_ERASE_4B_CMD 0x21U /* 4KB sector erase, 4-byte addr */
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#define RESET_ENABLE_CMD 0x66U
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#define RESET_MEMORY_CMD 0x99U
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/* NOR flash status register bits */
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#define FLASH_SR_BUSY (1 << 0) /* Write-in-progress */
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#define FLASH_SR_WRITE_EN (1 << 1) /* Write enable latch */
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/* NOR flash geometry */
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#define FLASH_PAGE_SIZE 256
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#define FLASH_SECTOR_SIZE 0x1000 /* 4KB */
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#define FLASH_DEVICE_SIZE (64 * 1024 * 1024) /* 64MB */
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#define FLASH_DEVICE_SIZE_LOG2 26 /* DEVSIZE: 2^26 = 64MB */
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/*** USART — parameterized by base address ***/
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#if TZ_SECURE()
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#define USART1_BASE (0x52001000UL) /* APB2 secure */
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#else
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#define USART1_BASE (0x42001000UL) /* APB2 non-secure */
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#endif
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#define UART_CR1(base) (*(volatile uint32_t *)((base) + 0x00))
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#define UART_CR2(base) (*(volatile uint32_t *)((base) + 0x04))
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#define UART_CR3(base) (*(volatile uint32_t *)((base) + 0x08))
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#define UART_BRR(base) (*(volatile uint32_t *)((base) + 0x0C))
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#define UART_ISR(base) (*(volatile uint32_t *)((base) + 0x1C))
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#define UART_ICR(base) (*(volatile uint32_t *)((base) + 0x20))
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#define UART_RDR(base) (*(volatile uint32_t *)((base) + 0x24))
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#define UART_TDR(base) (*(volatile uint32_t *)((base) + 0x28))
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#define USART_CR1_UE (1 << 0)
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#define USART_CR1_RE (1 << 2)
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#define USART_CR1_TE (1 << 3)
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#define USART_CR1_OVER8 (1 << 15)
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#define USART_ISR_TXE (1 << 7)
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#define USART_ISR_RXNE (1 << 5)
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#define USART_ISR_TC (1 << 6)
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/*** SCB (System Control Block) — Cortex-M55 cache control ***/
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#define SCB_BASE (0xE000ED00UL)
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#define SCB_CCR (*(volatile uint32_t *)(SCB_BASE + 0x14))
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#define SCB_CCR_IC (1 << 17)
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#define SCB_CCR_DC (1 << 16)
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/* Cache maintenance (Cortex-M55 uses standard ARM CMSIS-like registers) */
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#define SCB_ICIALLU (*(volatile uint32_t *)(0xE000EF50UL))
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#define SCB_DCIMVAC (*(volatile uint32_t *)(0xE000EF5CUL))
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#define SCB_DCISW (*(volatile uint32_t *)(0xE000EF60UL))
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#define SCB_DCCMVAU (*(volatile uint32_t *)(0xE000EF64UL))
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#define SCB_DCCMVAC (*(volatile uint32_t *)(0xE000EF68UL))
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#define SCB_DCCSW (*(volatile uint32_t *)(0xE000EF6CUL))
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#define SCB_DCCIMVAC (*(volatile uint32_t *)(0xE000EF70UL))
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#define SCB_DCCISW (*(volatile uint32_t *)(0xE000EF74UL))
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/* SAU registers defined in hal/armv8m_tz.h */
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/* Cache size ID registers */
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#define CCSIDR (*(volatile uint32_t *)(0xE000ED80UL))
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#define CSSELR (*(volatile uint32_t *)(0xE000ED84UL))
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/*** AIRCR (Application Interrupt and Reset Control) ***/
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#define AIRCR (*(volatile uint32_t *)(0xE000ED0CUL))
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#define AIRCR_VKEY (0x05FA << 16)
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#define AIRCR_SYSRESETREQ (1 << 2)
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/*** SysTick ***/
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#define SYSTICK_BASE (0xE000E010UL)
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#define SYSTICK_CSR (*(volatile uint32_t *)(SYSTICK_BASE + 0x00))
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#define SYSTICK_RVR (*(volatile uint32_t *)(SYSTICK_BASE + 0x04))
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#define SYSTICK_CVR (*(volatile uint32_t *)(SYSTICK_BASE + 0x08))
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/*** SRAM regions ***/
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#define AXISRAM1_BASE (0x34000000UL)
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#define AXISRAM2_BASE (0x34180400UL)
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#define AXISRAM3_BASE (0x34200000UL)
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#define AXISRAM4_BASE (0x34270000UL)
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#define AXISRAM5_BASE (0x342E0000UL)
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#define AXISRAM6_BASE (0x34350000UL)
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#endif /* STM32N6_DEF_INCLUDED */
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