mirror of https://github.com/wolfSSL/wolfBoot.git
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/* startup_riscv.c
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*
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* Copyright (C) 2020 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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extern void trap_entry(void);
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extern void trap_exit(void);
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extern uint32_t _start_vector;
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extern uint32_t _stored_data;
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extern uint32_t _start_data;
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extern uint32_t _end_data;
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extern uint32_t _start_bss;
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extern uint32_t _end_bss;
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extern uint32_t _end_stack;
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extern uint32_t _start_heap;
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extern uint32_t _global_pointer;
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extern void (* const IV[])(void);
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extern void main(void);
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void __attribute__((naked,section(".init"))) _reset(void) {
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register uint32_t *src, *dst;
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asm volatile("la gp, _global_pointer");
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asm volatile("la sp, _end_stack");
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/* Set up vectored interrupt, with IV starting at offset 0x100 */
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asm volatile("csrw mtvec, %0":: "r"((uint8_t *)(&_start_vector) + 1));
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src = (uint32_t *) &_stored_data;
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dst = (uint32_t *) &_start_data;
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/* Copy the .data section from flash to RAM. */
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while (dst < (uint32_t *)&_end_data) {
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*dst = *src;
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dst++;
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src++;
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}
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/* Initialize the BSS section to 0 */
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dst = &_start_bss;
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while (dst < (uint32_t *)&_end_bss) {
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*dst = 0U;
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dst++;
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}
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/* Run wolfboot */
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main();
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while(1)
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;
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}
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void do_boot(const uint32_t *app_offset)
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{
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}
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static uint32_t synctrap_cause = 0;
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void __attribute__((naked)) isr_synctrap(void)
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{
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asm volatile("csrr %0,mcause" : "=r"(synctrap_cause));
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//asm volatile("ebreak");
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}
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void isr_empty(void)
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{
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}
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