mirror of https://github.com/wolfSSL/wolfBoot.git
148 lines
4.0 KiB
C
148 lines
4.0 KiB
C
/* system.c
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*
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* Test bare-metal blinking led application
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*
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* Copyright (C) 2020 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#if defined(PLATFORM_stm32f4) || defined(PLATFORM_stm32f7)
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#include <stdint.h>
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#include "system.h"
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/*** FLASH ***/
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#define FLASH_BASE (0x40023C00)
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_ACR_ENABLE_DATA_CACHE (1 << 10)
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#define FLASH_ACR_ENABLE_INST_CACHE (1 << 9)
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/*** RCC ***/
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#define RCC_BASE (0x40023800)
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
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#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x04))
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#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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#define RCC_CFGR_SW_HSI 0x0
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#define RCC_CFGR_SW_HSE 0x1
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#define RCC_CFGR_SW_PLL 0x2
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#define RCC_PLLCFGR_PLLSRC (1 << 22)
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#define RCC_PRESCALER_DIV_NONE 0
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#define RCC_PRESCALER_DIV_2 8
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#define RCC_PRESCALER_DIV_4 9
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/* STM32F4-Discovery, 168 MHz */
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#ifdef PLATFORM_stm32f4
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# define PLLM 8
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# define PLLN 336
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# define PLLP 2
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# define PLLQ 7
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# define PLLR 0
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# define TARGET_FLASH_WAITSTATES 5
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#endif
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/* STM32F7-Discovery, 216 MHz */
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#ifdef PLATFORM_stm32f7
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# define PLLM 25
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# define PLLN 432
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# define PLLP 2
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# define PLLQ 9
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# define PLLR 0
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# define TARGET_FLASH_WAITSTATES 7
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#endif
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void flash_set_waitstates(void)
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{
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FLASH_ACR |= TARGET_FLASH_WAITSTATES | FLASH_ACR_ENABLE_DATA_CACHE | FLASH_ACR_ENABLE_INST_CACHE;
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}
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void clock_config(void)
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{
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uint32_t reg32;
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/* Enable internal high-speed oscillator. */
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RCC_CR |= RCC_CR_HSION;
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DMB();
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while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
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/* Select HSI as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
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DMB();
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/* Enable external high-speed oscillator 8MHz. */
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RCC_CR |= RCC_CR_HSEON;
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DMB();
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while ((RCC_CR & RCC_CR_HSERDY) == 0) {};
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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*/
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reg32 = RCC_CFGR;
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reg32 &= ~(0xF0);
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RCC_CFGR = (reg32 | (RCC_PRESCALER_DIV_NONE << 4));
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(0x1C00);
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RCC_CFGR = (reg32 | (RCC_PRESCALER_DIV_2 << 10));
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(0x07 << 13);
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RCC_CFGR = (reg32 | (RCC_PRESCALER_DIV_4 << 13));
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DMB();
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/* Set PLL config */
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(PLL_FULL_MASK);
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RCC_PLLCFGR = reg32 | RCC_PLLCFGR_PLLSRC | PLLM |
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(PLLN << 6) | (((PLLP >> 1) - 1) << 16) |
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(PLLQ << 24);
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DMB();
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/* Enable PLL oscillator and wait for it to stabilize. */
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RCC_CR |= RCC_CR_PLLON;
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DMB();
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while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
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/* Select PLL as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
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DMB();
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/* Wait for PLL clock to be selected. */
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
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/* Disable internal high-speed oscillator. */
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RCC_CR &= ~RCC_CR_HSION;
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}
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#endif /* PLATFORM_stm32f4 */
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