mirror of https://github.com/wolfSSL/wolfBoot.git
128 lines
3.5 KiB
C
128 lines
3.5 KiB
C
/* spi_drv.h
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*
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* Driver for the SPI back-end of the SPI_FLASH module.
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*
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* * Compile with SPI_FLASH=1
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* * Define your platform specific SPI driver in spi_drv_$PLATFORM.c,
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* implementing the spi_ calls below.
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*
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*
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* Copyright (C) 2022 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef SPI_DRV_H_INCLUDED
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#define SPI_DRV_H_INCLUDED
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#include <stdint.h>
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#include "image.h"
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/* SPI transfer flags */
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#define SPI_XFER_FLAG_NONE 0x0
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#define SPI_XFER_FLAG_CONTINUE 0x1 /* keep CS asserted */
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#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM) || defined(QSPI_FLASH) || \
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defined(OCTOSPI_FLASH)
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#if defined(TARGET_stm32f4) || defined(TARGET_stm32f7) || \
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defined(TARGET_stm32wb) || defined(TARGET_stm32l0) || \
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defined(TARGET_stm32u5) || defined(TARGET_stm32h7)
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#define WOLFBOOT_STM32_SPIDRV
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#include "hal/spi/spi_drv_stm32.h"
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#endif
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#if defined(TARGET_zynq)
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#include "hal/spi/spi_drv_zynq.h"
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#endif
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#if defined(TARGET_nrf52)
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#include "hal/spi/spi_drv_nrf52.h"
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#endif
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#if defined(TARGET_nrf5340)
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#include "hal/spi/spi_drv_nrf5340.h"
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#endif
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#if defined(TARGET_nxp_p1021) || defined(TARGET_nxp_t1024) || \
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defined(TARGET_nxp_ls1028a)
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#include "hal/spi/spi_drv_nxp.h"
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#endif
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#if defined(WOLFBOOT_ARCH_RENESAS_RX)
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#include "hal/spi/spi_drv_renesas_rx.h"
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#endif
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void spi_init(int polarity, int phase);
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void spi_release(void);
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#ifdef SPI_FLASH
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void spi_cs_on(uint32_t base, int pin);
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void spi_cs_off(uint32_t base, int pin);
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void spi_write(const char byte);
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uint8_t spi_read(void);
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#endif
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#ifdef WOLFBOOT_TPM
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/* Perform a SPI transaction.
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* Set flags == SPI_XFER_FLAG_CONTINUE to keep CS asserted after transfer. */
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int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags);
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#endif
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#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
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#define QSPI_MODE_WRITE 0
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#define QSPI_MODE_READ 1
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/* these are used in macro logic, so must be defines */
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#define QSPI_DATA_MODE_NONE 0
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#define QSPI_DATA_MODE_SPI 1
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#define QSPI_DATA_MODE_DSPI 2
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#define QSPI_DATA_MODE_QSPI 3
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/* QSPI Configuration */
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#ifndef QSPI_ADDR_MODE /* address uses single SPI mode */
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#define QSPI_ADDR_MODE QSPI_DATA_MODE_SPI
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#endif
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#ifndef QSPI_ADDR_SZ /* default to 24-bit address */
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#define QSPI_ADDR_SZ 3
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#endif
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#ifndef QSPI_DATA_MODE /* data defaults to Quad mode */
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#define QSPI_DATA_MODE QSPI_DATA_MODE_QSPI
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#endif
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int qspi_transfer(uint8_t fmode, const uint8_t cmd,
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uint32_t addr, uint32_t addrSz, uint32_t addrMode,
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uint32_t alt, uint32_t altSz, uint32_t altMode,
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uint32_t dummySz,
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uint8_t* data, uint32_t dataSz, uint32_t dataMode
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);
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#endif /* QSPI_FLASH || OCTOSPI_FLASH */
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#ifndef SPI_CS_FLASH
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#define SPI_CS_FLASH 0
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#endif
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#ifndef SPI_CS_PIO_BASE
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#define SPI_CS_PIO_BASE 0UL
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#endif
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#endif /* SPI_FLASH || WOLFBOOT_TPM || QSPI_FLASH || OCTOSPI_FLASH */
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#endif /* !SPI_DRV_H_INCLUDED */
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