mirror of https://github.com/wolfSSL/wolfBoot.git
477 lines
16 KiB
C
477 lines
16 KiB
C
/* sama5d3.h
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*
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* Header file for SAMA5D3 HAL
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef SAMA5D3_HAL_H
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#define SAMA5D3_HAL_H
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#include <stdint.h>
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/* CPU/Board clock settings */
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#define CPU_FREQ 264000000UL
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#define MASTER_FREQ 132000000UL
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#define CRYSTAL_FREQ 12000000UL
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#define MULA 43
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/* PLLA register
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*/
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#define PLLA_DIVA_SHIFT 0
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#define PLLA_DIVA_MASK (0xFF << PLLA_DIVA_SHIFT)
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#define PLLA_COUNT_SHIFT 8
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#define PLLA_COUNT_MASK (0x3F << PLLA_COUNT_SHIFT)
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#define PLLA_CKGR_OUTA_SHIFT 14
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#define PLLA_CKGR_OUTA_MASK (0x3 << PLLA_CKGR_OUTA_SHIFT)
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#define PLLA_MULA_SHIFT 18
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#define PLLA_MULA_MASK (0x7F << PLLA_MULA_SHIFT)
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#define PLLA_CKGR_SRCA (0x1 << 29)
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/* PMC version 1 */
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#define PMC_BASE 0xFFFFFC00
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#define PMC_SCER *(volatile uint32_t *)(PMC_BASE + 0x0000)
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#define PMC_UCKR *(volatile uint32_t *)(PMC_BASE + 0x001C)
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#define PMC_PLLA *(volatile uint32_t *)(PMC_BASE + 0x0028)
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#define PMC_MCKR *(volatile uint32_t *)(PMC_BASE + 0x0030)
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#define PMC_SR *(volatile uint32_t *)(PMC_BASE + 0x0068)
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#define PMC_PLLICPR *(volatile uint32_t *)(PMC_BASE + 0x0080)
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#define PMC_PCR *(volatile uint32_t *)(PMC_BASE + 0x010C)
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#define PMC_PLLADIV_SHIFT 12
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#define PMC_PLLADIV_MASK (0x1 << PMC_PLLADIV_SHIFT)
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#define PMC_PLLADIV_1 (0x0 << PMC_PLLADIV_SHIFT)
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#define PMC_PLLADIV_2 (0x1 << PMC_PLLADIV_SHIFT)
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#define PMC_CSS_SHIFT 0
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#define PMC_CSS_MASK (0x3 << PMC_CSS_SHIFT)
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#define PMC_CSS_SLOW_CLK (0x0 << PMC_CSS_SHIFT)
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#define PMC_CSS_MAIN_CLK (0x1 << PMC_CSS_SHIFT)
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#define PMC_CSS_PLLA_CLK (0x2 << PMC_CSS_SHIFT)
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#define PMC_CSS_UPLL_CLK (0x3 << PMC_CSS_SHIFT)
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#define PMC_PRES_SHIFT 2
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#define PMC_PRES_MASK (0xF << PMC_PRES_SHIFT)
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#define PMC_ALTPRES_SHIFT 4
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#define PMC_ALTPRES_MASK (0xF << PMC_ALTPRES_SHIFT)
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#define PMC_MDIV_SHIFT 8
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#define PMC_MDIV_MASK (0x3 << PMC_MDIV_SHIFT)
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#define PMC_MDIV_1 (0x0 << PMC_MDIV_SHIFT)
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#define PMC_MDIV_2 (0x1 << PMC_MDIV_SHIFT)
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#define PMC_MDIV_3 (0x2 << PMC_MDIV_SHIFT)
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#define PMC_MDIV_4 (0x3 << PMC_MDIV_SHIFT)
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#define PMC_H32MXDIV_SHIFT 24
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#define PMC_H32MXDIV_MASK (0x1 << PMC_H32MXDIV_SHIFT)
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#define PMC_SR_LOCKA (0x1 << 1)
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#define PMC_SR_MCKRDY (0x1 << 3)
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#define PMC_PLLICPR_ICPPLLA_SHIFT 0
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#define PMC_PLLICPR_ICPPLLA_MASK (0x7 << PMC_PLLICPR_ICPPLLA_SHIFT)
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#define PMC_PLLICPR_IPLLA_SHIFT 8
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#define PMC_PLLICPR_IPLLA_MASK (0xF << PMC_PLLICPR_IPLLA_SHIFT)
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#define PMC_PCR_CMD (0x1 << 12)
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#define PMC_PCR_EN (0x1 << 28)
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#define PMC_PCR_DIV_SHIFT 13
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#define PMC_PCR_DIV_MASK (0x3 << PMC_PCR_DIV_SHIFT)
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/* Specific configuration for 264/132/12 MHz */
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#define PLL_PCK (((CRYSTAL_FREQ * (PLLA_MULA + 1)) / 2))
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#define PLL_MCK (BOARD_PCK / 2)
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#define PLL_CKGR_PLLA (PLLA_CKGR_SRCA | (0 << PLLA_CKGR_OUTA_SHIFT))
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#define PLL_PLLACOUNT (PLLA_COUNT_MASK)
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#define PLL_MULA ((MULA << PLLA_MULA_SHIFT) & PLLA_MULA_MASK)
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#define PLL_DIVA (0x01 & PLLA_DIVA_MASK)
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#define PLLA_CONFIG (PLL_CKGR_PLLA | PLL_PLLACOUNT | PLL_MULA | PLL_DIVA)
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#define PRESCALER_MAIN_CLOCK (PMC_PLLADIV_2 | PMC_MDIV_2 | PMC_CSS_MAIN_CLK)
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#define PRESCALER_PLLA_CLOCK (PMC_PLLADIV_2 | PMC_MDIV_2 | PMC_CSS_PLLA_CLK)
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#define PLLICPR_CONFIG (0x0 << PMC_PLLICPR_ICPPLLA_SHIFT | 0x3 << PMC_PLLICPR_IPLLA_SHIFT)
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/* DBGU
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*
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*/
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#define DBGU_BASE 0xFFFFEE00
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#define DBGU_CR *(volatile uint32_t *)(DBGU_BASE + 0x00)
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#define DBGU_BRGR *(volatile uint32_t *)(DBGU_BASE + 0x20)
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#define DBGU_CR_RXEN (1 << 4)
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#define DBGU_CR_TXEN (1 << 6)
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#define DBGU_PMCID 0x02 /* dec: 2 for SAMA5D3 */
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/* Associated pins : GPIOB 30 - 31*/
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#define DBGU_PIN_RX 30
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#define DBGU_PIN_TX 31
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#define DBGU_GPIO GPIOB
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/* PIT
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*
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*/
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#define PIT_BASE 0xFFFFFE30
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#define PIT_MR *(volatile uint32_t *)(PIT_BASE + 0x00)
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#define PIT_SR *(volatile uint32_t *)(PIT_BASE + 0x04)
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#define PIT_PIVR *(volatile uint32_t *)(PIT_BASE + 0x08)
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#define PIT_PIIR *(volatile uint32_t *)(PIT_BASE + 0x0C)
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/* DRAM setup
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*
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*/
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#define MPDDRC_BASE 0xFFFFEA00
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#define MPDDRC_MR *(volatile uint32_t *)(MPDDRC_BASE + 0x00) /* Mode Register */
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#define MPDDRC_RTR *(volatile uint32_t *)(MPDDRC_BASE + 0x04) /* Refresh Timer Register */
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#define MPDDRC_CR *(volatile uint32_t *)(MPDDRC_BASE + 0x08) /* Configuration Register */
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#define MPDDRC_TPR0 *(volatile uint32_t *)(MPDDRC_BASE + 0x0C) /* Timing Parameter 0 Register */
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#define MPDDRC_TPR1 *(volatile uint32_t *)(MPDDRC_BASE + 0x10) /* Timing Parameter 1 Register */
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#define MPDDRC_TPR2 *(volatile uint32_t *)(MPDDRC_BASE + 0x14) /* Timing Parameter 2 Register */
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/* Reserved 0x18 */
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#define MPDDRC_LPR *(volatile uint32_t *)(MPDDRC_BASE + 0x1C) /* Low-power Register */
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#define MPDDRC_MD *(volatile uint32_t *)(MPDDRC_BASE + 0x20) /* Memory Device Register */
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#define MPDDRC_HS *(volatile uint32_t *)(MPDDRC_BASE + 0x24) /* High Speed Register */
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#define MPDDRC_LPDDR2_LPR *(volatile uint32_t *)(MPDDRC_BASE + 0x28) /* LPDDR2 Low-power Register */
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#define MPDDRC_LPDDR2_CAL_MR4 *(volatile uint32_t *)(MPDDRC_BASE + 0x2C) /* LPDDR2 Calibration and MR4 Register */
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#define MPDDRC_LPDDR2_TIM_CAL *(volatile uint32_t *)(MPDDRC_BASE + 0x30) /* LPDDR2 Timing Calibration Register */
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#define MPDDRC_IO_CALIBR *(volatile uint32_t *)(MPDDRC_BASE + 0x34) /* I/O Calibration Register */
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#define MPDDRC_OCMS *(volatile uint32_t *)(MPDDRC_BASE + 0x38) /* OCMS Register */
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#define MPDDRC_OCMS_KEY1 *(volatile uint32_t *)(MPDDRC_BASE + 0x3C) /* OCMS Key 1 Register */
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#define MPDDRC_OCMS_KEY2 *(volatile uint32_t *)(MPDDRC_BASE + 0x40) /* OCMS Key 2 Register */
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/* Reserved 0x44 to 0x58 */
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#define MPDDRC_RD_DATA_PATH *(volatile uint32_t *)(MPDDRC_BASE + 0x5C) /* Read Data Path Register */
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/* Reserved 0x60 to 0x70 */
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#define MPDDRC_DLL_MO *(volatile uint32_t *)(MPDDRC_BASE + 0x74) /* DLL Master Offset Register */
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#define MPDDRC_DLL_SOF *(volatile uint32_t *)(MPDDRC_BASE + 0x78) /* DLL Slave Offset Register */
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#define MPDDRC_DLL_MS *(volatile uint32_t *)(MPDDRC_BASE + 0x7C) /* DLL Master Status Register */
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#define MPDDRC_DLL_SS0 *(volatile uint32_t *)(MPDDRC_BASE + 0x80) /* DLL Slave 0 Status Register */
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#define MPDDRC_DLL_SS1 *(volatile uint32_t *)(MPDDRC_BASE + 0x84) /* DLL Slave 1 Status Register */
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#define MPDDRC_DLL_SS2 *(volatile uint32_t *)(MPDDRC_BASE + 0x88) /* DLL Slave 2 Status Register */
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#define MPDDRC_DLL_SS3 *(volatile uint32_t *)(MPDDRC_BASE + 0x8C) /* DLL Slave 3 Status Register */
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/* Reserved 0x90 to 0xE0 */
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#define MPDDRC_WPMR *(volatile uint32_t *)(MPDDRC_BASE + 0xE4) /* Write Protection Mode Register */
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#define MPDDRC_WPSR *(volatile uint32_t *)(MPDDRC_BASE + 0xE8) /* Write Protection Status Register */
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/* MPDDRC_CR: shift, mask, values */
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#define MPDDRC_NC_SHIFT 0 /* Number of Column Bits */
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#define MPDDRC_NC_MASK (0x3 << MPDDRC_NC_SHIFT)
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#define MPDDRC_NC_9 (0x0 << MPDDRC_NC_SHIFT)
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#define MPDDRC_NC_10 (0x1 << MPDDRC_NC_SHIFT)
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#define MPDDRC_NC_11 (0x2 << MPDDRC_NC_SHIFT)
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#define MPDDRC_NC_12 (0x3 << MPDDRC_NC_SHIFT)
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#define MPDDRC_NR_SHIFT 2 /* Number of Row Bits */
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#define MPDDRC_NR_MASK (0x3 << MPDDRC_NR_SHIFT)
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#define MPDDRC_NR_11 (0x0 << MPDDRC_NR_SHIFT)
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#define MPDDRC_NR_12 (0x1 << MPDDRC_NR_SHIFT)
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#define MPDDRC_NR_13 (0x2 << MPDDRC_NR_SHIFT)
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#define MPDDRC_NR_14 (0x3 << MPDDRC_NR_SHIFT)
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#define MPDDRC_CAS_SHIFT 4 /* CAS Latency */
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#define MPDDRC_CAS_MASK (0x7 << MPDDRC_CAS_SHIFT)
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#define MPDDRC_NB_SHIFT 20 /* Number of Banks */
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#define MPDDRC_NB_MASK (0x1 << MPDDRC_NB_SHIFT)
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#define MPDDRC_MD_DBW_SHIFT 4 /* Data Bus Width */
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#define MPDDRC_MD_DBW_MASK (0x1 << MPDDRC_MD_DBW_SHIFT)
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#define MPDDRC_NQDS_DISABLED_SHIFT 21 /* NAND Data Queue in DDR2 SDRAM */
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#define MPDDRC_NDQS_DISABLED (0x1 << MPDDRC_NQDS_DISABLED_SHIFT)
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#define MPDDRC_UNAL_SHIFT 23 /* Support Unaligned Access */
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#define MPDDRC_UNAL (0x1 << MPDDRC_UNAL_SHIFT)
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#define REF_WIN 32
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#define REF_CYCLE 2048
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/* Configuration register */
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#define MPDDRC_CR_NC_SHIFT 0
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#define MPDDRC_CR_NC_MASK (0x3 << MPDDRC_CR_NC_SHIFT)
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#define MPDDRC_CR_NR_SHIFT 2
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#define MPDDRC_CR_NR_MASK (0x3 << MPDDRC_CR_NR_SHIFT)
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#define MPDDRC_CR_CAS_SHIFT 4
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#define MPDDRC_CR_CAS_MASK (0x7 << MPDDRC_CR_CAS_SHIFT)
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#define MPDDRC_CR_ENABLE_DLL_RESET (1 << 7)
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#define MPDDRC_CR_NB_SHIFT 8
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#define MPDDRC_CR_NB_MASK (0x1 << MPDDRC_CR_NB_SHIFT)
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#define MPDDRC_CR_DECOD_INTERLEAVED (1 << 22)
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/* Memory device register */
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#define MPDDRC_MD_SDRAM (0x0 << 0)
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#define MPDDRC_MD_LP_SDRAM (0x1 << 0)
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#define MPDDRC_MD_DDR_SDRAM (0x2 << 0)
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#define MPDDRC_MD_LP_DDR_SDRAM (0x3 << 0)
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#define MPDDRC_MD_DDR3_SDRAM (0x4 << 0)
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#define MPDDRC_MD_LPDDR3_SDRAM (0x5 << 0)
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#define MPDDRC_MD_DDR2_SDRAM (0x6 << 0)
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#define MPDDRC_MD_LPDDR2_SDRAM (0x7 << 0)
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#define MPDDRC_MD_DBW_32BIT (0x0 << 4)
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#define MPDDRC_MD_DBW_16BIT (0x1 << 4)
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/* Mode register */
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#define MPDDRC_MR_MODE_NORMAL 0
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#define MPDDRC_MR_MODE_NOP 1
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#define MPDDRC_MR_MODE_PRECHARGE 2
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#define MPDDRC_MR_MODE_LOAD 3
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#define MPDDRC_MR_MODE_AUTO_REFRESH 4
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#define MPDDRC_MR_MODE_EXT_LOAD 5
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#define MPDDRC_MR_MODE_DEEP_POWER 6
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#define MPDDRC_MR_MODE_LPDDR2_PDE 7
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#define MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
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#define MPDDRC_TRAS_SHIFT 0
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#define MPDDRC_TRCD_SHIFT 4
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#define MPDDRC_TWR_SHIFT 8
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#define MPDDRC_TRC_SHIFT 12
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#define MPDDRC_TRP_SHIFT 16
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#define MPDDRC_TRRD_SHIFT 20
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#define MPDDRC_TWTR_SHIFT 24
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#define MPDDRC_TMRD_SHIFT 28
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#define MPDDRC_TRFC_SHIFT 0
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#define MPDDRC_TXSNR_SHIFT 8
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#define MPDDRC_TXSRD_SHIFT 16
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#define MPDDRC_TXP_SHIFT 24
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#define MPDDRC_TXARD_SHIFT 0
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#define MPDDRC_TXARDS_SHIFT 4
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#define MPDDRC_TRPA_SHIFT 8
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#define MPDDRC_TRTP_SHIFT 12
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#define MPDDRC_TFAW_SHIFT 16
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/* Calibration register */
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#define MPDDRC_IOCALIBR_RDIV_SHIFT 0
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#define MPDDRC_IOCALIBR_RDIV_MASK (0x7 << MPDDRC_IOCALIBR_RDIV_SHIFT)
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#define MPDDRC_IOCALIBR_RDIV_DDR2_RZQ_50 (4 << MPDDRC_IOCALIBR_RDIV_SHIFT)
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#define MPDDRC_IOCALIBR_TZQIO_SHIFT 8
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#define MPDDRC_IOCALIBR_TZQIO_MASK (0x7F << MPDDRC_IOCALIBR_TZQIO_SHIFT)
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/* Read data path register */
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#define MPDDRC_RD_DATA_PATH_CYCLES_SHIFT 0
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#define MPDDRC_RD_DATA_PATH_CYCLES_MASK (0x3 << MPDDRC_RD_DATA_PATH_CYCLES_SHIFT)
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/* MPDDRC Device clock */
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#define MPDDRC_PMCID 0x31 /* dec: 49 for SAMA5D3 */
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#define MPDDRC_SCERID (1 << 2)
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/* PIT device clock */
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#define PIT_PMCID 0x03 /* dec: 3 for SAMA5D3 */
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#define MAX_PIV 0xfffff
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#define PIT_MR_EN (1 << 24)
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/* GPIO PMC IDs */
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#define GPIOA_PMCID 0x06
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#define GPIOB_PMCID 0x07
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#define GPIOC_PMCID 0x08
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#define GPIOD_PMCID 0x09
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#define GPIOE_PMCID 0x0A
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struct dram {
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struct dram_timing {
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uint32_t tras;
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uint32_t trcd;
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uint32_t twr;
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uint32_t trc;
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uint32_t trp;
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uint32_t trrd;
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uint32_t twtr;
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uint32_t tmrd;
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uint32_t trfc;
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uint32_t txsnr;
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uint32_t txsrd;
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uint32_t txp;
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uint32_t txard;
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uint32_t txards;
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uint32_t trpa;
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uint32_t trtp;
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uint32_t tfaw;
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} timing;
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};
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/* Watchdog
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*
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*/
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#define WDT_BASE 0xFFFFFD40
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#define WDT_CR *(volatile uint32_t *)(WDT_BASE + 0x00)
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#define WDT_MR *(volatile uint32_t *)(WDT_BASE + 0x04)
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#define WDT_SR *(volatile uint32_t *)(WDT_BASE + 0x08)
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#define WDT_MD_WDDIS (0x1 << 15)
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#define WDT_MD_WDRSTEN (0x1 << 14)
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static inline void watchdog_disable(void)
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{
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WDT_MR |= WDT_MD_WDDIS;
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}
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/*
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*
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* NAND flash
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*/
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/* Fixed addresses */
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extern void *kernel_addr, *update_addr, *dts_addr;
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#if defined(EXT_FLASH) && defined(NAND_FLASH)
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/* Constant for local buffers */
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#define NAND_FLASH_PAGE_SIZE 0x800 /* 2KB */
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#define NAND_FLASH_OOB_SIZE 0x40 /* 64B */
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/* Address space mapping for atsama5d3 */
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#define DRAM_BASE 0x20000000UL
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#define CS1_BASE 0x40000000UL
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#define CS2_BASE 0x50000000UL
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#define CS3_BASE 0x60000000UL
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#define NFC_CMD_BASE 0x70000000UL
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/* NAND flash is mapped to CS3 */
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#define NAND_BASE CS3_BASE
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#define NAND_MASK_ALE (1 << 21)
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#define NAND_MASK_CLE (1 << 22)
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#define NAND_CMD (*((volatile uint8_t *)(NAND_BASE | NAND_MASK_CLE)))
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#define NAND_ADDR (*((volatile uint8_t *)(NAND_BASE | NAND_MASK_ALE)))
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#define NAND_DATA (*((volatile uint8_t *)(NAND_BASE)))
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/* Command set */
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_READ1 0x00
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#define NAND_CMD_READ2 0x30
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_RESET 0xFF
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_ERASE2 0xD0
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#define NAND_CMD_WRITE1 0x80
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#define NAND_CMD_WRITE2 0x10
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/* Small block */
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#define NAND_CMD_READ_A0 0x00
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#define NAND_CMD_READ_A1 0x01
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#define NAND_CMD_READ_C 0x50
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#define NAND_CMD_WRITE_A 0x00
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#define NAND_CMD_WRITE_C 0x50
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/* ONFI */
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#define NAND_CMD_READ_ONFI 0xEC
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/* Features set/get */
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#define NAND_CMD_GET_FEATURES 0xEE
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#define NAND_CMD_SET_FEATURES 0xEF
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/* ONFI parameters and definitions */
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#define ONFI_PARAMS_SIZE 256
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#define PARAMS_POS_REVISION 4
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#define PARAMS_REVISION_1_0 (0x1 << 1)
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#define PARAMS_REVISION_2_0 (0x1 << 2)
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#define PARAMS_REVISION_2_1 (0x1 << 3)
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#define PARAMS_POS_FEATURES 6
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#define PARAMS_FEATURE_BUSWIDTH (0x1 << 0)
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#define PARAMS_FEATURE_EXTENDED_PARAM (0x1 << 7)
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#define PARAMS_POS_OPT_CMD 8
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#define PARAMS_OPT_CMD_SET_GET_FEATURES (0x1 << 2)
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#define PARAMS_POS_EXT_PARAM_PAGE_LEN 12
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#define PARAMS_POS_PARAMETER_PAGE 14
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#define PARAMS_POS_PAGESIZE 80
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#define PARAMS_POS_OOBSIZE 84
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#define PARAMS_POS_BLOCKSIZE 92
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#define PARAMS_POS_NBBLOCKS 96
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#define PARAMS_POS_ECC_BITS 112
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#define PARAMS_POS_TIMING_MODE 129
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#define PARAMS_TIMING_MODE_0 (1 << 0)
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#define PARAMS_TIMING_MODE_1 (1 << 1)
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#define PARAMS_TIMING_MODE_2 (1 << 2)
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#define PARAMS_TIMING_MODE_3 (1 << 3)
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#define PARAMS_TIMING_MODE_4 (1 << 4)
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#define PARAMS_TIMING_MODE_5 (1 << 5)
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#define PARAMS_POS_CRC 254
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#define ONFI_CRC_BASE 0x4F4E
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#define ONFI_MAX_SECTIONS 8
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#define ONFI_SECTION_TYPE_0 0
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#define ONFI_SECTION_TYPE_1 1
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#define ONFI_SECTION_TYPE_2 2
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/* Read access modes */
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#define NAND_MODE_DATAPAGE 1
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#define NAND_MODE_INFO 2
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#define NAND_MODE_DATABLOCK 3
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#define nand_flash_read ext_flash_read
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#define nand_flash_write ext_flash_write
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#define nand_flash_erase ext_flash_erase
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#define nand_flash_unlock ext_flash_unlock
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#define nand_flash_lock ext_flash_lock
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#define MAX_ECC_BYTES 8
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#endif
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#define GPIOB 0xFFFFF400
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#define GPIOC 0xFFFFF600
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#define GPIOE 0xFFFFFA00
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#define GPIO_PER(base) *(volatile uint32_t *)(base + 0x00)
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#define GPIO_PDR(base) *(volatile uint32_t *)(base + 0x04)
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#define GPIO_PSR(base) *(volatile uint32_t *)(base + 0x08)
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#define GPIO_OER(base) *(volatile uint32_t *)(base + 0x10)
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#define GPIO_ODR(base) *(volatile uint32_t *)(base + 0x14)
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#define GPIO_OSR(base) *(volatile uint32_t *)(base + 0x18)
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#define GPIO_SODR(base) *(volatile uint32_t *)(base + 0x30)
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#define GPIO_CODR(base) *(volatile uint32_t *)(base + 0x34)
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#define GPIO_IER(base) *(volatile uint32_t *)(base + 0x40)
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#define GPIO_IDR(base) *(volatile uint32_t *)(base + 0x44)
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#define GPIO_MDER(base) *(volatile uint32_t *)(base + 0x50)
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#define GPIO_MDDR(base) *(volatile uint32_t *)(base + 0x54)
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#define GPIO_PPUDR(base) *(volatile uint32_t *)(base + 0x60)
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#define GPIO_PPUER(base) *(volatile uint32_t *)(base + 0x64)
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#define GPIO_ASR(base) *(volatile uint32_t *)(base + 0x70)
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#define GPIO_PPDDR(base) *(volatile uint32_t *)(base + 0x90)
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/* PMC Macro to enable clock */
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#define PMC_CLOCK_EN(id) { \
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register uint32_t pmc_pcr; \
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PMC_PCR = id; \
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pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK); \
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pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN; \
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PMC_PCR = pmc_pcr; \
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}
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#endif
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