mirror of https://github.com/wolfSSL/wolfBoot.git
119 lines
4.1 KiB
Plaintext
119 lines
4.1 KiB
Plaintext
# wolfBoot configuration for AMD ZynqMP ZCU102 - FSBL REPLACEMENT (QSPI boot)
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# Zynq UltraScale+ MPSoC ZU9EG - Quad-core ARM Cortex-A53
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#
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# wolfBoot replaces the Xilinx First Stage Boot Loader (FSBL). The BootROM
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# (optionally with eFuse PPK RSA secure boot) authenticates and loads wolfBoot
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# directly into OCM at 0xFFFC0000 and enters it at EL3. wolfBoot then:
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# 1. runs the board psu_init() (PLLs, DDR, MIO mux, clocks)
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# 2. loads + verifies the downstream images with its OWN signing keys
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# 3. (Milestone 1) hands off to real ARM Trusted Firmware (BL31) which keeps
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# EL3/PSCI and drops to Linux.
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# PMUFW is still loaded by the BootROM via the [pmufw_image] BIF tag.
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#
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# Boot flow: BootROM -> wolfBoot (OCM/EL3) -> psu_init -> verify+load
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# BL31 + kernel + DTB -> BL31 -> Linux
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#
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# The board-specific psu_init_gpl.c / psu_init_gpl.h (generated from the XSA,
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# Xilinx copyright) must be supplied at build time. By default they are read
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# from hal/board/zynqmp/ (override with ZYNQMP_PSU_INIT_DIR=...). They are not
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# part of the wolfBoot tree. Build with:
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# make ZYNQMP_FSBL=1 ZYNQMP_PSU_INIT_DIR=/path/to/board
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# Package with tools/scripts/zcu102/zynqmp_wolfboot_fsbl.bif
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ARCH?=AARCH64
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TARGET?=zynq
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# Enable the FSBL-replacement build: link/run from OCM, run psu_init at boot,
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# pull in the board psu_init_gpl.o + the hal/zynqmp shim.
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ZYNQMP_FSBL?=1
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ZYNQMP_PSU_INIT_DIR?=hal/board/zynqmp
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# Load the PMU configuration object (EEMI permission table) into PMU firmware
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# so the APU can control SoC nodes; needs hal/board/zynqmp/pm_cfg_obj.c.
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ZYNQMP_PM_CFG?=1
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# Run the PS-GTR serdes init so USB3/SATA/PCIe/DP PHY lanes are clocked.
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# Needed for the kernel's USB (dwc3) probe not to hang. Set 0 to skip (QSPI/SD
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# boot does not need serdes).
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ZYNQMP_PSU_INIT_SERDES?=1
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# FSBL security features (eFuse read/PUF/AES-CSU) via direct EL3 CSU/eFuse
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# access. Read-only eFuse dump today. Set 0 to exclude.
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ZYNQMP_SEC?=1
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# BootROM enters the [bootloader] partition at EL3. Run wolfBoot at EL3.
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CFLAGS_EXTRA+=-DEL3_SECURE=1
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# DDR-training delay correction. The BootROM leaves the IOU_SCNTRS system
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# counter running at the ~1.6GHz pre-divider rate during psu_init (the /15
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# TIMESTAMP_REF_CTRL divisor does not re-latch the already-running counter),
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# while usleep() computes its tick budget at the nominal 100MHz timestamp
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# clock. Without correction every psu_ddr_phybringup settle delay is ~16x too
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# short and DDR PHY training comes up marginal. Hardware-measured: a 16x scale
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# restores correct training. See hal/zynqmp_psu_shim.c.
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CFLAGS_EXTRA+=-DZYNQMP_USLEEP_SCALE=16
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WOLFBOOT_VERSION?=0
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# RSA 4096-bit with SHA3-384 (downstream image signing)
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SIGN?=RSA4096
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HASH?=SHA3
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IMAGE_HEADER_SIZE?=1024
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# Software ARMv8+Crypto assembly for SHA3 (no CSU/PMU SMC available at EL3
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# until BL31 is resident).
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NO_ARM_ASM?=0
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HW_SHA3?=0
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DEBUG?=0
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DEBUG_SYMBOLS=1
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DEBUG_UART=1
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# CFLAGS_EXTRA+=-DDEBUG_ZYNQ=1 # per-chunk QSPI/DDR debug spew; enable only for bring-up
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=0
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DUALBANK_SWAP?=0
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PKA?=0
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WOLFTPM?=0
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# Downstream images are read from QSPI (not XIP; wolfBoot executes from OCM).
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EXT_FLASH?=1
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SPI_FLASH?=0
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NO_XIP=1
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USE_GCC=1
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ELF?=1
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# Native gzip decompression for FIT subimages
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GZIP?=1
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# Flash Sector Size
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WOLFBOOT_SECTOR_SIZE=0x20000
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# Application Partition Size
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WOLFBOOT_PARTITION_SIZE=0x2A00000
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# wolfBoot self-location (OCM). Must match ORIGIN in hal/zynqmp_ocm.ld.
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WOLFBOOT_ORIGIN=0xFFFC0000
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# Location in QSPI for Primary Boot Partition (OS payload: FIT kernel+DTB)
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x800000
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# Load Partition to RAM Address (DDR, after psu_init)
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WOLFBOOT_LOAD_ADDRESS?=0x10000000
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# Location in QSPI for Secondary (update) Partition
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x3A00000
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# Location to store wolfBoot state
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x63E0000
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# DTS (Device Tree)
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x11800000
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WOLFBOOT_DTS_BOOT_ADDRESS?=0x7B0000
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WOLFBOOT_DTS_UPDATE_ADDRESS?=0x39B0000
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CROSS_COMPILE=aarch64-none-elf-
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# Speed up reads from flash by using larger blocks
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CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
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