mirror of https://github.com/wolfSSL/wolfBoot.git
190 lines
8.7 KiB
C
190 lines
8.7 KiB
C
/* tegra234.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* NVIDIA Jetson Orin (Tegra234) hardware definitions. Register bases are from
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* the public Tegra234 memory map / upstream device tree (tegra234.dtsi).
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*
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* src/boot_aarch64_start.S includes this header for the USE_*_STARTUP
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* selection below, so nothing here may expand to C-only syntax on the path the
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* assembler sees. Everything is a plain integer expression; the pointer
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* casting lives in the HAL (hal/tegra234.c).
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*/
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#ifndef _TEGRA234_H_
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#define _TEGRA234_H_
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/* Simple AArch64 startup (src/boot_aarch64_start.S): a .boot reset stub that
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* detects the EL, sets sp, and calls boot_entry_C. MB1/MB2 already brought up
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* DRAM/clocks, so no builtin EL3/MMU init is needed (same model as raspi3). */
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#define USE_BUILTIN_STARTUP
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#define USE_SIMPLE_STARTUP
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/* --- BL33 image layout ---------------------------------------------------
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* MB2 loads the cpu-bootloader (cpubl) slot at BL33_BASE and BL31 enters it
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* there; confirmed on hardware. The signed payload and the DTB are bundled
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* into the same image at fixed offsets so update_ram boots straight out of
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* DRAM with no storage driver. Offsets must clear wolfBoot's runtime
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* footprint (~600 KB incl. the 256 KB .stack) and the total must stay under
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* MB2's 4 MB cpubl cap. Keep in sync with hal/tegra234.ld and
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* tools/scripts/tegra234-mk*.sh. */
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#define TEGRA234_BL33_BASE 0x272000000
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/* Non-ECC DRAM window, used to sanity-check handoff pointers */
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#define TEGRA234_DRAM_BASE 0x80000000
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#define TEGRA234_DRAM_END 0x280000000
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#define TEGRA234_BUNDLE_OFFSET 0x200000 /* 2 MB: signed payload */
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#define TEGRA234_DTB_OFFSET 0x300000 /* 3 MB: device tree */
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#define TEGRA234_CPUBL_MAX_SIZE 0x400000 /* MB2 cap on the image */
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/* Update partition, staged in low DRAM. A constant rather than a linker
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* symbol: an ADRP against an absolute symbol this far from the image base does
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* not fit its +/-4GB reach. */
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#define TEGRA234_UPDATE_ADDR 0x81100000
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/* --- Generic timer -------------------------------------------------------
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* Fallback if firmware left CNTFRQ_EL0 unprogrammed. Tegra234's timestamp
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* counter runs at 31.25 MHz (CNTFRQ_EL0 = 0x01DCD650, read on silicon). */
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#ifndef TIMER_CLK_FREQ
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#define TIMER_CLK_FREQ 31250000
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#endif
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/* --- Console: Tegra Combined UART (TCU) ----------------------------------
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* At BL33 the console is the TCU (Linux ttyTCU0), not a raw NS16550: a
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* physical UART such as UARTA (0x03100000) is neither clocked nor routed
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* here, and touching it faults with a CBB slave error (RAS uncorrectable)
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* that powers the core off. Confirmed on hardware 2026-07-27.
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*
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* TX is an AON HSP shared mailbox the SPE drains and forwards to the debug
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* UART. Per the platform device tree the TCU "tx" mailbox is SM1 of the AON
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* HSP (hsp@c150000); Tegra HSP lays shared mailboxes out at
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* 0x10000 + (n/2)*0x10000 + (n%2)*0x8000, so SM1 = 0x0c150000 + 0x18000
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* (this equals ARM Trusted Firmware's TEGRA_CONSOLE_SPE_BASE).
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*
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* Protocol (matches tegra-tcu / ATF console_spe): wait for FULL to clear,
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* then write FULL | count<<24 | up to 3 bytes packed little-endian. */
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#define TEGRA_TCU_TX_MBOX 0x0c168000
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#define TEGRA_TCU_MBOX_FULL (1u << 31)
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#define TEGRA_TCU_MBOX_NBYTES_SHIFT 24
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#define TEGRA_TCU_MBOX_MAX_BYTES 3
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/* --- BPMP IPC: IVC channel + HSP doorbell --------------------------------
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* Clocks and resets are owned by the BPMP. T234 uses the tegra186 BPMP layout
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* (cpu_tx channel at queue index 3, 256-byte queues), signalled by the top0
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* HSP doorbell for master BPMP (19 -> doorbell register index 3). */
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#define TEGRA_BPMP_TXCH 0x40070300 /* TX SysRAM + cpu_tx(3)*256 */
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#define TEGRA_BPMP_RXCH 0x40071300 /* RX SysRAM + 0x300 */
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#define TEGRA_IVC_HDR_SZ 128 /* tx{count,state} + rx{count} */
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#define TEGRA_IVC_TX_COUNT 0x00
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#define TEGRA_IVC_TX_STATE 0x04
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#define TEGRA_IVC_RX_COUNT 0x40
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#define TEGRA_IVC_SYNC 0
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#define TEGRA_IVC_ACK 1
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#define TEGRA_IVC_ESTABLISHED 2
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#define TEGRA_HSP_TOP0 0x03c00000
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#define TEGRA_HSP_INT_DIMENSIONING 0x380
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#define TEGRA_HSP_DB_BPMP 3
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/* BPMP mb_data frame: u32 code, u32 flags, u8 data[120] */
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#define TEGRA_BPMP_MB_CODE 0x00
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#define TEGRA_BPMP_MB_FLAGS 0x04
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#define TEGRA_BPMP_MB_DATA 0x08
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#define TEGRA_BPMP_MB_DATA_SZ 120
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#define TEGRA_BPMP_MSG_ACK 1
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/* MRQ requests and the clock/reset sub-commands we issue */
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#define TEGRA_BPMP_MRQ_PING 0
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#define TEGRA_BPMP_MRQ_RESET 20
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#define TEGRA_BPMP_MRQ_CLK 22
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#define TEGRA_BPMP_CMD_CLK_GET_RATE 1
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#define TEGRA_BPMP_CMD_CLK_SET_RATE 2
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#define TEGRA_BPMP_CMD_CLK_ENABLE 7
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#define TEGRA_BPMP_CMD_RESET_DEASSERT 2
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#define TEGRA234_CLK_SDMMC1 120
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#define TEGRA234_RESET_SDMMC1 82
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/* SDMMC legacy timeout clock (tmclk). t234 SDHCI (NVQUIRK_HAS_TMCLK) keeps
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* this 12 MHz clock on at all times for data-timeout, and advertises it in
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* CAPS; without it the SD clock path never completes. */
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#define TEGRA234_CLK_SDMMC_LEGACY_TM 219
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#define TEGRA234_SDMMC_TMCLK_RATE 12000000
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/* SDMMC1 base clock: the controller advertises 208 MHz in CAPS */
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#define TEGRA234_SDMMC1_BASE_RATE 208000000
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/* --- SDMMC / SDHCI -------------------------------------------------------
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* SDMMC1 (external microSD on the Orin Nano dev kit) is sdhci@3400000 in
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* tegra234.dtsi; SDMMC4 (eMMC) is at 0x03460000. Tegra234 SDMMC1 is a v4+
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* standard-SDHCI controller (HOSTVER 0x0505, A64S set). */
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#define TEGRA_SDMMC1_BASE 0x03400000
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#define TEGRA_SDMMC4_BASE 0x03460000
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#ifndef TEGRA_SDHCI_BASE
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#define TEGRA_SDHCI_BASE TEGRA_SDMMC1_BASE
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#endif
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/* Offset at which the generic (Cadence) driver in src/sdhci.c places the
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* standard SD Host Controller "SRS" block; subtract it to reach Tegra's
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* standard-SDHCI registers, which begin at offset 0. */
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#define TEGRA_SDHCI_SRS_OFFSET 0x200
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/* Standard SDHCI registers the shim reaches directly (the Cadence HRS
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* definitions come from include/sdhci.h) */
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#define TEGRA_STD_SW_RESET 0x2F /* 8-bit */
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#define TEGRA_STD_SW_RESET_ALL 0x01
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#define TEGRA_STD_CAPS1 0x40
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#define TEGRA_STD_CAPS2 0x44
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#define TEGRA_STD_PRESENT_STATE 0x24
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#define TEGRA_STD_HOST_VERSION 0xFC
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/* Tegra SDMMC vendor registers (outside the standard SDHCI range, so they
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* survive the driver's Software-Reset-for-All) */
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#define TEGRA_VENDOR_CLOCK_CTRL 0x100
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#define TEGRA_VCC_TAP_MASK 0x00FF0000
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#define TEGRA_VCC_TAP_SHIFT 16
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#define TEGRA_VCC_TRIM_MASK 0x1F000000
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#define TEGRA_VCC_TRIM_SHIFT 24
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#define TEGRA_VCC_PADPIPE_CLKEN_OVERRIDE (1u << 3)
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#define TEGRA_VCC_SDR50_TUNING_OVERRIDE (1u << 5)
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#define TEGRA_VENDOR_MISC_CTRL 0x120
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#define TEGRA_VMC_ENABLE_SDR104 0x08
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#define TEGRA_VMC_ENABLE_SDR50 0x10
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#define TEGRA_VMC_ENABLE_SPEC_300 0x20
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#define TEGRA_SDMEM_COMP_PADCTRL 0x1e0
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#define TEGRA_PADCTRL_VREF_SEL_MASK 0x0000000F
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#define TEGRA_PADCTRL_VREF_SEL_VAL 0x7
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#define TEGRA_PADCTRL_E_INPUT_E_PWRD (1u << 31)
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/* SDMMC1 (microSD) default pad tap/trim from the platform device tree */
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#define TEGRA_SDMMC1_DEFAULT_TAP 0x0E
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#define TEGRA_SDMMC1_DEFAULT_TRIM 0x08
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/* --- Main GPIO: microSD 3.3V rail ----------------------------------------
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* VDD_3V3_SD is a GPIO-controlled fixed regulator that MB1 leaves off (it
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* boots from QSPI). Per the platform device tree the enable is main-GPIO port
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* A pin 0 (regulator-vdd-3v3-sd, enable-active-high). Per-pin registers are
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* at base + bank*0x1000 + port*0x200 + pin*0x20, and port A is bank 0 /
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* port 0 / pin 0. */
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#define TEGRA_MAIN_GPIO_A0 0x02210000
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#define TEGRA_GPIO_ENABLE_CONFIG 0x00 /* bit0 ENABLE, bit1 OUT */
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#define TEGRA_GPIO_ENABLE_OUT 0x03 /* ENABLE | OUT */
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#define TEGRA_GPIO_OUTPUT_CONTROL 0x0C /* bit0 FLOATED (0 = driven) */
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#define TEGRA_GPIO_OUTPUT_VALUE 0x10 /* bit0 HIGH */
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#endif /* _TEGRA234_H_ */
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