mirror of https://github.com/wolfSSL/wolfBoot.git
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/* spi_drv_nrf5340.h
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef SPI_DRV_NRF53_H_INCLUDED
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#define SPI_DRV_NRF53_H_INCLUDED
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#include <stdint.h>
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#include "hal/nrf5340.h"
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/* Default SPI interface (0-2) */
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#ifndef SPI_PORT
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#define SPI_PORT 0
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#endif
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/* SPI Pin Configuration (P1.x) */
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/* Default for nRF5340-DK is Arduino shield P4 P1.12-15 */
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/* CLK=P1.15, CS=P1.12, MOSI=P1.13, MISO=P1.14 */
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#ifndef SPI_CS_PIO_BASE
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#define SPI_CS_PIO_BASE 1
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#endif
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#ifndef SPI_CS_TPM
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#define SPI_CS_TPM 11
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#endif
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#ifndef SPI_CS_FLASH
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#define SPI_CS_FLASH 12
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#endif
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#ifndef SPI_MOSI_PIN
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#define SPI_MOSI_PIN 13
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#endif
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#ifndef SPI_MISO_PIN
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#define SPI_MISO_PIN 14
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#endif
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#ifndef SPI_CLK_PIN
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#define SPI_CLK_PIN 15
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#endif
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/* QSPI Pin Configuration */
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/* Default is nRF5340-DK QSPI connected to MX25R6435F */
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/* CLK=P0.17, CS=P0.18, IO0=P0.13, IO1=P0.14, IO2=P0.15, IO3=P0.16 */
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/* QSPI CLK PB2 (alt OCTOSPIM_P1_CLK)*/
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#ifndef QSPI_CLK_PIN
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#define QSPI_CLK_PORT 0
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#define QSPI_CLK_PIN 17
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#endif
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#ifndef QSPI_CS_PIN
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#define QSPI_CS_PORT 0
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#define QSPI_CS_PIN 18
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#endif
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#ifndef QSPI_IO0_PIN
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#define QSPI_IO0_PORT 0
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#define QSPI_IO0_PIN 13
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#endif
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#ifndef QSPI_IO1_PIN
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#define QSPI_IO1_PORT 0
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#define QSPI_IO1_PIN 14
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#endif
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#ifndef QSPI_IO2_PIN
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#define QSPI_IO2_PORT 0
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#define QSPI_IO2_PIN 15
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#endif
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#ifndef QSPI_IO3_PIN
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#define QSPI_IO3_PORT 0
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#define QSPI_IO3_PIN 16
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#endif
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#ifndef QSPI_CLOCK_MHZ /* default 24MHz (up to 96MHz) */
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#define QSPI_CLOCK_MHZ 24000000UL
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#endif
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/* MX25R6435F */
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#define QSPI_NO_SR2
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#define QSPI_CLK 96000000UL
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#if QSPI_CLOCK_MHZ <= 24000000
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#define QSPI_CLK_DIV CLOCK_HFCLK192MCTRL_DIV4
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#elif QSPI_CLOCK_MHZ <= 48000000
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/* Note: Power consumption higher for DIV2/DIV1 */
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#define QSPI_CLK_DIV CLOCK_HFCLK192MCTRL_DIV2
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#else
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/* Note: Power consumption higher for DIV2/DIV1 */
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#define QSPI_CLK_DIV CLOCK_HFCLK192MCTRL_DIV1
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#endif
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/* Calculate the IFCONFIG1_SCKFREG divisor */
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#define QSPI_CLK_FREQ_DIV ((QSPI_CLK / (QSPI_CLK_DIV+1) / QSPI_CLOCK_MHZ) - 1)
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#endif /* !SPI_DRV_NRF53_H_INCLUDED */
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