mirror of https://github.com/wolfSSL/wolfBoot.git
245 lines
10 KiB
C
245 lines
10 KiB
C
/* rp2350.c
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*
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* Custom HAL implementation. Defines the
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* functions used by wolfboot for raspberry-pi pico2 (rp2350)
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*
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* Copyright (C) 2025 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <target.h>
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#include "image.h"
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#include "printf.h"
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#include "hardware/flash.h"
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#ifdef TZEN
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#include "armv8m_tz.h"
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#include "pico/bootrom.h"
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#define NVIC_ICER0 (*(volatile uint32_t *)(0xE000E180))
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#define NVIC_ICPR0 (*(volatile uint32_t *)(0xE000E280))
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#define NVIC_ITNS0 (*(volatile uint32_t *)(0xE000EF00))
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#define SCB_VTOR_NS (*(volatile uint32_t *)(0xE002ED08))
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#define NSACR (*(volatile uint32_t *)(0xE000ED8C))
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#define CPACR (*(volatile uint32_t *)(0xE000ED88))
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#define SHCSR (*(volatile uint32_t *)(0xE000ED24))
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#define SHCSR_MEMFAULTENA (1 << 16)
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#define SHCSR_BUSFAULTENA (1 << 17)
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#define SHCSR_USGFAULTENA (1 << 18)
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#define ACCESS_BITS_DBG (1 << 7)
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#define ACCESS_BITS_DMA (1 << 6)
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#define ACCESS_BITS_CORE1 (1 << 5)
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#define ACCESS_BITS_CORE0 (1 << 4)
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#define ACCESS_BITS_SP (1 << 3)
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#define ACCESS_BITS_SU (1 << 2)
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#define ACCESS_BITS_NSP (1 << 1)
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#define ACCESS_BITS_NSU (1 << 0)
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#define ACCESS_MAGIC (0xACCE0000)
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#define ACCESS_CONTROL (0x40060000)
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#define ACCESS_CONTROL_LOCK (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0000))
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#define ACCESS_CONTROL_FORCE_CORE_NS (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0004))
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#define ACCESS_CONTROL_CFGRESET (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0008))
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#define ACCESS_CONTROL_GPIOMASK0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x000C))
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#define ACCESS_CONTROL_GPIOMASK1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0010))
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#define ACCESS_CONTROL_ROM (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0014))
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#define ACCESS_CONTROL_XIP_MAIN (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0018))
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#define ACCESS_CONTROL_SRAM(block) (*(volatile uint32_t *)(ACCESS_CONTROL + 0x001C + (block) * 4)) /* block = 0..9 */
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#define ACCESS_CONTROL_DMA (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0044))
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#define ACCESS_CONTROL_USBCTRL (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0048))
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#define ACCESS_CONTROL_PIO0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x004C))
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#define ACCESS_CONTROL_PIO1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0050))
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#define ACCESS_CONTROL_PIO2 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0054))
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#define ACCESS_CONTROL_CORESIGHT_TRACE (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0058))
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#define ACCESS_CONTROL_CORESIGHT_PERIPH (*(volatile uint32_t *)(ACCESS_CONTROL + 0x005C))
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#define ACCESS_CONTROL_SYSINFO (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0060))
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#define ACCESS_CONTROL_RESETS (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0064))
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#define ACCESS_CONTROL_IO_BANK0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0068))
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#define ACCESS_CONTROL_IO_BANK1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x006C))
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#define ACCESS_CONTROL_PADS_BANK0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0070))
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#define ACCESS_CONTROL_PADS_QSPI (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0074))
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#define ACCESS_CONTROL_BUSCTRL (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0078))
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#define ACCESS_CONTROL_ADC (*(volatile uint32_t *)(ACCESS_CONTROL + 0x007C))
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#define ACCESS_CONTROL_HSTX (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0080))
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#define ACCESS_CONTROL_I2C0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0084))
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#define ACCESS_CONTROL_I2C1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0088))
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#define ACCESS_CONTROL_PWM (*(volatile uint32_t *)(ACCESS_CONTROL + 0x008C))
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#define ACCESS_CONTROL_SPI0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0090))
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#define ACCESS_CONTROL_SPI1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0094))
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#define ACCESS_CONTROL_TIMER0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x0098))
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#define ACCESS_CONTROL_TIMER1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x009C))
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#define ACCESS_CONTROL_UART0 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00A0))
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#define ACCESS_CONTROL_UART1 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00A4))
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#define ACCESS_CONTROL_OTP (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00A8))
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#define ACCESS_CONTROL_TBMAN (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00AC))
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#define ACCESS_CONTROL_POWMAN (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00B0))
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#define ACCESS_CONTROL_TRNG (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00B4))
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#define ACCESS_CONTROL_SHA256 (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00B8))
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#define ACCESS_CONTROL_SYSCFG (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00BC))
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#define ACCESS_CONTROL_CLOCKS (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00C0))
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#define ACCESS_CONTROL_XOSC (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00C4))
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#define ACCESS_CONTROL_ROSC (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00C8))
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#define ACCESS_CONTROL_PLL_SYS (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00CC))
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#define ACCESS_CONTROL_PLL_USB (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00D0))
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#define ACCESS_CONTROL_TICKS (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00D4))
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#define ACCESS_CONTROL_WATCHDOG (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00D8))
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#define ACCESS_CONTROL_PSM (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00DC))
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#define ACCESS_CONTROL_XIP_CTRL (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00E0))
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#define ACCESS_CONTROL_XIP_QMI (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00E4))
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#define ACCESS_CONTROL_XIP_AUX (*(volatile uint32_t *)(ACCESS_CONTROL + 0x00E8))
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#endif
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#ifdef __WOLFBOOT
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void hal_init(void)
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{
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#ifdef PRINTF_ENABLED
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stdio_init_all();
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#endif
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}
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#ifdef TZEN
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static void rp2350_configure_sau(void)
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{
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/* Disable SAU */
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SAU_CTRL = 0;
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sau_init_region(0, 0x10000000, 0x1002FFFF, 1); /* Secure flash */
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sau_init_region(1, 0x10030000, 0x1003FFFF, 1); /* Non-secure-callable flash */
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sau_init_region(2, 0x10040000, 0x101FFFFF, 0); /* Non-secure flash */
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sau_init_region(3, 0x20000000, 0x2003FFFF, 1); /* Secure RAM (Low 256K) */
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sau_init_region(4, 0x20040000, 0x20081FFF, 0); /* Non-secure RAM (High 256 + 8K) */
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sau_init_region(6, 0x40000000, 0x5FFFFFFF, 0); /* Non-secure peripherals */
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sau_init_region(7, 0xD0000000, 0xDFFFFFFF, 0); /* Non-secure SIO region */
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/* Enable SAU */
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SAU_CTRL = 1;
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/* Enable MemFault, BusFault and UsageFault */
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SHCSR |= SHCSR_MEMFAULTENA | SHCSR_BUSFAULTENA | SHCSR_USGFAULTENA;
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/* Add flag to trap misaligned accesses */
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*((volatile uint32_t *)0xE000ED14) |= 0x00000008;
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}
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static void rp2350_configure_nvic(void)
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{
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/* Disable all interrupts */
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NVIC_ICER0 = 0xFFFFFFFF;
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NVIC_ICPR0 = 0xFFFFFFFF;
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/* Set all interrupts to non-secure */
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NVIC_ITNS0 = 0xFFFFFFFF;
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}
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static void rp2350_configure_access_control(void)
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{
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int i;
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const uint32_t secure_fl = (ACCESS_BITS_SU | ACCESS_BITS_SP | ACCESS_BITS_DMA | ACCESS_BITS_DBG | ACCESS_BITS_CORE0) | ACCESS_MAGIC;
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const uint32_t non_secure_fl = (ACCESS_BITS_NSU | ACCESS_BITS_NSP | ACCESS_BITS_DMA | ACCESS_BITS_DBG | ACCESS_BITS_CORE0 | ACCESS_BITS_CORE1) | ACCESS_MAGIC;
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/* Set access control to Secure for lower RAM (0x20000000 - 0x2003FFFF) */
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for (i = 0; i < 4; i ++)
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ACCESS_CONTROL_SRAM(i) = secure_fl;
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/* Set access control to Non-secure for upper RAM (0x20040000 - 0x20081FFF) */
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for (i = 4; i < 10; i++)
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ACCESS_CONTROL_SRAM(i) = non_secure_fl | secure_fl;
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/* Set access control for peripherals */
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ACCESS_CONTROL_ROM = secure_fl | non_secure_fl;
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ACCESS_CONTROL_XIP_MAIN = non_secure_fl | secure_fl;
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ACCESS_CONTROL_DMA = non_secure_fl;
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ACCESS_CONTROL_TRNG = secure_fl;
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ACCESS_CONTROL_SYSCFG = secure_fl;
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ACCESS_CONTROL_SHA256 = secure_fl;
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ACCESS_CONTROL_IO_BANK0 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_IO_BANK1 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_PADS_BANK0 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_PIO0 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_PIO1 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_PIO2 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_I2C0 = non_secure_fl |secure_fl;
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ACCESS_CONTROL_I2C1 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_PWM = non_secure_fl | secure_fl;
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ACCESS_CONTROL_SPI0 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_SPI1 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_TIMER0 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_TIMER1 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_UART0 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_UART1 = non_secure_fl | secure_fl;
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ACCESS_CONTROL_ADC = non_secure_fl | secure_fl;
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ACCESS_CONTROL_RESETS = non_secure_fl | secure_fl;
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/* Force core 1 to non-secure */
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ACCESS_CONTROL_FORCE_CORE_NS = (1 << 1) | ACCESS_MAGIC;
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/* GPIO masks: Each bit represents "NS allowed" for a GPIO pin */
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ACCESS_CONTROL_GPIOMASK0 = 0xFFFFFFFF;
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ACCESS_CONTROL_GPIOMASK1 = 0xFFFFFFFF;
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CPACR |= 0x000000FF; /* Enable access to coprocessors CP0-CP7 */
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NSACR |= 0x000000FF; /* Enable non-secure access to coprocessors CP0-CP7 */
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/* Lock access control */
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ACCESS_CONTROL_LOCK = non_secure_fl | secure_fl;
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}
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#endif
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void hal_prepare_boot(void)
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{
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#ifdef TZEN
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rp2350_configure_sau();
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rp2350_configure_nvic();
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rp2350_configure_access_control();
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#endif
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}
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#endif
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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flash_range_program(address - XIP_BASE, data, len);
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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}
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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flash_range_erase(address - XIP_BASE, len);
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return 0;
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}
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