mirror of https://github.com/wolfSSL/wolfBoot.git
85 lines
2.6 KiB
Plaintext
85 lines
2.6 KiB
Plaintext
/* tegra234.ld - bare-metal link map for the Tegra234 BL33 firmware target.
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*
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* DRAM-resident, boot-from-DRAM AArch64 map (same style as hal/raspi3.ld).
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* Keep the addresses here in sync with hal/tegra234.h.
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*/
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MEMORY
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{
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/* MB2 loads the cpubl (BL33) slot at 0x272000000 and BL31 enters it there,
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* near the top of the 8GB DRAM map (non-ECC 0x80000000..0x280000000);
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* confirmed on hardware 2026-07-27. wolfBoot is not position-independent,
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* so it must link/run at that base.
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*
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* LENGTH is deliberately the payload offset (TEGRA234_BUNDLE_OFFSET, 2 MB)
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* rather than the whole window: growing wolfBoot into the bundled payload
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* is then a link error instead of an image the bundling scripts silently
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* assemble wrong. */
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DDR_MEM(rwx): ORIGIN = 0x272000000, LENGTH = 0x200000
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}
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ENTRY(_vector_table);
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.boot*))
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*(.text*)
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*(.rodata*)
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*(.note.*)
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. = ALIGN(4);
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_end_text = .;
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} > DDR_MEM
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.edidx :
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{
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. = ALIGN(4);
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*(.ARM.exidx*)
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} > DDR_MEM
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.data :
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{
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PROVIDE(_stored_data = .); /* XIP builds copy .data from here */
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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KEEP(*(.ramcode))
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. = ALIGN(4);
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_end_data = .;
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} > DDR_MEM
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.bss (NOLOAD) :
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{
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_start_bss = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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__bss_end__ = .;
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} > DDR_MEM
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/* Dedicated stack region, image-relative so the stack top is valid
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* wherever the prior stage loads wolfBoot. Used by the tegra234 sp fixup
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* in src/boot_aarch64_start.S. */
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.stack (NOLOAD) :
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{
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. = ALIGN(16);
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_stack_bottom = .;
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. += 0x40000; /* 256 KB */
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. = ALIGN(16);
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END_STACK = .;
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/* _end marks the top of wolfBoot's runtime footprint, so it sits
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* above the stack rather than at the end of .bss. src/update_ram.c
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* compares against it in the RAM-boot overlap guard (built only with
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* EXT_FLASH+NO_XIP), and it is the conventional heap start. */
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_end = .;
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} > DDR_MEM
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. = ALIGN(4);
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}
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/* No partition symbols here: this target builds WOLFBOOT_NO_PARTITIONS, so the
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* boot/update/DTB addresses come from hal_get_*_address() in hal/tegra234.c
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* (constants in hal/tegra234.h) and the RAM staging targets come from
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* WOLFBOOT_LOAD_ADDRESS / WOLFBOOT_LOAD_DTS_ADDRESS in the config. Defining
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* them twice only invites the two copies to disagree. */
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