mirror of https://github.com/wolfSSL/wolfBoot.git
148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
/* kontron_vx3060_s2.c
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <wolfboot/wolfboot.h>
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#include <stdint.h>
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#include <uart_drv.h>
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#include <printf.h>
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#include <pci.h>
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#include <x86/gdt.h>
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#include <x86/fsp.h>
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#include <x86/common.h>
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#ifdef __WOLFBOOT
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#define SPI_PCI_DEV 31
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#define SPI_PCI_FUN 5
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#define SPI_BAR_OFF 0x10
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#define SPI_FREG1 0x58
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#define SPI_FREG_BASE_MASK (0x7fffU << 0)
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#define SPI_FREG_LIMIT_MASK (0x7fffU << 16)
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#define SPI_FREG_LIMIT_SHIFT (16)
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#define SPI_FREG_ADDR_SHIFT (12)
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#define SPI_FPR0 (0x48)
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#define SPI_FPR_WPE (1U << 31)
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#define SPI_FPR_RPE (1U << 15)
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#define SPI_BIOS_HSFSTS_CTL (0x4)
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#define SPI_FLOCKDN (1U << 15)
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int tgl_lock_bios_region()
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{
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uint32_t spi_bar, spi_cmd;
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uint32_t reg;
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#if defined(DEBUG)
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uint32_t bios_reg_base, bios_reg_lim;
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#endif
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spi_bar = pci_config_read32(0, SPI_PCI_DEV, SPI_PCI_FUN, PCI_BAR0_OFFSET);
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spi_bar &= PCI_BAR_MASK;
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spi_cmd =
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pci_config_read32(0, SPI_PCI_DEV, SPI_PCI_FUN, PCI_COMMAND_OFFSET);
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pci_config_write32(0, SPI_PCI_DEV, SPI_PCI_FUN, PCI_COMMAND_OFFSET,
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spi_cmd | PCI_COMMAND_MEM_SPACE);
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reg = mmio_read32(spi_bar + SPI_FREG1);
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#if defined(DEBUG)
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bios_reg_base = (reg & SPI_FREG_BASE_MASK) << SPI_FREG_ADDR_SHIFT;
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bios_reg_lim = ((reg & SPI_FREG_LIMIT_MASK) >> SPI_FREG_LIMIT_SHIFT)
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<< SPI_FREG_ADDR_SHIFT;
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wolfBoot_printf("Bios reg base: 0x%x lim: 0x%x\r\n", bios_reg_base,
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bios_reg_lim);
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#endif
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/* Flash Protected Range register has very similar layout of the Flash
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* Region Register, so we can reuse it and just enable read and write
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* protection
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*/
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reg |= (SPI_FPR_RPE) | (SPI_FPR_WPE);
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pci_config_write32(0, SPI_PCI_DEV, SPI_PCI_FUN, SPI_FPR0, reg);
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/* lock down BIOS register configuration */
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reg = pci_config_read32(0, SPI_PCI_DEV, SPI_PCI_FUN, SPI_BIOS_HSFSTS_CTL);
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reg |= SPI_FLOCKDN;
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pci_config_write32(0, SPI_PCI_DEV, SPI_PCI_FUN, SPI_BIOS_HSFSTS_CTL, reg);
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/* restore original cmd */
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pci_config_write32(0, SPI_PCI_DEV, SPI_PCI_FUN, PCI_COMMAND_OFFSET, spi_cmd);
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return 0;
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}
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void hal_init(void)
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{
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gdt_setup_table();
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gdt_update_segments();
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fsp_init_silicon();
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}
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void hal_prepare_boot(void)
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{
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}
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#endif
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int hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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return 0;
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}
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void hal_flash_unlock(void)
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{
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}
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void hal_flash_lock(void)
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{
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}
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int hal_flash_erase(uint32_t address, int len)
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{
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return 0;
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}
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int wolfBoot_fallback_is_possible(void)
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{
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return 0;
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}
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int wolfBoot_dualboot_candidate(void)
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{
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return PART_BOOT;
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}
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void* hal_get_primary_address(void)
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{
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return (void*)0;
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}
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void* hal_get_update_address(void)
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{
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return (void*)0;
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}
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void *hal_get_dts_address(void)
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{
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return 0;
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}
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void *hal_get_dts_update_address(void)
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{
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return 0;
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}
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