mirror of https://github.com/wolfSSL/wolfBoot.git
214 lines
9.3 KiB
C
214 lines
9.3 KiB
C
/* mpfs250.h
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*
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* Copyright (C) 2025 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef MPFS250_DEF_INCLUDED
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#define MPFS250_DEF_INCLUDED
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/* Generic RISC-V definitions are included at the end of this file
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* (after PLIC_BASE is defined) to enable PLIC function declarations */
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/* PolarFire SoC MPFS250T board specific configuration */
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/* APB/AHB Clock Frequency */
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#define MSS_APB_AHB_CLK 150000000
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/* Hardware Base Address */
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#define SYSREG_BASE 0x20002000
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/* Write "0xDEAD" to cause a full MSS reset*/
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#define SYSREG_MSS_RESET_CR (*((volatile uint32_t*)(SYSREG_BASE + 0x18)))
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/* Peripheral Soft Reset Control Register */
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#define SYSREG_SOFT_RESET_CR (*((volatile uint32_t*)(SYSREG_BASE + 0x88)))
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#define SYSREG_SOFT_RESET_CR_ENVM (1U << 0)
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#define SYSREG_SOFT_RESET_CR_MMC (1U << 3)
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#define SYSREG_SOFT_RESET_CR_MMUART0 (1U << 5)
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#define SYSREG_SOFT_RESET_CR_MMUART1 (1U << 6)
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#define SYSREG_SOFT_RESET_CR_MMUART2 (1U << 7)
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#define SYSREG_SOFT_RESET_CR_MMUART3 (1U << 8)
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#define SYSREG_SOFT_RESET_CR_MMUART4 (1U << 9)
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#define SYSREG_SOFT_RESET_CR_SPI0 (1U << 10)
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#define SYSREG_SOFT_RESET_CR_SPI1 (1U << 11)
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#define SYSREG_SOFT_RESET_CR_QSPI (1U << 19)
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#define SYSREG_SOFT_RESET_CR_GPIO0 (1U << 20)
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#define SYSREG_SOFT_RESET_CR_GPIO1 (1U << 21)
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#define SYSREG_SOFT_RESET_CR_GPIO2 (1U << 22)
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#define SYSREG_SOFT_RESET_CR_DDRC (1U << 23)
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#define SYSREG_SOFT_RESET_CR_ATHENA (1U << 28) /* Crypto hardware accelerator */
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/* UART */
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#define MSS_UART0_LO_BASE 0x20000000UL
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#define MSS_UART1_LO_BASE 0x20100000UL
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#define MSS_UART2_LO_BASE 0x20102000UL
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#define MSS_UART3_LO_BASE 0x20104000UL
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#define MSS_UART4_LO_BASE 0x20106000UL
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#define MSS_UART0_HI_BASE 0x28000000UL
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#define MSS_UART1_HI_BASE 0x28100000UL
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#define MSS_UART2_HI_BASE 0x28102000UL
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#define MSS_UART3_HI_BASE 0x28104000UL
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#define MSS_UART4_HI_BASE 0x28106000UL
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#define MMUART_RBR(base) *((volatile uint8_t*)((base)) + 0x00) /* Receiver buffer register */
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#define MMUART_IER(base) *((volatile uint8_t*)((base)) + 0x04) /* Interrupt enable register */
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#define MMUART_IIR(base) *((volatile uint8_t*)((base)) + 0x08) /* Interrupt ID register */
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#define MMUART_LCR(base) *((volatile uint8_t*)((base)) + 0x0C) /* Line control register */
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#define MMUART_MCR(base) *((volatile uint8_t*)((base)) + 0x10) /* Modem control register */
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#define MMUART_LSR(base) *((volatile uint8_t*)((base)) + 0x14) /* Line status register */
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#define MMUART_MSR(base) *((volatile uint8_t*)((base)) + 0x18) /* Modem status register */
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#define MMUART_SCR(base) *((volatile uint8_t*)((base)) + 0x1C) /* Scratch register */
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#define MMUART_IEM(base) *((volatile uint8_t*)((base)) + 0x24) /* Interrupt enable mask */
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#define MMUART_IIM(base) *((volatile uint8_t*)((base)) + 0x28) /* multi-mode Interrupt ID register */
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#define MMUART_MM0(base) *((volatile uint8_t*)((base)) + 0x30) /* Mode register 0 */
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#define MMUART_MM1(base) *((volatile uint8_t*)((base)) + 0x34) /* Mode register 1 */
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#define MMUART_MM2(base) *((volatile uint8_t*)((base)) + 0x38) /* Mode register 2 */
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#define MMUART_DFR(base) *((volatile uint8_t*)((base)) + 0x3C) /* Data frame register */
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#define MMUART_GFR(base) *((volatile uint8_t*)((base)) + 0x44) /* Global filter register */
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#define MMUART_TTG(base) *((volatile uint8_t*)((base)) + 0x48) /* TX time guard register */
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#define MMUART_RTO(base) *((volatile uint8_t*)((base)) + 0x4C) /* RX timeout register */
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#define MMUART_ADR(base) *((volatile uint8_t*)((base)) + 0x50) /* Address register */
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#define MMUART_DLR(base) *((volatile uint8_t*)((base)) + 0x80) /* Divisor latch register */
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#define MMUART_DMR(base) *((volatile uint8_t*)((base)) + 0x84) /* Divisor mode register */
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#define MMUART_THR(base) *((volatile uint8_t*)((base)) + 0x100) /* Transmitter holding register */
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#define MMUART_FCR(base) *((volatile uint8_t*)((base)) + 0x104) /* FIFO control register */
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/* LCR (Line Control Register) */
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#define MSS_UART_DATA_8_BITS ((uint8_t)0x03)
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#define MSS_UART_NO_PARITY ((uint8_t)0x00)
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#define MSS_UART_ONE_STOP_BIT ((uint8_t)0x00)
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/* LSR (Line Status Register) */
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#define MSS_UART_THRE ((uint8_t)0x20) /* Transmitter holding register empty */
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#define MSS_UART_TEMT ((uint8_t)0x40) /* Transmit empty */
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#define ELIN_MASK (1U << 3) /* Enable LIN header detection */
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#define EIRD_MASK (1U << 2) /* Enable IrDA modem */
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#define EERR_MASK (1U << 0) /* Enable ERR / NACK during stop time */
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#define RXRDY_TXRDYN_EN_MASK (1U << 0) /* Enable TXRDY and RXRDY signals */
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#define CLEAR_RX_FIFO_MASK (1U << 1) /* Clear receiver FIFO */
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#define CLEAR_TX_FIFO_MASK (1U << 2) /* Clear transmitter FIFO */
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#define LOOP_MASK (1U << 4) /* Local loopback */
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#define RLOOP_MASK (1U << 5) /* Remote loopback & Automatic echo*/
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#define E_MSB_RX_MASK (1U << 0) /* MSB / LSB first for receiver */
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#define E_MSB_TX_MASK (1U << 1) /* MSB / LSB first for transmitter */
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#define EAFM_MASK (1U << 1) /* Enable 9-bit address flag mode */
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#define ETTG_MASK (1U << 5) /* Enable transmitter time guard */
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#define ERTO_MASK (1U << 6) /* Enable receiver time-out */
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#define ESWM_MASK (1U << 3) /* Enable single wire half-duplex mode */
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#define EFBR_MASK (1U << 7) /* Enable fractional baud rate mode */
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/* Line Control register bit masks */
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#define SB_MASK (1U << 6) /* Set break */
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#define DLAB_MASK (1U << 7) /* Divisor latch access bit */
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/* ============================================================================
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* EMMC/SD Card Controller (Cadence SD4HC)
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* Base Address: 0x20008000
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* ============================================================================ */
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#define EMMC_SD_BASE 0x20008000UL
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/* ============================================================================
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* System Controller Mailbox
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* Control Base: 0x37020000
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* Mailbox RAM: 0x37020800
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*
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* Used for system services like reading the device serial number.
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* ============================================================================ */
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#define SCBCTRL_BASE 0x37020000UL
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#define SCBMBOX_BASE 0x37020800UL
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/* System Services Control and Status Register offsets (from SCBCTRL_BASE) */
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#define SERVICES_CR_OFFSET 0x50u
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#define SERVICES_SR_OFFSET 0x54u
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/* Control Register bits */
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#define SERVICES_CR_REQ_MASK 0x01u
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#define SERVICES_CR_COMMAND_SHIFT 16
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/* Status Register bits */
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#define SERVICES_SR_BUSY_MASK 0x02u
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#define SERVICES_SR_STATUS_SHIFT 16
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/* System Service command opcodes */
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#define SYS_SERV_CMD_SERIAL_NUMBER 0x00u
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/* Device serial number size in bytes */
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#define DEVICE_SERIAL_NUMBER_SIZE 16
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/* System Controller register access */
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#define SCBCTRL_REG(off) (*((volatile uint32_t*)(SCBCTRL_BASE + (off))))
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#define SCBMBOX_REG(off) (*((volatile uint32_t*)(SCBMBOX_BASE + (off))))
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#define SCBMBOX_BYTE(off) (*((volatile uint8_t*)(SCBMBOX_BASE + (off))))
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/* Crypto Engine: Athena F5200 TeraFire Crypto Processor (1x), 200 MHz */
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#define ATHENA_BASE (SYSREG_BASE + 0x125000)
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/* ============================================================================
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* PLIC - Platform-Level Interrupt Controller (MPFS250-specific configuration)
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* Base Address: 0x0c000000, Size: 64MB
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*
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* Generic PLIC register access is provided by hal/riscv.h
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* ============================================================================ */
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#define PLIC_BASE 0x0C000000UL
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#define PLIC_SIZE 0x04000000UL /* 64MB */
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/* Number of interrupt sources and contexts */
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#define PLIC_NUM_SOURCES 186 /* riscv,ndev = 0xBA = 186 */
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#define PLIC_NUM_HARTS 5 /* 1x E51 + 4x U54 */
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#define PLIC_NUM_CONTEXTS 10 /* 2 contexts per hart (M-mode + S-mode) */
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/* MSS Global Interrupt offset - PLIC interrupts 0-12 are local, 13+ are MSS */
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#define OFFSET_TO_MSS_GLOBAL_INTS 13
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/* PLIC Interrupt Sources (PLIC IRQ numbers) */
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#define PLIC_INT_MMC_MAIN 88 /* MMC/SD controller main interrupt */
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#define PLIC_INT_MMC_WAKEUP 89 /* MMC/SD controller wakeup interrupt */
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/* PLIC Context IDs for each hart
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* Hart 0 (E51): Context 0 = M-mode (no S-mode on E51)
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* Hart 1 (U54): Context 1 = M-mode, Context 2 = S-mode
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* Hart 2 (U54): Context 3 = M-mode, Context 4 = S-mode
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* Hart 3 (U54): Context 5 = M-mode, Context 6 = S-mode
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* Hart 4 (U54): Context 7 = M-mode, Context 8 = S-mode
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*/
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#define PLIC_CONTEXT_E51_M 0
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#define PLIC_CONTEXT_U54_1_M 1
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#define PLIC_CONTEXT_U54_1_S 2
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#define PLIC_CONTEXT_U54_2_M 3
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#define PLIC_CONTEXT_U54_2_S 4
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#define PLIC_CONTEXT_U54_3_M 5
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#define PLIC_CONTEXT_U54_3_S 6
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#define PLIC_CONTEXT_U54_4_M 7
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#define PLIC_CONTEXT_U54_4_S 8
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#endif /* MPFS250_DEF_INCLUDED */
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