mirror of https://github.com/wolfSSL/wolfBoot.git
902 lines
52 KiB
C
902 lines
52 KiB
C
/* mpfs250.h
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*
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* Copyright (C) 2025 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef MPFS250_DEF_INCLUDED
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#define MPFS250_DEF_INCLUDED
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/* PolarFire SoC MPFS250T board specific configuration */
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/* APB/AHB Clock Frequency */
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#define MSS_APB_AHB_CLK 150000000
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/* Hardware Base Address */
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#define SYSREG_BASE 0x20002000
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/* Write "0xDEAD" to cause a full MSS reset*/
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#define SYSREG_MSS_RESET_CR (*((volatile uint32_t*)(SYSREG_BASE + 0x18)))
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/* Peripheral Soft Reset Control Register */
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#define SYSREG_SOFT_RESET_CR (*((volatile uint32_t*)(SYSREG_BASE + 0x88)))
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#define SYSREG_SOFT_RESET_CR_ENVM (1U << 0)
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#define SYSREG_SOFT_RESET_CR_MMC (1U << 3)
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#define SYSREG_SOFT_RESET_CR_MMUART0 (1U << 5)
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#define SYSREG_SOFT_RESET_CR_MMUART1 (1U << 6)
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#define SYSREG_SOFT_RESET_CR_MMUART2 (1U << 7)
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#define SYSREG_SOFT_RESET_CR_MMUART3 (1U << 8)
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#define SYSREG_SOFT_RESET_CR_MMUART4 (1U << 9)
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#define SYSREG_SOFT_RESET_CR_SPI0 (1U << 10)
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#define SYSREG_SOFT_RESET_CR_SPI1 (1U << 11)
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#define SYSREG_SOFT_RESET_CR_QSPI (1U << 19)
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#define SYSREG_SOFT_RESET_CR_GPIO0 (1U << 20)
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#define SYSREG_SOFT_RESET_CR_GPIO1 (1U << 21)
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#define SYSREG_SOFT_RESET_CR_GPIO2 (1U << 22)
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#define SYSREG_SOFT_RESET_CR_DDRC (1U << 23)
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#define SYSREG_SOFT_RESET_CR_ATHENA (1U << 28) /* Crypto hardware accelerator */
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/* TODO: Add support for machine mode wolfBoot */
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#if 1
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#define WOLFBOOT_RISCV_SMODE /* supervisor mode */
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#else
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#define WOLFBOOT_RISCV_MMODE /* machine mode */
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#endif
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/* size of each trap frame register */
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#define REGBYTES (1 << 3)
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/* Machine Information Registers */
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#define CSR_MVENDORID 0xF11
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#define CSR_MARCHID 0xF12
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#define CSR_MIMPID 0xF13
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#define CSR_MHARTID 0xF14
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/* Initial stack pointer address (stack grows downward from here) */
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#ifdef WOLFBOOT_RISCV_SMODE
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#define WOLFBOOT_STACK_TOP 0x80200000
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#else
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#define WOLFBOOT_STACK_TOP 0x80000000
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#endif
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#ifdef WOLFBOOT_RISCV_SMODE
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#define MODE_PREFIX(__suffix) s##__suffix
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#else
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#define MODE_PREFIX(__suffix) m##__suffix
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#endif
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/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
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#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_U_TIMER 4
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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#define MIE_MSIE (1 << IRQ_M_SOFT)
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#define SIE_SSIE (1 << IRQ_S_SOFT)
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#define SIE_STIE (1 << IRQ_S_TIMER)
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#define SIE_SEIE (1 << IRQ_S_EXT)
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#define MCAUSE64_INT 0x8000000000000000LLU
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#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFFLLU
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/* UART */
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#define MSS_UART0_LO_BASE 0x20000000UL
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#define MSS_UART1_LO_BASE 0x20100000UL
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#define MSS_UART2_LO_BASE 0x20102000UL
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#define MSS_UART3_LO_BASE 0x20104000UL
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#define MSS_UART4_LO_BASE 0x20106000UL
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#define MSS_UART0_HI_BASE 0x28000000UL
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#define MSS_UART1_HI_BASE 0x28100000UL
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#define MSS_UART2_HI_BASE 0x28102000UL
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#define MSS_UART3_HI_BASE 0x28104000UL
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#define MSS_UART4_HI_BASE 0x28106000UL
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#define MMUART_RBR(base) *((volatile uint8_t*)((base)) + 0x00) /* Receiver buffer register */
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#define MMUART_IER(base) *((volatile uint8_t*)((base)) + 0x04) /* Interrupt enable register */
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#define MMUART_IIR(base) *((volatile uint8_t*)((base)) + 0x08) /* Interrupt ID register */
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#define MMUART_LCR(base) *((volatile uint8_t*)((base)) + 0x0C) /* Line control register */
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#define MMUART_MCR(base) *((volatile uint8_t*)((base)) + 0x10) /* Modem control register */
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#define MMUART_LSR(base) *((volatile uint8_t*)((base)) + 0x14) /* Line status register */
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#define MMUART_MSR(base) *((volatile uint8_t*)((base)) + 0x18) /* Modem status register */
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#define MMUART_SCR(base) *((volatile uint8_t*)((base)) + 0x1C) /* Scratch register */
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#define MMUART_IEM(base) *((volatile uint8_t*)((base)) + 0x24) /* Interrupt enable mask */
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#define MMUART_IIM(base) *((volatile uint8_t*)((base)) + 0x28) /* multi-mode Interrupt ID register */
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#define MMUART_MM0(base) *((volatile uint8_t*)((base)) + 0x30) /* Mode register 0 */
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#define MMUART_MM1(base) *((volatile uint8_t*)((base)) + 0x34) /* Mode register 1 */
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#define MMUART_MM2(base) *((volatile uint8_t*)((base)) + 0x38) /* Mode register 2 */
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#define MMUART_DFR(base) *((volatile uint8_t*)((base)) + 0x3C) /* Data frame register */
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#define MMUART_GFR(base) *((volatile uint8_t*)((base)) + 0x44) /* Global filter register */
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#define MMUART_TTG(base) *((volatile uint8_t*)((base)) + 0x48) /* TX time guard register */
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#define MMUART_RTO(base) *((volatile uint8_t*)((base)) + 0x4C) /* RX timeout register */
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#define MMUART_ADR(base) *((volatile uint8_t*)((base)) + 0x50) /* Address register */
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#define MMUART_DLR(base) *((volatile uint8_t*)((base)) + 0x80) /* Divisor latch register */
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#define MMUART_DMR(base) *((volatile uint8_t*)((base)) + 0x84) /* Divisor mode register */
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#define MMUART_THR(base) *((volatile uint8_t*)((base)) + 0x100) /* Transmitter holding register */
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#define MMUART_FCR(base) *((volatile uint8_t*)((base)) + 0x104) /* FIFO control register */
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/* LCR (Line Control Register) */
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#define MSS_UART_DATA_8_BITS ((uint8_t)0x03)
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#define MSS_UART_NO_PARITY ((uint8_t)0x00)
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#define MSS_UART_ONE_STOP_BIT ((uint8_t)0x00)
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/* LSR (Line Status Register) */
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#define MSS_UART_THRE ((uint8_t)0x20) /* Transmitter holding register empty */
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#define MSS_UART_TEMT ((uint8_t)0x40) /* Transmit empty */
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#define ELIN_MASK (1U << 3) /* Enable LIN header detection */
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#define EIRD_MASK (1U << 2) /* Enable IrDA modem */
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#define EERR_MASK (1U << 0) /* Enable ERR / NACK during stop time */
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#define RXRDY_TXRDYN_EN_MASK (1U << 0) /* Enable TXRDY and RXRDY signals */
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#define CLEAR_RX_FIFO_MASK (1U << 1) /* Clear receiver FIFO */
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#define CLEAR_TX_FIFO_MASK (1U << 2) /* Clear transmitter FIFO */
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#define LOOP_MASK (1U << 4) /* Local loopback */
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#define RLOOP_MASK (1U << 5) /* Remote loopback & Automatic echo*/
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#define E_MSB_RX_MASK (1U << 0) /* MSB / LSB first for receiver */
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#define E_MSB_TX_MASK (1U << 1) /* MSB / LSB first for transmitter */
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#define EAFM_MASK (1U << 1) /* Enable 9-bit address flag mode */
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#define ETTG_MASK (1U << 5) /* Enable transmitter time guard */
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#define ERTO_MASK (1U << 6) /* Enable receiver time-out */
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#define ESWM_MASK (1U << 3) /* Enable single wire half-duplex mode */
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#define EFBR_MASK (1U << 7) /* Enable fractional baud rate mode */
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/* Line Control register bit masks */
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#define SB_MASK (1U << 6) /* Set break */
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#define DLAB_MASK (1U << 7) /* Divisor latch access bit */
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/* ============================================================================
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* EMMC/SD Card Controller (Cadence SD4HC)
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* Base Address: 0x20008000
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* ============================================================================ */
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#define EMMC_SD_BASE 0x20008000UL
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/* ----------------------------------------------------------------------------
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* HRS - Host Register Set (Cadence-specific registers)
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* ---------------------------------------------------------------------------- */
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/* HRS00 - General Information Register */
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#define EMMC_SD_HRS00 *((volatile uint32_t*)(EMMC_SD_BASE + 0x000))
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#define EMMC_SD_HRS00_SAV_SHIFT 16 /* 23:16: RO - Number of slots */
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#define EMMC_SD_HRS00_SAV_MASK (0xFFU << 16)
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#define EMMC_SD_HRS00_SWR (1U << 0) /* 0: RW - Software Reset (entire core) */
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/* HRS01 - Debounce Setting Register */
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#define EMMC_SD_HRS01 *((volatile uint32_t*)(EMMC_SD_BASE + 0x004))
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#define EMMC_SD_HRS01_DP_SHIFT 0 /* 23:0: RW - Debounce Period */
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#define EMMC_SD_HRS01_DP_MASK (0xFFFFFFU << 0)
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/* HRS02 - Bus Setting Register */
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#define EMMC_SD_HRS02 *((volatile uint32_t*)(EMMC_SD_BASE + 0x008))
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#define EMMC_SD_HRS02_OTN_SHIFT 16 /* 17:16: RW - Outstanding Transactions Number */
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#define EMMC_SD_HRS02_OTN_MASK (0x3U << 16)
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#define EMMC_SD_HRS02_PBL_SHIFT 0 /* 3:0: RW - Programmable Burst Length */
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#define EMMC_SD_HRS02_PBL_MASK (0xFU << 0)
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/* HRS03 - AXI ERROR Responses Register */
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#define EMMC_SD_HRS03 *((volatile uint32_t*)(EMMC_SD_BASE + 0x00C))
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#define EMMC_SD_HRS03_AER_IEBS (1U << 19) /* 19: Int Enable Bus Status */
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#define EMMC_SD_HRS03_AER_IEBD (1U << 18) /* 18: Int Enable Bus Data */
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#define EMMC_SD_HRS03_AER_IERS (1U << 17) /* 17: Int Enable Resp Status */
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#define EMMC_SD_HRS03_AER_IERD (1U << 16) /* 16: Int Enable Resp Data */
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#define EMMC_SD_HRS03_AER_SENBS (1U << 11) /* 11: Status Enable Bus Status */
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#define EMMC_SD_HRS03_AER_SENBD (1U << 10) /* 10: Status Enable Bus Data */
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#define EMMC_SD_HRS03_AER_SENRS (1U << 9) /* 9: Status Enable Resp Status */
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#define EMMC_SD_HRS03_AER_SENRD (1U << 8) /* 8: Status Enable Resp Data */
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/* HRS04 - PHY Registers Interface (SD/eMMC PHY access) */
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#define EMMC_SD_HRS04 *((volatile uint32_t*)(EMMC_SD_BASE + 0x010))
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#define EMMC_SD_HRS04_UIS_ACK (1U << 26) /* 26: RO - PHY Acknowledge */
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#define EMMC_SD_HRS04_UIS_RD (1U << 25) /* 25: RW - PHY Read Request */
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#define EMMC_SD_HRS04_UIS_WR (1U << 24) /* 24: RW - PHY Write Request */
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#define EMMC_SD_HRS04_UIS_RDATA_SHIFT 16 /* 23:16: RO - PHY Read Data */
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#define EMMC_SD_HRS04_UIS_RDATA_MASK (0xFFU << 16)
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#define EMMC_SD_HRS04_UIS_WDATA_SHIFT 8 /* 15:8: RW - PHY Write Data */
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#define EMMC_SD_HRS04_UIS_WDATA_MASK (0xFFU << 8)
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#define EMMC_SD_HRS04_UIS_ADDR_SHIFT 0 /* 5:0: RW - PHY Register Address */
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#define EMMC_SD_HRS04_UIS_ADDR_MASK (0x3FU << 0)
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/* PHY register addresses */
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#define EMMC_SD_PHY_ADDR_HIGH_SPEED 0x00U
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#define EMMC_SD_PHY_ADDR_DEFAULT_SPEED 0x01U
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#define EMMC_SD_PHY_ADDR_UHSI_SDR12 0x02U
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#define EMMC_SD_PHY_ADDR_UHSI_SDR25 0x03U
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#define EMMC_SD_PHY_ADDR_UHSI_SDR50 0x04U
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#define EMMC_SD_PHY_ADDR_UHSI_DDR50 0x05U
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#define EMMC_SD_PHY_ADDR_MMC_LEGACY 0x06U
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#define EMMC_SD_PHY_ADDR_MMC_SDR 0x07U
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#define EMMC_SD_PHY_ADDR_MMC_DDR 0x08U
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#define EMMC_SD_PHY_ADDR_SDCLK 0x0BU
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#define EMMC_SD_PHY_ADDR_HS_SDCLK 0x0CU
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#define EMMC_SD_PHY_ADDR_DAT_STROBE 0x0DU
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/* HRS06 - eMMC Control Register */
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#define EMMC_SD_HRS06 *((volatile uint32_t*)(EMMC_SD_BASE + 0x018))
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#define EMMC_SD_HRS06_ETR (1U << 15) /* 15: RW - eMMC Tune Request */
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#define EMMC_SD_HRS06_ETV_SHIFT 8 /* eMMC Tune Value */
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#define EMMC_SD_HRS06_ETV_MASK 0x3FU
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#define EMMC_SD_HRS06_EMM_SHIFT 0 /* 2:0: RW - eMMC Mode Select */
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#define EMMC_SD_HRS06_EMM_MASK (0x7U << 0)
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/* eMMC Mode values */
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#define EMMC_SD_HRS06_MODE_SD (0x0U << 0) /* SD card mode */
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#define EMMC_SD_HRS06_MODE_MMC_SDR (0x2U << 0) /* eMMC SDR mode */
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#define EMMC_SD_HRS06_MODE_MMC_DDR (0x3U << 0) /* eMMC DDR mode */
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#define EMMC_SD_HRS06_MODE_MMC_HS200 (0x4U << 0) /* eMMC HS200 mode */
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#define EMMC_SD_HRS06_MODE_MMC_HS400 (0x5U << 0) /* eMMC HS400 mode */
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#define EMMC_SD_HRS06_MODE_MMC_HS400ES (0x6U << 0) /* eMMC HS400 Enhanced Strobe */
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#define EMMC_SD_HRS06_MODE_LEGACY (0x7U << 0) /* Legacy mode */
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/* HRS07 - IO Delay Information Register */
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#define EMMC_SD_HRS07 *((volatile uint32_t*)(EMMC_SD_BASE + 0x01C))
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#define EMMC_SD_HRS07_ODELAY_VAL_SHIFT 16 /* 20:16: RW - Output Delay Value */
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#define EMMC_SD_HRS07_ODELAY_VAL_MASK (0x1FU << 16)
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#define EMMC_SD_HRS07_IDELAY_VAL_SHIFT 0 /* 4:0: RW - Input Delay Value */
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#define EMMC_SD_HRS07_IDELAY_VAL_MASK (0x1FU << 0)
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#define EMMC_SD_HRS30 *((volatile uint32_t*)(EMMC_SD_BASE + 0x078)) /* Host Capability Register */
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#define EMMC_SD_HRS30_HS400ESSUP (1U << 1) /* 1: RO - HS400 Enhanced Strobe Support */
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#define EMMC_SD_HRS30_CQSUP (1U << 0) /* 0: RO - Command Queuing Support */
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#define EMMC_SD_HRS31 *((volatile uint32_t*)(EMMC_SD_BASE + 0x07C)) /* Host Controller Version */
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#define EMMC_SD_HRS31_HOSTCTRLVER_SHIFT 16 /* 27:16: RO */
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#define EMMC_SD_HRS31_HOSTCTRLVER_MASK (0xFFFU << 16)
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#define EMMC_SD_HRS31_HOSTFIXVER_SHIFT 0 /* 7:0: RO */
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#define EMMC_SD_HRS31_HOSTFIXVER_MASK (0xFFU << 0)
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#define EMMC_SD_HRS32 *((volatile uint32_t*)(EMMC_SD_BASE + 0x080)) /* FSM Monitor Register */
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#define EMMC_SD_HRS32_LOAD (1U << 31) /* 31: RW */
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#define EMMC_SD_HRS32_ADDR_SHIFT 16 /* 30:16: WO */
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#define EMMC_SD_HRS32_ADDR_MASK (0x7FFFU << 16)
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#define EMMC_SD_HRS32_DATA_SHIFT 0 /* 15:0: RO */
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#define EMMC_SD_HRS32_DATA_MASK (0xFFFFU << 0)
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#define EMMC_SD_HRS33 *((volatile uint32_t*)(EMMC_SD_BASE + 0x084)) /* Tune Status 0 Register */
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#define EMMC_SD_HRS33_STAT0_SHIFT 0 /* 31:0: RO */
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#define EMMC_SD_HRS33_STAT0_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_HRS34 *((volatile uint32_t*)(EMMC_SD_BASE + 0x088)) /* Tune Status 1 Register */
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#define EMMC_SD_HRS34_STAT1_SHIFT 0 /* 7:0: RO */
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#define EMMC_SD_HRS34_STAT1_MASK (0xFFU << 0)
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#define EMMC_SD_HRS35 *((volatile uint32_t*)(EMMC_SD_BASE + 0x08C)) /* Tune Debug Register */
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#define EMMC_SD_HRS35_TFR (1U << 31) /* 31: RW */
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#define EMMC_SD_HRS35_TFV_SHIFT 16 /* 21:16: RW */
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#define EMMC_SD_HRS35_TFV_MASK (0x3FU << 16)
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#define EMMC_SD_HRS35_TVAL_SHIFT 0 /* 5:0: RO */
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#define EMMC_SD_HRS35_TVAL_MASK (0x3FU << 0)
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#define EMMC_SD_HRS36 *((volatile uint32_t*)(EMMC_SD_BASE + 0x090)) /* Boot Status Register */
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#define EMMC_SD_HRS36_BOOT_EDE (1U << 5) /* 5: RO - Boot Error Data End Bit */
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#define EMMC_SD_HRS36_BOOT_EDC (1U << 4) /* 4: RO - Boot Error Data CRC */
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#define EMMC_SD_HRS36_BOOT_EDT (1U << 3) /* 3: RO - Boot Error Data Timeout */
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#define EMMC_SD_HRS36_BOOT_EAI (1U << 2) /* 2: RO - Boot Error Ack Index */
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#define EMMC_SD_HRS36_BOOT_EAT (1U << 1) /* 1: RO - Boot Error Ack Timeout */
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#define EMMC_SD_HRS36_BOOT_ACT (1U << 0) /* 0: RO - Boot Active */
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#define EMMC_SD_HRS37 *((volatile uint32_t*)(EMMC_SD_BASE + 0x094)) /* Read block gap coeff interface mode select */
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#define EMMC_SD_HRS37_RGB_COEFF_IFM_SHIFT 0 /* 5:0: RW */
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#define EMMC_SD_HRS37_RGB_COEFF_IFM_MASK (0x3FU << 0)
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#define EMMC_SD_HRS38 *((volatile uint32_t*)(EMMC_SD_BASE + 0x098)) /* Read block gap coefficient */
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#define EMMC_SD_HRS38_RGB_COEFF_SHIFT 0 /* 3:0: RW */
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#define EMMC_SD_HRS38_RGB_COEFF_MASK (0xFU << 0)
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/* CRS - Capability Register Set */
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#define EMMC_SD_CRS63 *((volatile uint32_t*)(EMMC_SD_BASE + 0x0FC)) /* Host Controller Version/Slot Interrupt Status */
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#define EMMC_SD_CRS63_SVN_SHIFT 16 /* 23:16: RO */
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#define EMMC_SD_CRS63_SVN_MASK (0xFFU << 16)
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#define EMMC_SD_CRS63_ISES_SHIFT 0 /* 7:0: RO */
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#define EMMC_SD_CRS63_ISES_MASK (0xFFU << 0)
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/* ----------------------------------------------------------------------------
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* SRS - Slot Register Set (SD Host Controller Standard Registers)
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* ---------------------------------------------------------------------------- */
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/* SRS00 - SDMA System Address / Argument 2 (for Auto CMD23) */
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#define EMMC_SD_SRS00 *((volatile uint32_t*)(EMMC_SD_BASE + 0x200))
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#define EMMC_SD_SRS00_SAAR_SHIFT 0 /* 31:0: RW */
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#define EMMC_SD_SRS00_SAAR_MASK (0xFFFFFFFFU << 0)
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/* SRS01 - Block Size / Block Count Register */
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#define EMMC_SD_SRS01 *((volatile uint32_t*)(EMMC_SD_BASE + 0x204))
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#define EMMC_SD_SRS01_BCCT_SHIFT 16 /* 31:16: RW - Block Count for Current Transfer */
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#define EMMC_SD_SRS01_BCCT_MASK (0xFFFFU << 16)
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#define EMMC_SD_SRS01_SDMABB_SHIFT 12 /* SDMA Buffer Boundary */
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#define EMMC_SD_SRS01_SDMABB_MASK 0x7U
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#define EMMC_SD_SRS01_DMA_BUFF_4KB (0x0U << 12) /* DMA buffer 4KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_8KB (0x1U << 12) /* DMA buffer 8KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_16KB (0x2U << 12) /* DMA buffer 16KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_32KB (0x3U << 12) /* DMA buffer 32KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_64KB (0x4U << 12) /* DMA buffer 64KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_128KB (0x5U << 12) /* DMA buffer 128KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_256KB (0x6U << 12) /* DMA buffer 256KB boundary */
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#define EMMC_SD_SRS01_DMA_BUFF_512KB (0x7U << 12) /* DMA buffer 512KB boundary */
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#define EMMC_SD_SRS01_TBS_SHIFT 0 /* 11:0: RW - Transfer Block Size */
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#define EMMC_SD_SRS01_TBS_MASK (0xFFFU << 0)
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/* SRS02 - Argument 1 Register */
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#define EMMC_SD_SRS02 *((volatile uint32_t*)(EMMC_SD_BASE + 0x208))
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#define EMMC_SD_SRS02_ARG1_SHIFT 0 /* 31:0: RW */
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#define EMMC_SD_SRS02_ARG1_MASK (0xFFFFFFFFU << 0)
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/* SRS03 - Command/Transfer Mode Register */
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#define EMMC_SD_SRS03 *((volatile uint32_t*)(EMMC_SD_BASE + 0x20C))
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#define EMMC_SD_SRS03_CIDX_SHIFT 24 /* 29:24: RW - Command Index */
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#define EMMC_SD_SRS03_CIDX_MASK (0x3FU << 24)
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#define EMMC_SD_SRS03_CT_SHIFT 22 /* 23:22: RW - Command Type */
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#define EMMC_SD_SRS03_CT_MASK (0x3U << 22)
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#define EMMC_SD_SRS03_CMD_NORMAL (0x0U << 22) /* Normal command */
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#define EMMC_SD_SRS03_CMD_SUSPEND (0x1U << 22) /* Suspend command */
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#define EMMC_SD_SRS03_CMD_RESUME (0x2U << 22) /* Resume command */
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#define EMMC_SD_SRS03_CMD_ABORT (0x3U << 22) /* Abort command (CMD12, CMD52) */
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#define EMMC_SD_SRS03_DPS (1U << 21) /* 21: RW - Data Present Select */
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#define EMMC_SD_SRS03_CICE (1U << 20) /* 20: RW - Command Index Check Enable */
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#define EMMC_SD_SRS03_CRCCE (1U << 19) /* 19: RW - Command CRC Check Enable */
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#define EMMC_SD_SRS03_RTS_SHIFT 16 /* Response Type Select */
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#define EMMC_SD_SRS03_RTS_MASK 0x3U
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#define EMMC_SD_SRS03_RESP_NONE (0x0U << 16) /* No response */
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#define EMMC_SD_SRS03_RESP_136 (0x1U << 16) /* Response length 136 bits */
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#define EMMC_SD_SRS03_RESP_48 (0x2U << 16) /* Response length 48 bits */
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#define EMMC_SD_SRS03_RESP_48B (0x3U << 16) /* Response length 48 bits + busy */
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#define EMMC_SD_SRS03_RID (1U << 8) /* 8: RW - Response Interrupt Disable */
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#define EMMC_SD_SRS03_RECE (1U << 7) /* 7: RW - Response Error Check Enable */
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#define EMMC_SD_SRS03_RECT (1U << 6) /* 6: RW - Response Check Type (R1/R5) */
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#define EMMC_SD_SRS03_MSBS (1U << 5) /* 5: RW - Multi/Single Block Select */
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#define EMMC_SD_SRS03_DTDS (1U << 4) /* 4: RW - Data Transfer Direction (1=read) */
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#define EMMC_SD_SRS03_ACE_SHIFT 2 /* 3:2: RW - Auto CMD Enable */
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#define EMMC_SD_SRS03_ACE_MASK (0x3U << 2)
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#define EMMC_SD_SRS03_ACMD_DISABLE (0x0U << 2) /* Auto CMD disabled */
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#define EMMC_SD_SRS03_ACMD12 (0x1U << 2) /* Auto CMD12 enable */
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#define EMMC_SD_SRS03_ACMD23 (0x2U << 2) /* Auto CMD23 enable */
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#define EMMC_SD_SRS03_BCE (1U << 1) /* 1: RW - Block Count Enable */
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#define EMMC_SD_SRS03_DMAE (1U << 0) /* 0: RW - DMA Enable */
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#define EMMC_SD_SRS04 *((volatile uint32_t*)(EMMC_SD_BASE + 0x210)) /* Response Register 1 */
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#define EMMC_SD_SRS04_RESP1_SHIFT 0 /* 31:0: RO */
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#define EMMC_SD_SRS04_RESP1_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_SRS05 *((volatile uint32_t*)(EMMC_SD_BASE + 0x214)) /* Response Register 2 */
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#define EMMC_SD_SRS05_RESP2_SHIFT 0 /* 31:0: RO */
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#define EMMC_SD_SRS05_RESP2_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_SRS06 *((volatile uint32_t*)(EMMC_SD_BASE + 0x218)) /* Response Register 3 */
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#define EMMC_SD_SRS06_RESP3_SHIFT 0 /* 31:0: RO */
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#define EMMC_SD_SRS06_RESP3_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_SRS07 *((volatile uint32_t*)(EMMC_SD_BASE + 0x21C)) /* Response Register 4 */
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#define EMMC_SD_SRS07_RESP4_SHIFT 0 /* 31:0: RO */
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#define EMMC_SD_SRS07_RESP4_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_SRS08 *((volatile uint32_t*)(EMMC_SD_BASE + 0x220)) /* Data Buffer */
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#define EMMC_SD_SRS08_BDP_SHIFT 0 /* 31:0: RW */
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#define EMMC_SD_SRS08_BDP_MASK (0xFFFFFFFFU << 0)
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/* SRS09 - Present State Register */
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#define EMMC_SD_SRS09 *((volatile uint32_t*)(EMMC_SD_BASE + 0x224))
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#define EMMC_SD_SRS09_CMDSL (1U << 24) /* 24: RO - CMD Line Signal Level */
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#define EMMC_SD_SRS09_DATSL1_SHIFT 20 /* 23:20: RO - DAT[3:0] Line Signal Level */
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#define EMMC_SD_SRS09_DATSL1_MASK (0xFU << 20)
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#define EMMC_SD_SRS09_DAT3_LVL (1U << 23) /* 23: RO - DAT3 signal level */
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#define EMMC_SD_SRS09_DAT2_LVL (1U << 22) /* 22: RO - DAT2 signal level */
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#define EMMC_SD_SRS09_DAT1_LVL (1U << 21) /* 21: RO - DAT1 signal level */
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#define EMMC_SD_SRS09_DAT0_LVL (1U << 20) /* 20: RO - DAT0 signal level */
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#define EMMC_SD_SRS09_DATS_LVL (EMMC_SD_SRS09_DAT0_LVL | EMMC_SD_SRS09_DAT1_LVL | EMMC_SD_SRS09_DAT2_LVL | EMMC_SD_SRS09_DAT3_LVL)
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#define EMMC_SD_SRS09_WPSL (1U << 19) /* 19: RO - Write Protect Switch Level */
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#define EMMC_SD_SRS09_CDSL (1U << 18) /* 18: RO - Card Detect Pin Level */
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#define EMMC_SD_SRS09_CSS (1U << 17) /* 17: RO - Card State Stable */
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#define EMMC_SD_SRS09_CI (1U << 16) /* 16: RO - Card Inserted */
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#define EMMC_SD_SRS09_BRE (1U << 11) /* 11: RO - Buffer Read Enable */
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#define EMMC_SD_SRS09_BWE (1U << 10) /* 10: RO - Buffer Write Enable */
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#define EMMC_SD_SRS09_RTA (1U << 9) /* 9: RO - Read Transfer Active */
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#define EMMC_SD_SRS09_WTA (1U << 8) /* 8: RO - Write Transfer Active */
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#define EMMC_SD_SRS09_DATSL2_SHIFT 4 /* 7:4: RO - DAT[7:4] Line Signal Level */
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#define EMMC_SD_SRS09_DATSL2_MASK (0xFU << 4)
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#define EMMC_SD_SRS09_DLA (1U << 2) /* 2: RO - DAT Line Active */
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#define EMMC_SD_SRS09_CIDAT (1U << 1) /* 1: RO - Command Inhibit (DAT) */
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#define EMMC_SD_SRS09_CICMD (1U << 0) /* 0: RO - Command Inhibit (CMD) */
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/* SRS10 - Host Control 1 Register (Power/Block-Gap/Wake-Up) */
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#define EMMC_SD_SRS10 *((volatile uint32_t*)(EMMC_SD_BASE + 0x228))
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#define EMMC_SD_SRS10_WORM (1U << 26) /* 26: RW - Wakeup on Card Removal */
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#define EMMC_SD_SRS10_WOIS (1U << 25) /* 25: RW - Wakeup on Card Insertion */
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#define EMMC_SD_SRS10_WOIQ (1U << 24) /* 24: RW - Wakeup on Card Interrupt */
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#define EMMC_SD_SRS10_IBG (1U << 19) /* 19: RW - Interrupt at Block Gap */
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#define EMMC_SD_SRS10_RWC (1U << 18) /* 18: RW - Read Wait Control */
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#define EMMC_SD_SRS10_CREQ (1U << 17) /* 17: RW - Continue Request */
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#define EMMC_SD_SRS10_SBGR (1U << 16) /* 16: RW - Stop at Block Gap Request */
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#define EMMC_SD_SRS10_BVS2_SHIFT 13 /* 15:13: RW - SD Bus Voltage Select (VDD2) */
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#define EMMC_SD_SRS10_BVS2_MASK (0x7U << 13)
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#define EMMC_SD_SRS10_BP2 (1U << 12) /* 12: RW - Bus Power (VDD2) */
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#define EMMC_SD_SRS10_BVS_SHIFT 9 /* 11:9: RW - SD Bus Voltage Select */
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#define EMMC_SD_SRS10_BVS_MASK (0x7U << 9)
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#define EMMC_SD_SRS10_BVS_3_3V (0x7U << 9) /* SD bus voltage 3.3V */
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#define EMMC_SD_SRS10_BVS_3_0V (0x6U << 9) /* SD bus voltage 3.0V */
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#define EMMC_SD_SRS10_BVS_1_8V (0x5U << 9) /* SD bus voltage 1.8V */
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#define EMMC_SD_SRS10_BVS_CLR (0x7U << 9) /* Clear voltage field mask */
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#define EMMC_SD_SRS10_BP (1U << 8) /* 8: RW - SD Bus Power */
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/* Power-on sequences: combine voltage selection with bus power enable */
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#define EMMC_SD_SRS10_PWR_3_3V (EMMC_SD_SRS10_BVS_3_3V | EMMC_SD_SRS10_BP)
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#define EMMC_SD_SRS10_PWR_3_0V (EMMC_SD_SRS10_BVS_3_0V | EMMC_SD_SRS10_BP)
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#define EMMC_SD_SRS10_PWR_1_8V (EMMC_SD_SRS10_BVS_1_8V | EMMC_SD_SRS10_BP)
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#define EMMC_SD_SRS10_CDSS (1U << 7) /* 7: RW - Card Detect Signal Selection */
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#define EMMC_SD_SRS10_CDTL (1U << 6) /* 6: RW - Card Detect Test Level */
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#define EMMC_SD_SRS10_EDTW (1U << 5) /* 5: RW - Extended Data Transfer Width (8-bit) */
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#define EMMC_SD_SRS10_DMASEL_SHIFT 3 /* 4:3: RW - DMA Select */
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#define EMMC_SD_SRS10_DMASEL_MASK (0x3U << 3)
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#define EMMC_SD_SRS10_DMA_SDMA (0x0U << 3) /* SDMA mode */
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#define EMMC_SD_SRS10_DMA_ADMA1 (0x1U << 3) /* ADMA1 mode */
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#define EMMC_SD_SRS10_DMA_ADMA2 (0x2U << 3) /* ADMA2 mode */
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#define EMMC_SD_SRS10_HSE (1U << 2) /* 2: RW - High Speed Enable */
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#define EMMC_SD_SRS10_DTW (1U << 1) /* 1: RW - Data Transfer Width (1=4-bit) */
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#define EMMC_SD_SRS10_LEDC (1U << 0) /* 0: RW - LED Control */
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/* SRS11 - Host Control 2 Register (Clock/Timeout/Reset) */
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#define EMMC_SD_SRS11 *((volatile uint32_t*)(EMMC_SD_BASE + 0x22C))
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#define EMMC_SD_SRS11_SRDA (1U << 26) /* 26: RW - Software Reset for DAT Line */
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#define EMMC_SD_SRS11_SRCD (1U << 25) /* 25: RW - Software Reset for CMD Line */
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#define EMMC_SD_SRS11_SRFA (1U << 24) /* 24: RW - Software Reset for All */
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#define EMMC_SD_SRS11_RESET_DAT_CMD (EMMC_SD_SRS11_SRDA | EMMC_SD_SRS11_SRCD) /* Reset DAT+CMD lines */
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#define EMMC_SD_SRS11_DTCV_SHIFT 16 /* 19:16: RW - Data Timeout Counter Value */
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#define EMMC_SD_SRS11_DTCV_MASK (0xFU << 16)
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#define EMMC_SD_SRS11_SDCFSL_SHIFT 8 /* 15:8: RW - SDCLK Freq Select (lower 8 bits) */
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#define EMMC_SD_SRS11_SDCFSL_MASK (0xFFU << 8)
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#define EMMC_SD_SRS11_SDCFSH_SHIFT 6 /* 7:6: RW - SDCLK Freq Select (upper 2 bits) */
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#define EMMC_SD_SRS11_SDCFSH_MASK (0x3U << 6)
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#define EMMC_SD_SRS11_CGS (1U << 5) /* 5: RW - Clock Generator Select */
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#define EMMC_SD_SRS11_SDCE (1U << 2) /* 2: RW - SD Clock Enable */
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#define EMMC_SD_SRS11_ICS (1U << 1) /* 1: RO - Internal Clock Stable */
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#define EMMC_SD_SRS11_ICE (1U << 0) /* 0: RW - Internal Clock Enable */
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/* SRS12 - Error/Normal Interrupt Status Register */
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#define EMMC_SD_SRS12 *((volatile uint32_t*)(EMMC_SD_BASE + 0x230))
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#define EMMC_SD_SRS12_ERSP (1U << 27) /* 27: RO - Response Error */
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#define EMMC_SD_SRS12_ETUNE (1U << 26) /* 26: RO - Tuning Error */
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#define EMMC_SD_SRS12_EADMA (1U << 25) /* 25: RO - ADMA Error */
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#define EMMC_SD_SRS12_EAC (1U << 24) /* 24: RO - Auto CMD Error */
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#define EMMC_SD_SRS12_ECL (1U << 23) /* 23: RO - Current Limit Error */
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#define EMMC_SD_SRS12_EDEB (1U << 22) /* 22: RO - Data End Bit Error */
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#define EMMC_SD_SRS12_EDCRC (1U << 21) /* 21: RO - Data CRC Error */
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#define EMMC_SD_SRS12_EDT (1U << 20) /* 20: RO - Data Timeout Error */
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#define EMMC_SD_SRS12_ECI (1U << 19) /* 19: RO - Command Index Error */
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#define EMMC_SD_SRS12_ECEB (1U << 18) /* 18: RO - Command End Bit Error */
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#define EMMC_SD_SRS12_ECCRC (1U << 17) /* 17: RO - Command CRC Error */
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#define EMMC_SD_SRS12_ECT (1U << 16) /* 16: RO - Command Timeout Error */
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#define EMMC_SD_SRS12_EINT (1U << 15) /* 15: RO - Error Interrupt */
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#define EMMC_SD_SRS12_CQI (1U << 14) /* 14: RO - Command Queuing Interrupt */
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#define EMMC_SD_SRS12_CINT (1U << 8) /* 8: RO - Card Interrupt */
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#define EMMC_SD_SRS12_CR (1U << 7) /* 7: RW - Card Removal */
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#define EMMC_SD_SRS12_CIN (1U << 6) /* 6: RW - Card Insertion */
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#define EMMC_SD_SRS12_BRR (1U << 5) /* 5: RO - Buffer Read Ready */
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#define EMMC_SD_SRS12_BWR (1U << 4) /* 4: RO - Buffer Write Ready */
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#define EMMC_SD_SRS12_DMAINT (1U << 3) /* 3: RW - DMA Interrupt */
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#define EMMC_SD_SRS12_BGE (1U << 2) /* 2: RW - Block Gap Event */
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#define EMMC_SD_SRS12_TC (1U << 1) /* 1: RW - Transfer Complete */
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#define EMMC_SD_SRS12_CC (1U << 0) /* 0: RW - Command Complete */
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/* Interrupt status masks */
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#define EMMC_SD_SRS12_NORM_STAT 0x00007FFFU /* Normal interrupt status mask */
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#define EMMC_SD_SRS12_ERR_STAT 0xFFFF8000U /* Error interrupt status mask */
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#define EMMC_SD_SRS12_CMD_ERR (EMMC_SD_SRS12_ECT | EMMC_SD_SRS12_ECCRC | \
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EMMC_SD_SRS12_ECEB | EMMC_SD_SRS12_ECI)
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#define EMMC_SD_SRS13 *((volatile uint32_t*)(EMMC_SD_BASE + 0x234)) /* Error/Normal Status Enable */
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#define EMMC_SD_SRS13_ERSP_SE (1U << 27) /* 27: RW - Response Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_ETUNE_SE (1U << 26) /* 26: RW - Tuning Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_EADMA_SE (1U << 25) /* 25: RW - ADMA Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_EAC_SE (1U << 24) /* 24: RW - Auto CMD Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_ECL_SE (1U << 23) /* 23: RW - Current Limit Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_EDEB_SE (1U << 22) /* 22: RW - Data End Bit Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_EDCRC_SE (1U << 21) /* 21: RW - Data CRC Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_EDT_SE (1U << 20) /* 20: RW - Data Timeout Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_ECI_SE (1U << 19) /* 19: RW - Command Index Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_ECEB_SE (1U << 18) /* 18: RW - Command End Bit Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_ECCRC_SE (1U << 17) /* 17: RW - Command CRC Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_ECT_SE (1U << 16) /* 16: RW - Command Timeout Error Status Enable (SD mode only) */
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#define EMMC_SD_SRS13_CQINT_SE (1U << 14) /* 14: RW - Command Queuing Status Enable */
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#define EMMC_SD_SRS13_RTUNE_SE (1U << 12) /* 12: RW - Retuning event status enable */
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#define EMMC_SD_SRS13_INT_ONC (1U << 11) /* 11: RW - Interrupt On Line C status enable */
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#define EMMC_SD_SRS13_INT_ONB (1U << 10) /* 10: RW - Interrupt On Line B status enable */
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#define EMMC_SD_SRS13_INT_ONA (1U << 9) /* 9: RW - Interrupt On Line A status enable */
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#define EMMC_SD_SRS13_CINT_SE (1U << 8) /* 8: RW - Card Interrupt Status Enable */
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#define EMMC_SD_SRS13_CR_SE (1U << 7) /* 7: RW - Card Removal Status Enable */
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#define EMMC_SD_SRS13_CIN_SE (1U << 6) /* 6: RW - Card Insertion Status Enable */
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#define EMMC_SD_SRS13_BRR_SE (1U << 5) /* 5: RW - Buffer Read Ready Status Enable */
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#define EMMC_SD_SRS13_BWR_SE (1U << 4) /* 4: RW - Buffer Write Ready Status Enable */
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#define EMMC_SD_SRS13_DMAINT_SE (1U << 3) /* 3: RW - DMA Interrupt Status Enable */
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#define EMMC_SD_SRS13_BGE_SE (1U << 2) /* 2: RW - Block Gap Event Status Enable */
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#define EMMC_SD_SRS13_TC_SE (1U << 1) /* 1: RW - Transfer Complete Status Enable */
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#define EMMC_SD_SRS13_CC_SE (1U << 0) /* 0: RW - Command Complete Status Enable */
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#define EMMC_SD_SRS14 *((volatile uint32_t*)(EMMC_SD_BASE + 0x238)) /* Error/Normal Signal Enable */
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#define EMMC_SD_SRS14_ERSP_IE (1U << 27) /* 27: RW - Response Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_EADMA_IE (1U << 25) /* 25: RW - ADMA Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_EAC_IE (1U << 24) /* 24: RW - Auto CMD Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_ECL_IE (1U << 23) /* 23: RW - Current Limit Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_EDEB_IE (1U << 22) /* 22: RW - Data End Bit Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_EDCRC_IE (1U << 21) /* 21: RW - Data CRC Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_EDT_IE (1U << 20) /* 20: RW - Data Timeout Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_ECI_IE (1U << 19) /* 19: RW - Command Index Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_ECEB_IE (1U << 18) /* 18: RW - Command End Bit Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_ECCRC_IE (1U << 17) /* 17: RW - Command CRC Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_ECT_IE (1U << 16) /* 16: RW - Command Timeout Error Interrupt Enable (SD mode only) */
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#define EMMC_SD_SRS14_CQINT_IE (1U << 14) /* 14: RW - Command Queuing Interrupt Enable */
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#define EMMC_SD_SRS14_CINT_IE (1U << 8) /* 8: RW - Card Interrupt Interrupt Enable */
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#define EMMC_SD_SRS14_CR_IE (1U << 7) /* 7: RW - Card Removal Interrupt Enable */
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#define EMMC_SD_SRS14_CIN_IE (1U << 6) /* 6: RW - Card Insertion Interrupt Enable */
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#define EMMC_SD_SRS14_BRR_IE (1U << 5) /* 5: RW - Buffer Read Ready Interrupt Enable */
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#define EMMC_SD_SRS14_BWR_IE (1U << 4) /* 4: RW - Buffer Write Ready Interrupt Enable */
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#define EMMC_SD_SRS14_DMAINT_IE (1U << 3) /* 3: RW - DMA Interrupt Interrupt Enable */
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#define EMMC_SD_SRS14_BGE_IE (1U << 2) /* 2: RW - Block Gap Event Interrupt Enable */
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#define EMMC_SD_SRS14_TC_IE (1U << 1) /* 1: RW - Transfer Complete Interrupt Enable */
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#define EMMC_SD_SRS14_CC_IE (1U << 0) /* 0: RW - Command Complete Interrupt Enable */
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/* SRS15 - Host Control #2 / Auto CMD Error Status Register */
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#define EMMC_SD_SRS15 *((volatile uint32_t*)(EMMC_SD_BASE + 0x23C))
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#define EMMC_SD_SRS15_PVE (1U << 31) /* 31: RW - Preset Value Enable */
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#define EMMC_SD_SRS15_AIE (1U << 30) /* 30: RW - Async Interrupt Enable */
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#define EMMC_SD_SRS15_A64 (1U << 29) /* 29: RW - 64-bit Addressing */
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#define EMMC_SD_SRS15_HV4E (1U << 28) /* 28: RW - Host Version 4 Enable */
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#define EMMC_SD_SRS15_UHSII (1U << 24) /* 24: RW - UHS-II Interface Enable */
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#define EMMC_SD_SRS15_SCS (1U << 23) /* 23: RW - Sampling Clock Select */
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#define EMMC_SD_SRS15_EXTNG (1U << 22) /* 22: RW - Execute Tuning */
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#define EMMC_SD_SRS15_DSS_SHIFT 20 /* 21:20: RW - Driver Strength Select */
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#define EMMC_SD_SRS15_DSS_MASK (0x3U << 20)
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#define EMMC_SD_SRS15_DSS_TYPE_B (0x0U << 20) /* Driver Type B (default) */
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#define EMMC_SD_SRS15_DSS_TYPE_A (0x1U << 20) /* Driver Type A */
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#define EMMC_SD_SRS15_DSS_TYPE_C (0x2U << 20) /* Driver Type C */
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#define EMMC_SD_SRS15_DSS_TYPE_D (0x3U << 20) /* Driver Type D */
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#define EMMC_SD_SRS15_V18SE (1U << 19) /* 19: RW - 1.8V Signaling Enable */
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#define EMMC_SD_SRS15_UMS_SHIFT 16 /* 18:16: RW - UHS Mode Select */
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#define EMMC_SD_SRS15_UMS_MASK (0x7U << 16)
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#define EMMC_SD_SRS15_UMS_SDR12 (0x0U << 16) /* SDR12 mode */
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#define EMMC_SD_SRS15_UMS_SDR25 (0x1U << 16) /* SDR25 mode (High Speed) */
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#define EMMC_SD_SRS15_UMS_SDR50 (0x2U << 16) /* SDR50 mode */
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#define EMMC_SD_SRS15_UMS_SDR104 (0x3U << 16) /* SDR104 mode */
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#define EMMC_SD_SRS15_UMS_DDR50 (0x4U << 16) /* DDR50 mode */
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#define EMMC_SD_SRS15_UMS_UHSII (0x7U << 16) /* UHS-II mode */
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/* Auto CMD Error Status bits (lower byte) */
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#define EMMC_SD_SRS15_CNIACE (1U << 7) /* 7: RO - CMD Not Issued by Auto CMD12 */
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#define EMMC_SD_SRS15_ACIE (1U << 4) /* 4: RO - Auto CMD12 Index Error */
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#define EMMC_SD_SRS15_ACEBE (1U << 3) /* 3: RO - Auto CMD12 End Bit Error */
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#define EMMC_SD_SRS15_ACCE (1U << 2) /* 2: RO - Auto CMD12 CRC Error */
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#define EMMC_SD_SRS15_ACTE (1U << 1) /* 1: RO - Auto CMD12 Timeout Error */
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#define EMMC_SD_SRS15_ACNE (1U << 0) /* 0: RO - Auto CMD12 Not Executed */
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/* SRS16 - Capabilities Register #1 */
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#define EMMC_SD_SRS16 *((volatile uint32_t*)(EMMC_SD_BASE + 0x240))
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#define EMMC_SD_SRS16_SLT_SHIFT 30 /* 31:30: RO - Slot Type */
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#define EMMC_SD_SRS16_SLT_MASK (0x3U << 30)
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#define EMMC_SD_SRS16_AIS (1U << 29) /* 29: RO - Async Interrupt Support */
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#define EMMC_SD_SRS16_A64S (1U << 28) /* 28: RO - 64-bit System Bus Support */
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#define EMMC_SD_SRS16_VS18 (1U << 26) /* 26: RO - Voltage Support 1.8V */
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#define EMMC_SD_SRS16_VS30 (1U << 25) /* 25: RO - Voltage Support 3.0V */
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#define EMMC_SD_SRS16_VS33 (1U << 24) /* 24: RO - Voltage Support 3.3V */
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#define EMMC_SD_SRS16_SRS (1U << 23) /* 23: RO - Suspend/Resume Support */
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#define EMMC_SD_SRS16_DMAS (1U << 22) /* 22: RO - SDMA Support */
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#define EMMC_SD_SRS16_HSS (1U << 21) /* 21: RO - High Speed Support */
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#define EMMC_SD_SRS16_ADMA1S (1U << 20) /* 20: RO - ADMA1 Support */
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#define EMMC_SD_SRS16_ADMA2S (1U << 19) /* 19: RO - ADMA2 Support */
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#define EMMC_SD_SRS16_EDS8 (1U << 18) /* 18: RO - 8-bit Data Support */
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#define EMMC_SD_SRS16_MBL_SHIFT 16 /* 17:16: RO - Max Block Length */
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#define EMMC_SD_SRS16_MBL_MASK (0x3U << 16)
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#define EMMC_SD_SRS16_MBL_512 (0x0U << 16) /* Max 512 bytes */
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#define EMMC_SD_SRS16_MBL_1024 (0x1U << 16) /* Max 1024 bytes */
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#define EMMC_SD_SRS16_MBL_2048 (0x2U << 16) /* Max 2048 bytes */
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#define EMMC_SD_SRS16_BCSDCLK_SHIFT 8 /* 15:8: RO - Base Clock for SD Clock (in MHz) */
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#define EMMC_SD_SRS16_BCSDCLK_MASK (0xFFU << 8)
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#define EMMC_SD_SRS16_TCU (1U << 7) /* 7: RO - Timeout Clock Unit (1=MHz) */
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#define EMMC_SD_SRS16_TCF_SHIFT 0 /* 5:0: RO - Timeout Clock Frequency */
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#define EMMC_SD_SRS16_TCF_MASK (0x3FU << 0)
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/* SRS17 - Capabilities Register #2 */
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#define EMMC_SD_SRS17 *((volatile uint32_t*)(EMMC_SD_BASE + 0x244))
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#define EMMC_SD_SRS17_VDD2S (1U << 28) /* 28: RO - VDD2 Support */
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#define EMMC_SD_SRS17_CLKMPR_SHIFT 16 /* 23:16: RO - Clock Multiplier */
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#define EMMC_SD_SRS17_CLKMPR_MASK (0xFFU << 16)
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#define EMMC_SD_SRS17_RTNGM_SHIFT 14 /* 15:14: RO - Re-Tuning Modes */
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#define EMMC_SD_SRS17_RTNGM_MASK (0x3U << 14)
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#define EMMC_SD_SRS17_RTNGM_MODE1 (0x0U << 14) /* Re-tuning mode 1 */
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#define EMMC_SD_SRS17_RTNGM_MODE2 (0x1U << 14) /* Re-tuning mode 2 */
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#define EMMC_SD_SRS17_RTNGM_MODE3 (0x2U << 14) /* Re-tuning mode 3 */
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#define EMMC_SD_SRS17_TSDR50 (1U << 13) /* 13: RO - Tuning for SDR50 */
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#define EMMC_SD_SRS17_TCRT_SHIFT 8 /* 11:8: RO - Timer Count for Re-Tuning */
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#define EMMC_SD_SRS17_TCRT_MASK (0xFU << 8)
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#define EMMC_SD_SRS17_UHSII (1U << 8) /* 8: RO - UHS-II Support */
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#define EMMC_SD_SRS17_DRVD (1U << 6) /* 6: RO - Driver Type D Support */
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#define EMMC_SD_SRS17_DRVC (1U << 5) /* 5: RO - Driver Type C Support */
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#define EMMC_SD_SRS17_DRVA (1U << 4) /* 4: RO - Driver Type A Support */
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#define EMMC_SD_SRS17_DDR50 (1U << 2) /* 2: RO - DDR50 Support */
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#define EMMC_SD_SRS17_SDR104 (1U << 1) /* 1: RO - SDR104 Support */
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#define EMMC_SD_SRS17_SDR50 (1U << 0) /* 0: RO - SDR50 Support */
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#define EMMC_SD_SRS18 *((volatile uint32_t*)(EMMC_SD_BASE + 0x248)) /* Capabilities #3 */
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#define EMMC_SD_SRS18_MC18_SHIFT 16 /* 23:16: RO - Maximym current for 1.8v */
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#define EMMC_SD_SRS18_MC18_MASK (0xFFU << 16)
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#define EMMC_SD_SRS18_MC30_SHIFT 8 /* 15:8: RO - Maximym current for 3.0v */
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#define EMMC_SD_SRS18_MC30_MASK (0xFFU << 8)
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#define EMMC_SD_SRS18_MC33_SHIFT 0 /* 7:0: RO - Maximym current for 3.3v */
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#define EMMC_SD_SRS18_MC33_MASK (0xFFU << 0)
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#define EMMC_SD_SRS19 *((volatile uint32_t*)(EMMC_SD_BASE + 0x24C)) /* Capabilities #4 */
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#define EMMC_SD_SRS19_MC18V2_SHIFT 0 /* 7:0: RO */
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#define EMMC_SD_SRS19_MC18V2_MASK (0xFFU << 0)
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#define EMMC_SD_SRS20 *((volatile uint32_t*)(EMMC_SD_BASE + 0x250)) /* Force Event */
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#define EMMC_SD_SRS20_ERESP_FE (1U << 27) /* 27: WO - Force Response Error */
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#define EMMC_SD_SRS20_ETUNE_FE (1U << 26) /* 26: WO - Force Tuning Error */
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#define EMMC_SD_SRS20_EADMA_FE (1U << 25) /* 25: WO - Force ADMA Error */
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#define EMMC_SD_SRS20_EAC_FE (1U << 24) /* 24: WO - Force Auto CMD Error */
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#define EMMC_SD_SRS20_ECL_FE (1U << 23) /* 23: WO - Force Current Limit Error */
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#define EMMC_SD_SRS20_EDEB_FE (1U << 22) /* 22: WO - Force Data End Bit Error */
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#define EMMC_SD_SRS20_EDCRC_FE (1U << 21) /* 21: WO - Force Data CRC Error */
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#define EMMC_SD_SRS20_EDT_FE (1U << 20) /* 20: WO - Force Data Timeout Error */
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#define EMMC_SD_SRS20_ECI_FE (1U << 19) /* 19: WO - Force Command Index Error */
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#define EMMC_SD_SRS20_ECEB_FE (1U << 18) /* 18: WO - Force Command End Bit Error */
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#define EMMC_SD_SRS20_ECCRC_FE (1U << 17) /* 17: WO - Force Command CRC Error */
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#define EMMC_SD_SRS20_ECT_FE (1U << 16) /* 16: WO - Force Command Timeout Error */
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#define EMMC_SD_SRS21 *((volatile uint32_t*)(EMMC_SD_BASE + 0x254)) /* ADMA Error Status */
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#define EMMC_SD_SRS21_EADMAL (1U << 2) /* 2: RO - ADMA Length Mismatch Error */
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#define EMMC_SD_SRS21_EADMAS_SHIFT 0 /* 1:0: RO */
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#define EMMC_SD_SRS21_EADMAS_MASK (0x3U << 0)
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#define EMMC_SD_SRS22 *((volatile uint32_t*)(EMMC_SD_BASE + 0x258)) /* ADMA System Address 1 */
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#define EMMC_SD_SRS22_DMASA1_SHIFT 0 /* 31:0: RW */
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#define EMMC_SD_SRS22_DMASA1_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_SRS23 *((volatile uint32_t*)(EMMC_SD_BASE + 0x25C)) /* ADMA System Address 2 */
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#define EMMC_SD_SRS23_DMASA2_SHIFT 0 /* 31:0: RW */
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#define EMMC_SD_SRS23_DMASA2_MASK (0xFFFFFFFFU << 0)
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#define EMMC_SD_SRS24 *((volatile uint32_t*)(EMMC_SD_BASE + 0x260)) /* Preset Value (Default Speed) */
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#define EMMC_SD_SRS25 *((volatile uint32_t*)(EMMC_SD_BASE + 0x264)) /* Preset Value (High Speed/SDR12) */
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#define EMMC_SD_SRS26 *((volatile uint32_t*)(EMMC_SD_BASE + 0x268)) /* Preset Value (SDR25/SDR50) */
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#define EMMC_SD_SRS27 *((volatile uint32_t*)(EMMC_SD_BASE + 0x26C)) /* Preset Value (SDR104/DDR50) */
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#define EMMC_SD_SRS29 *((volatile uint32_t*)(EMMC_SD_BASE + 0x274)) /* Preset Value for UHS-II */
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/* ----------------------------------------------------------------------------
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* CQRS - Command Queuing Register Set (eMMC 5.1 Command Queuing)
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* ---------------------------------------------------------------------------- */
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/* CQRS00 - Command Queuing Version Register */
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#define EMMC_SD_CQRS00 *((volatile uint32_t*)(EMMC_SD_BASE + 0x400))
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#define EMMC_SD_CQRS00_CQVN1_SHIFT 8 /* 11:8: RO - CQ Version (major) */
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#define EMMC_SD_CQRS00_CQVN1_MASK (0xFU << 8)
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#define EMMC_SD_CQRS00_CQVN2_SHIFT 4 /* 7:4: RO - CQ Version (minor) */
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#define EMMC_SD_CQRS00_CQVN2_MASK (0xFU << 4)
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#define EMMC_SD_CQRS00_CQVN3_SHIFT 0 /* 3:0: RO - CQ Version (suffix) */
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#define EMMC_SD_CQRS00_CQVN3_MASK (0xFU << 0)
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/* CQRS01 - Command Queuing Capabilities Register */
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#define EMMC_SD_CQRS01 *((volatile uint32_t*)(EMMC_SD_BASE + 0x404))
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#define EMMC_SD_CQRS01_ITCFMUL_SHIFT 12 /* 15:12: RO - Internal Timer Clock Freq Multiplier */
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#define EMMC_SD_CQRS01_ITCFMUL_MASK (0xFU << 12)
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#define EMMC_SD_CQRS01_ITCFVAL_SHIFT 0 /* 9:0: RO - Internal Timer Clock Freq Value */
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#define EMMC_SD_CQRS01_ITCFVAL_MASK (0x3FFU << 0)
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/* CQRS02 - Command Queuing Configuration Register */
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#define EMMC_SD_CQRS02 *((volatile uint32_t*)(EMMC_SD_BASE + 0x408))
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#define EMMC_SD_CQRS02_CQDCE (1U << 12) /* 12: RW - Direct Command (DCMD) Enable */
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#define EMMC_SD_CQRS02_CQTDS (1U << 8) /* 8: RW - Task Desc Size (0=64bit, 1=128bit) */
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#define EMMC_SD_CQRS02_CQTDS_64 (0x0U << 8) /* Task descriptor 64 bits */
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#define EMMC_SD_CQRS02_CQTDS_128 (0x1U << 8) /* Task descriptor 128 bits */
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#define EMMC_SD_CQRS02_CQE (1U << 0) /* 0: RW - Command Queuing Enable */
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/* CQRS03 - Command Queuing Control Register */
|
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#define EMMC_SD_CQRS03 *((volatile uint32_t*)(EMMC_SD_BASE + 0x40C))
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#define EMMC_SD_CQRS03_CQHLT (1U << 0) /* 0: RW - Halt CQ Engine */
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/* CQRS04 - Command Queuing Interrupt Status Register */
|
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#define EMMC_SD_CQRS04 *((volatile uint32_t*)(EMMC_SD_BASE + 0x410))
|
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#define EMMC_SD_CQRS04_CQTCL (1U << 3) /* 3: RW - Task Cleared Interrupt */
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#define EMMC_SD_CQRS04_CQRED (1U << 2) /* 2: RW - Response Error Detected */
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#define EMMC_SD_CQRS04_CQTCC (1U << 1) /* 1: RW - Task Complete Interrupt */
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#define EMMC_SD_CQRS04_CQHAC (1U << 0) /* 0: RW - Halt Complete Interrupt */
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/* CQRS05 - Command Queuing Interrupt Status Enable Register */
|
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#define EMMC_SD_CQRS05 *((volatile uint32_t*)(EMMC_SD_BASE + 0x414))
|
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#define EMMC_SD_CQRS05_CQTCLST (1U << 3) /* 3: RW - Task Cleared Status Enable */
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#define EMMC_SD_CQRS05_CQREDST (1U << 2) /* 2: RW - Response Error Status Enable */
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#define EMMC_SD_CQRS05_CQTCCST (1U << 1) /* 1: RW - Task Complete Status Enable */
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#define EMMC_SD_CQRS05_CQHACST (1U << 0) /* 0: RW - Halt Complete Status Enable */
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/* CQRS06 - Command Queuing Interrupt Signal Enable Register */
|
|
#define EMMC_SD_CQRS06 *((volatile uint32_t*)(EMMC_SD_BASE + 0x418))
|
|
#define EMMC_SD_CQRS06_CQTCLSI (1U << 3) /* 3: RW - Task Cleared Signal Enable */
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#define EMMC_SD_CQRS06_CQREDSI (1U << 2) /* 2: RW - Response Error Signal Enable */
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#define EMMC_SD_CQRS06_CQTCCSI (1U << 1) /* 1: RW - Task Complete Signal Enable */
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#define EMMC_SD_CQRS06_CQHACSI (1U << 0) /* 0: RW - Halt Complete Signal Enable */
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|
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/* CQRS07 - Interrupt Coalescing Register */
|
|
#define EMMC_SD_CQRS07 *((volatile uint32_t*)(EMMC_SD_BASE + 0x41C))
|
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#define EMMC_SD_CQRS07_CQICED (1U << 31) /* 31: RW - Int Coalescing Enable/Disable */
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#define EMMC_SD_CQRS07_CQICSB (1U << 20) /* 20: RO - Int Coalescing Status Bit */
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#define EMMC_SD_CQRS07_CQICCTR (1U << 16) /* 16: WO - Counter and Timer Reset */
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#define EMMC_SD_CQRS07_CQICCTHWEN (1U << 15) /* 15: WO - Counter Threshold Write Enable */
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#define EMMC_SD_CQRS07_CQICCTH_SHIFT 8 /* 12:8: RW - Int Coalescing Counter Threshold */
|
|
#define EMMC_SD_CQRS07_CQICCTH_MASK (0x1FU << 8)
|
|
#define EMMC_SD_CQRS07_CQICTOVALEN (1U << 7) /* 7: WO - Timeout Value Write Enable */
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#define EMMC_SD_CQRS07_CQICTOVAL_SHIFT 0 /* 6:0: RW - Int Coalescing Timeout Value */
|
|
#define EMMC_SD_CQRS07_CQICTOVAL_MASK (0x7FU << 0)
|
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|
|
#define EMMC_SD_CQRS08 *((volatile uint32_t*)(EMMC_SD_BASE + 0x420)) /* Task Descriptor List Base Address */
|
|
#define EMMC_SD_CQRS08_CQTDLBA_SHIFT 0 /* 31:0: RW */
|
|
#define EMMC_SD_CQRS08_CQTDLBA_MASK (0xFFFFFFFFU << 0)
|
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|
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#define EMMC_SD_CQRS09 *((volatile uint32_t*)(EMMC_SD_BASE + 0x424)) /* Task Descriptor List Base Address Upper */
|
|
#define EMMC_SD_CQRS09_CQTDLBAU_SHIFT 0 /* 31:0: RW */
|
|
#define EMMC_SD_CQRS09_CQTDLBAU_MASK (0xFFFFFFFFU << 0)
|
|
|
|
#define EMMC_SD_CQRS10 *((volatile uint32_t*)(EMMC_SD_BASE + 0x428)) /* Command Queuing Task Doorbell */
|
|
#define EMMC_SD_CQRS11 *((volatile uint32_t*)(EMMC_SD_BASE + 0x42C)) /* Task Complete Notification */
|
|
#define EMMC_SD_CQRS12 *((volatile uint32_t*)(EMMC_SD_BASE + 0x430)) /* Device Queue Status */
|
|
#define EMMC_SD_CQRS12_CQDQS_SHIFT 0 /* 31:0: RO */
|
|
#define EMMC_SD_CQRS12_CQDQS_MASK (0xFFFFFFFFU << 0)
|
|
|
|
#define EMMC_SD_CQRS13 *((volatile uint32_t*)(EMMC_SD_BASE + 0x434)) /* Device Pending Tasks */
|
|
#define EMMC_SD_CQRS14 *((volatile uint32_t*)(EMMC_SD_BASE + 0x438)) /* Task Clear */
|
|
|
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#define EMMC_SD_CQRS16 *((volatile uint32_t*)(EMMC_SD_BASE + 0x440)) /* Send Status Configuration 1 */
|
|
#define EMMC_SD_CQRS16_CQSSCBC_SHIFT 16 /* 19:16: RW */
|
|
#define EMMC_SD_CQRS16_CQSSCBC_MASK (0xFU << 16)
|
|
#define EMMC_SD_CQRS16_CQSSCIT_SHIFT 0 /* 15:0: RW */
|
|
#define EMMC_SD_CQRS16_CQSSCIT_MASK (0xFFFFU << 0)
|
|
|
|
#define EMMC_SD_CQRS17 *((volatile uint32_t*)(EMMC_SD_BASE + 0x444)) /* Send Status Configuration 2 */
|
|
#define EMMC_SD_CQRS17_CQSQSR_SHIFT 0 /* 15:0: RW */
|
|
#define EMMC_SD_CQRS17_CQSQSR_MASK (0xFFFFU << 0)
|
|
|
|
#define EMMC_SD_CQRS18 *((volatile uint32_t*)(EMMC_SD_BASE + 0x448)) /* Command Response for Direct-Command */
|
|
#define EMMC_SD_CQRS18_CQDCLR_SHIFT 0 /* 31:0: RO */
|
|
#define EMMC_SD_CQRS18_CQDCLR_MASK (0xFFFFFFFFU << 0)
|
|
|
|
#define EMMC_SD_CQRS20 *((volatile uint32_t*)(EMMC_SD_BASE + 0x450)) /* Response Mode Error Mask */
|
|
#define EMMC_SD_CQRS20_CQRMEM_SHIFT 0 /* 31:0: RW */
|
|
#define EMMC_SD_CQRS20_CQRMEM_MASK (0xFFFFFFFFU << 0)
|
|
|
|
#define EMMC_SD_CQRS21 *((volatile uint32_t*)(EMMC_SD_BASE + 0x454)) /* Task Error Information */
|
|
#define EMMC_SD_CQRS21_CQDTEFV (1U << 31) /* 31: RO */
|
|
#define EMMC_SD_CQRS21_CQDTETID_SHIFT 24 /* 28:24: RO */
|
|
#define EMMC_SD_CQRS21_CQDTETID_MASK (0x1FU << 24)
|
|
#define EMMC_SD_CQRS21_CQDTECI_SHIFT 16 /* 21:16: RO */
|
|
#define EMMC_SD_CQRS21_CQDTECI_MASK (0x3FU << 16)
|
|
#define EMMC_SD_CQRS21_CQRMEFV (1U << 15) /* 15: RO */
|
|
#define EMMC_SD_CQRS21_CQRMETID_SHIFT 8 /* 12:8: RO */
|
|
#define EMMC_SD_CQRS21_CQRMETID_MASK (0x1FU << 8)
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#define EMMC_SD_CQRS21_CQRMECI_SHIFT 0 /* 5:0: RO */
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#define EMMC_SD_CQRS21_CQRMECI_MASK (0x3FU << 0)
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#define EMMC_SD_CQRS22 *((volatile uint32_t*)(EMMC_SD_BASE + 0x458)) /* Command Response Index */
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#define EMMC_SD_CQRS22_CQLCRI_SHIFT 0 /* 5:0: RO */
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#define EMMC_SD_CQRS22_CQLCRI_MASK (0x3FU << 0)
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#define EMMC_SD_CQRS23 *((volatile uint32_t*)(EMMC_SD_BASE + 0x45C)) /* Command Response Argument */
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#define EMMC_SD_CQRS23_CQLCRA_SHIFT 0 /* 31:0: RO */
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#define EMMC_SD_CQRS23_CQLCRA_MASK (0xFFFFFFFFU << 0)
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/* ----------------------------------------------------------------------------
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* EMMC/SD - Common Constants and Helper Macros
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* ---------------------------------------------------------------------------- */
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/* Clock Frequencies (in KHz) */
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#define EMMC_SD_CLK_400KHZ 400U /* Initial identification clock */
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#define EMMC_SD_CLK_25MHZ 25000U /* Default Speed / SDR12 */
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#define EMMC_SD_CLK_50MHZ 50000U /* High Speed / SDR25 */
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#define EMMC_SD_CLK_100MHZ 100000U /* SDR50 */
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#define EMMC_SD_CLK_200MHZ 200000U /* SDR104 / HS200 / HS400 */
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/* Block Size */
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#define EMMC_SD_BLOCK_SIZE 512U /* Standard block size */
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/* SD Interface Conditions */
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#define IF_COND_27V_33V (1U << 8)
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/* SD OCR register bits definitions */
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#define SDCARD_REG_OCR_2_7_2_8 (1U << 15)
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#define SDCARD_REG_OCR_2_8_2_9 (1U << 16)
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#define SDCARD_REG_OCR_2_9_3_0 (1U << 17)
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#define SDCARD_REG_OCR_3_0_3_1 (1U << 18)
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#define SDCARD_REG_OCR_3_1_3_2 (1U << 19)
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#define SDCARD_REG_OCR_3_2_3_3 (1U << 20)
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#define SDCARD_REG_OCR_3_3_3_4 (1U << 21)
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#define SDCARD_REG_OCR_3_4_3_5 (1U << 22)
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#define SDCARD_REG_OCR_3_5_3_6 (1U << 23)
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#define SDCARD_REG_OCR_S18RA (1U << 24) /* Switching to 1.8V request/accept bit */
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#define SDCARD_REG_OCR_XPC (1U << 28) /* eXtended Power Control (XPC) bit */
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#define SDCARD_REG_OCR_CCS (1U << 30) /* Card Capacity Status bit */
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#define SDCARD_REG_OCR_READY (1U << 31) /* OCR ready bit */
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#define SDCARD_ACMD41_HCS (1U << 30) /* High Capacity Support bit */
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/* Common MMC/SD Commands (for use with SRS03) */
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#define MMC_CMD0_GO_IDLE 0 /* Reset card to idle state */
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#define MMC_CMD1_SEND_OP_COND 1 /* MMC: Send operating conditions */
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#define MMC_CMD2_ALL_SEND_CID 2 /* Get card identification */
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#define MMC_CMD3_SET_REL_ADDR 3 /* Set relative address */
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#define MMC_CMD_4_SET_DSR 4
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#define SD_CMD_6_SWITCH_FUNC 6 /* SD: Switch function */
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#define MMC_CMD7_SELECT_CARD 7 /* Select/deselect card */
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#define MMC_CMD8_SEND_EXT_CSD 8 /* MMC: Get EXT_CSD */
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#define SD_CMD8_SEND_IF_COND 8 /* SD: Send interface condition */
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#define MMC_CMD9_SEND_CSD 9 /* Get card-specific data */
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#define SD_CMD11_VOLAGE_SWITCH 11 /* R1 Rsp */
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#define MMC_CMD12_STOP_TRANS 12 /* Stop transmission */
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#define MMC_CMD13_SEND_STATUS 13 /* Get card status */
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#define MMC_CMD_15_GOTO_INACT_ST 15
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#define SD_CMD_16 16 /* R1 Rsp */
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#define MMC_CMD17_READ_SINGLE 17 /* Read single block */
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#define MMC_CMD18_READ_MULTIPLE 18 /* Read multiple blocks */
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#define MMC_CMD24_WRITE_SINGLE 24 /* Write single block */
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#define MMC_CMD25_WRITE_MULTIPLE 25 /* Write multiple blocks */
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#define SD_CMD55_APP_CMD 55 /* Prefix for ACMD */
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#define SD_ACMD6_SET_BUS_WIDTH 6 /* SD: Set bus width */
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#define SD_ACMD41_SEND_OP_COND 41 /* SD: Send operating conditions */
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#define SD_ACMD51_SEND_SCR 51 /* SD: Get SCR register */
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/* Debouncing time for card detect */
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#define EMMC_SD_DEBOUNCE_TIME 0x300000U
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/* Timeout values */
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#define EMMC_SD_DATA_TIMEOUT_US 500000U /* 500ms data timeout */
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#define EMMC_SD_CMD_TIMEOUT_MS 3000U /* 3s command timeout */
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#define WOLFBOOT_CARDTYPE_SD 1
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#define WOLFBOOT_CARDTYPE_EMMC 2
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#define WOLFBOOT_CARDTYPE WOLFBOOT_CARDTYPE_SD
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#define MAX_CURRENT_MA 150 /* mA */
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#define SD_RCA_SHIFT 16 /* relative card address */
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#define SD_RCA_MASK (0xFFFFU << SD_RCA_SHIFT) /* relative card address mask */
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#define SCR_REG_DATA_SIZE 8
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/* Switch Function Command Arguments */
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#define SDCARD_SWITCH_FUNC_MODE_SWITCH (0x1u << 31) /* Set function mode */
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#define SDCARD_SWITCH_FUNC_MODE_CHECK (0x0u << 31) /* Check mode */
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/* group 1 - function 1 */
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#define SDCARD_SWITCH_ACCESS_MODE_SDR12 0x0U /* Card access mode - SDR12 default */
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#define SDCARD_SWITCH_ACCESS_MODE_SDR25 0x1U /* Card access mode - SDR25 high speed */
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#define SDCARD_SWITCH_ACCESS_MODE_SDR50 0x2U /* Card access mode - SDR50 */
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#define SDCARD_SWITCH_ACCESS_MODE_SDR104 0x3U /* Card access mode - SDR104 */
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#define SDCARD_SWITCH_ACCESS_MODE_DDR50 0x4U /* Card access mode - DDR50 */
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#define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_B 0x0U /* Card driver strength - Type B default */
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#define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_A 0x1U /* Card driver strength - Type A */
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#define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_C 0x2U /* Card driver strength - Type C */
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#define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_D 0x3U /* Card driver strength - Type D */
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/* Crypto Engine: Athena F5200 TeraFire Crypto Processor (1x), 200 MHz */
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#define ATHENA_BASE (SYSREG_BASE + 0x125000)
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#endif /* MPFS250_DEF_INCLUDED */
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