mirror of https://github.com/wolfSSL/wolfBoot.git
364 lines
17 KiB
C
364 lines
17 KiB
C
/* zynq.h
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef _ZYNQMP_H_
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#define _ZYNQMP_H_
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/* By default expect EL2 at startup */
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#ifndef EL3_SECURE
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#define EL3_SECURE 0
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#endif
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#ifndef EL2_HYPERVISOR
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#define EL2_HYPERVISOR 1
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#endif
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#ifndef EL1_NONSECURE
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#define EL1_NONSECURE 0
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#endif
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#ifndef HYP_GUEST
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/* ZEN Hypervisor guest format support */
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#define HYP_GUEST 0
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#endif
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/* Floating Point Trap Enable */
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#ifndef FPU_TRAP
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#define FPU_TRAP 0
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#endif
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/* Errata: 855873: An eviction might overtake a cache clean operation */
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#define CONFIG_ARM_ERRATA_855873 1
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#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
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#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
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#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
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#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
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/* Clocking */
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#define CORTEXA53_0_CPU_CLK_FREQ_HZ 1199880127
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#define CORTEXA53_0_TIMESTAMP_CLK_FREQ 99990005
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#define UART_MASTER_CLOCK 99990005
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#define GQSPI_CLK_FREQ_HZ 124987511
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/* IOP System-level Control */
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#define IOU_SLCR_BASSE 0xFF180000
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#define IOU_TAPDLY_BYPASS (*((volatile uint32_t*)(IOU_SLCR_BASSE + 0x390)))
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#define IOU_TAPDLY_BYPASS_LQSPI_RX (1UL << 2) /* LQSPI Tap Delay Enable on Rx Clock signal. 0: enable. 1: disable (bypass tap delay). */
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/* QSPI bare-metal driver */
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/* Generic Quad-SPI */
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#define QSPI_BASE 0xFF0F0000UL
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#define LQSPI_EN (*((volatile uint32_t*)(QSPI_BASE + 0x14))) /* SPI enable: 0: disable the SPI, 1: enable the SPI */
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#define GQSPI_CFG (*((volatile uint32_t*)(QSPI_BASE + 0x100))) /* configuration register. */
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#define GQSPI_ISR (*((volatile uint32_t*)(QSPI_BASE + 0x104))) /* interrupt status register. */
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#define GQSPI_IER (*((volatile uint32_t*)(QSPI_BASE + 0x108))) /* interrupt enable register. */
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#define GQSPI_IDR (*((volatile uint32_t*)(QSPI_BASE + 0x10C))) /* interrupt disable register. */
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#define GQSPI_IMR (*((volatile uint32_t*)(QSPI_BASE + 0x110))) /* interrupt unmask register. */
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#define GQSPI_EN (*((volatile uint32_t*)(QSPI_BASE + 0x114))) /* enable register. */
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#define GQSPI_TXD (*((volatile uint32_t*)(QSPI_BASE + 0x11C))) /* TX data register. Keyhole addresses for the transmit data FIFO. */
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#define GQSPI_RXD (*((volatile uint32_t*)(QSPI_BASE + 0x120))) /* RX data register. */
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#define GQSPI_TX_THRESH (*((volatile uint32_t*)(QSPI_BASE + 0x128))) /* TXFIFO Threshold Level register: (bits 5:0) Defines the level at which the TX_FIFO_NOT_FULL interrupt is generated */
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#define GQSPI_RX_THRESH (*((volatile uint32_t*)(QSPI_BASE + 0x12C))) /* RXFIFO threshold level register: (bits 5:0) Defines the level at which the RX_FIFO_NOT_EMPTY interrupt is generated */
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#define GQSPI_GPIO (*((volatile uint32_t*)(QSPI_BASE + 0x130)))
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#define GQSPI_LPBK_DLY_ADJ (*((volatile uint32_t*)(QSPI_BASE + 0x138))) /* adjusting the internal loopback clock delay for read data capturing */
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#define GQSPI_GEN_FIFO (*((volatile uint32_t*)(QSPI_BASE + 0x140))) /* generic FIFO data register. Keyhole addresses for the generic FIFO. */
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#define GQSPI_SEL (*((volatile uint32_t*)(QSPI_BASE + 0x144))) /* select register. */
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#define GQSPI_FIFO_CTRL (*((volatile uint32_t*)(QSPI_BASE + 0x14C))) /* FIFO control register. */
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#define GQSPI_GF_THRESH (*((volatile uint32_t*)(QSPI_BASE + 0x150))) /* generic FIFO threshold level register: (bits 4:0) Defines the level at which the GEN_FIFO_NOT_FULL interrupt is generated */
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#define GQSPI_POLL_CFG (*((volatile uint32_t*)(QSPI_BASE + 0x154))) /* poll configuration register */
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#define GQSPI_P_TIMEOUT (*((volatile uint32_t*)(QSPI_BASE + 0x158))) /* poll timeout register. */
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#define GQSPI_XFER_STS (*((volatile uint32_t*)(QSPI_BASE + 0x15C))) /* transfer status register. */
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#define QSPI_DATA_DLY_ADJ (*((volatile uint32_t*)(QSPI_BASE + 0x1F8))) /* adjusting the internal receive data delay for read data capturing */
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#define GQSPI_MOD_ID (*((volatile uint32_t*)(QSPI_BASE + 0x1FC)))
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#define QSPIDMA_DST_STS (*((volatile uint32_t*)(QSPI_BASE + 0x808)))
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#define QSPIDMA_DST_CTRL (*((volatile uint32_t*)(QSPI_BASE + 0x80C)))
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#define QSPIDMA_DST_I_STS (*((volatile uint32_t*)(QSPI_BASE + 0x814)))
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#define QSPIDMA_DST_CTRL2 (*((volatile uint32_t*)(QSPI_BASE + 0x824)))
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#define GQSPI_LPBK_DLY_ADJ_USE_LPBK (1UL << 5)
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#define GQSPI_LPBK_DLY_ADJ_DIV0(x) (((x) & 0x7) << 0)
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#define GQSPI_LPBK_DLY_ADJ_DLY1(x) (((x) & 0x3) << 3)
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#define QSPI_DATA_DLY_ADJ_USE_DATA_DLY (1UL << 31)
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#define QSPI_DATA_DLY_ADJ_DATA_DLY_ADJ(x) (((x) & 0x7) << 28)
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/* GQSPI Registers */
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/* GQSPI_CFG: Configuration registers */
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#define GQSPI_CFG_CLK_POL (1UL << 1) /* Clock polarity outside QSPI word: 0: QSPI clock is quiescent low, 1: QSPI clock is quiescent high */
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#define GQSPI_CFG_CLK_PH (1UL << 2) /* Clock phase: 1: the QSPI clock is inactive outside the word, 0: the QSPI clock is active outside the word */
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/* 000: divide by 2, 001: divide by 4, 010: divide by 8,
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011: divide by 16, 100: divide by 32, 101: divide by 64,
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110: divide by 128, 111: divide by 256 */
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#define GQSPI_CFG_BAUD_RATE_DIV_MASK (7UL << 3)
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#define GQSPI_CFG_BAUD_RATE_DIV(d) ((d << 3) & GQSPI_CFG_BAUD_RATE_DIV_MASK)
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#define GQSPI_CFG_WP_HOLD (1UL << 19) /* If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes. */
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#define GQSPI_CFG_EN_POLL_TIMEOUT (1UL << 20) /* Poll Timeout Enable: 0: disable, 1: enable */
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#define GQSPI_CFG_ENDIAN (1UL << 26) /* Endian format transmit data register: 0: little endian, 1: big endian */
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#define GQSPI_CFG_START_GEN_FIFO (1UL << 28) /* Trigger Generic FIFO Command Execution: 0:disable executing requests, 1: enable executing requests */
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#define GQSPI_CFG_GEN_FIFO_START_MODE (1UL << 29) /* Start mode of Generic FIFO: 0: Auto Start Mode, 1: Manual Start Mode */
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#define GQSPI_CFG_MODE_EN_MASK (3UL << 30) /* Flash memory interface mode control: 00: IO mode, 10: DMA mode */
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#define GQSPI_CFG_MODE_EN(m) ((m << 30) & GQSPI_CFG_MODE_EN_MASK)
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#define GQSPI_CFG_MODE_EN_IO GQSPI_CFG_MODE_EN(0)
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#define GQSPI_CFG_MODE_EN_DMA GQSPI_CFG_MODE_EN(2)
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/* GQSPI_ISR / GQSPI_IER / GQSPI_IDR / GQSPI_IMR: Interrupt registers */
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#define GQSPI_IXR_RX_FIFO_EMPTY (1UL << 11)
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#define GQSPI_IXR_GEN_FIFO_FULL (1UL << 10)
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#define GQSPI_IXR_GEN_FIFO_NOT_FULL (1UL << 9)
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#define GQSPI_IXR_TX_FIFO_EMPTY (1UL << 8)
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#define GQSPI_IXR_GEN_FIFO_EMPTY (1UL << 7)
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#define GQSPI_IXR_RX_FIFO_FULL (1UL << 5)
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#define GQSPI_IXR_RX_FIFO_NOT_EMPTY (1UL << 4)
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#define GQSPI_IXR_TX_FIFO_FULL (1UL << 3)
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#define GQSPI_IXR_TX_FIFO_NOT_FULL (1UL << 2)
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#define GQSPI_IXR_POLL_TIME_EXPIRE (1UL << 1)
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#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_POLL_TIME_EXPIRE | GQSPI_IXR_TX_FIFO_NOT_FULL | \
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GQSPI_IXR_TX_FIFO_FULL | GQSPI_IXR_RX_FIFO_NOT_EMPTY | GQSPI_IXR_RX_FIFO_FULL | \
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GQSPI_IXR_GEN_FIFO_EMPTY | GQSPI_IXR_TX_FIFO_EMPTY | GQSPI_IXR_GEN_FIFO_NOT_FULL | \
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GQSPI_IXR_GEN_FIFO_FULL | GQSPI_IXR_RX_FIFO_EMPTY)
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#define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002U
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/* GQSPI_GEN_FIFO: FIFO data register */
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/* bits 0-7: Length in bytes (except when GQSPI_GEN_FIFO_EXP_MASK is set length as 255 chunks) */
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#define GQSPI_GEN_FIFO_IMM_MASK (0xFFUL) /* Immediate Data Field */
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#define GQSPI_GEN_FIFO_IMM(imm) (imm & GQSPI_GEN_FIFO_IMM_MASK)
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#define GQSPI_GEN_FIFO_DATA_XFER (1UL << 8) /* Indicates IMM is size, otherwise byte is sent directly in IMM reg */
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#define GQSPI_GEN_FIFO_EXP_MASK (1UL << 9) /* Length is Exponent (length / 255) */
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#define GQSPI_GEN_FIFO_MODE_MASK (3UL << 10)
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#define GQSPI_GEN_FIFO_MODE(m) ((m << 10) & GQSPI_GEN_FIFO_MODE_MASK)
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#define GQSPI_GEN_FIFO_MODE_SPI GQSPI_GEN_FIFO_MODE(1)
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#define GQSPI_GEN_FIFO_MODE_DSPI GQSPI_GEN_FIFO_MODE(2)
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#define GQSPI_GEN_FIFO_MODE_QSPI GQSPI_GEN_FIFO_MODE(3)
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#define GQSPI_GEN_FIFO_CS_MASK (3UL << 12)
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#define GQSPI_GEN_FIFO_CS(c) ((c << 12) & GQSPI_GEN_FIFO_CS_MASK)
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#define GQSPI_GEN_FIFO_CS_LOWER GQSPI_GEN_FIFO_CS(1)
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#define GQSPI_GEN_FIFO_CS_UPPER GQSPI_GEN_FIFO_CS(2)
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#define GQSPI_GEN_FIFO_CS_BOTH GQSPI_GEN_FIFO_CS(3)
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#define GQSPI_GEN_FIFO_BUS_MASK (3UL << 14)
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#define GQSPI_GEN_FIFO_BUS(b) ((b << 14) & GQSPI_GEN_FIFO_BUS_MASK)
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#define GQSPI_GEN_FIFO_BUS_LOW GQSPI_GEN_FIFO_BUS(1)
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#define GQSPI_GEN_FIFO_BUS_UP GQSPI_GEN_FIFO_BUS(2)
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#define GQSPI_GEN_FIFO_BUS_BOTH GQSPI_GEN_FIFO_BUS(3)
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#define GQSPI_GEN_FIFO_TX (1UL << 16)
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#define GQSPI_GEN_FIFO_RX (1UL << 17)
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#define GQSPI_GEN_FIFO_STRIPE (1UL << 18) /* Stripe data across the lower and upper data buses. */
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#define GQSPI_GEN_FIFO_POLL (1UL << 19)
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/* GQSPI_FIFO_CTRL */
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#define GQSPI_FIFO_CTRL_RST_GEN_FIFO (1UL << 0)
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#define GQSPI_FIFO_CTRL_RST_TX_FIFO (1UL << 1)
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#define GQSPI_FIFO_CTRL_RST_RX_FIFO (1UL << 2)
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/* QSPIDMA_DST_CTRL */
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#define QSPIDMA_DST_CTRL_DEF 0x403FFA00UL
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#define QSPIDMA_DST_CTRL2_DEF 0x081BFFF8UL
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/* QSPIDMA_DST_STS */
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#define QSPIDMA_DST_STS_WTC 0xE000U
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/* QSPIDMA_DST_I_STS */
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#define QSPIDMA_DST_I_STS_ALL_MASK 0xFEU
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/* QSPI Configuration (bare-metal only) */
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#ifndef GQSPI_CLK_DIV
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#define GQSPI_CLK_DIV 2 /* (CLK (300MHz) / (2 << DIV) = BUS): 0=DIV2, 1=DIV4, 2=DIV8 */
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#endif
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#define GQSPI_CS_ASSERT_CLOCKS 5 /* CS Setup Time (tCSS) - num of clock cycles foes in IMM */
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#define GQSPI_FIFO_WORD_SZ 4
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#define GQSPI_TIMEOUT_TRIES 100000
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#define QSPI_FLASH_READY_TRIES 1000
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/* QSPI Configuration */
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#ifndef GQSPI_QSPI_MODE
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#define GQSPI_QSPI_MODE GQSPI_GEN_FIFO_MODE_QSPI
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#endif
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#ifndef GQPI_USE_DUAL_PARALLEL
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#define GQPI_USE_DUAL_PARALLEL 1 /* 0=no stripe, 1=stripe */
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#endif
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#ifndef GQPI_USE_4BYTE_ADDR
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#define GQPI_USE_4BYTE_ADDR 1
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#endif
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#ifndef GQSPI_DUMMY_READ
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#define GQSPI_DUMMY_READ (8*8) /* Number of dummy clock cycles for reads */
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#endif
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/* Flash Parameters:
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* Micron Serial NOR Flash Memory 64KB Sector Erase MT25QU512ABB
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* Stacked device (two 512Mb (64MB))
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* Dual Parallel so total addressable size is double
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*/
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#ifndef FLASH_DEVICE_SIZE
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#ifdef ZCU102
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/* 64*2 (dual parallel) = 128MB */
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#define FLASH_DEVICE_SIZE (2 * 64 * 1024 * 1024) /* MT25QU512ABB */
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#else
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/* 128*2 (dual parallel) = 256MB */
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#define FLASH_DEVICE_SIZE (2 * 128 * 1024 * 1024) /* MT25QU01GBBB */
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#endif
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#endif
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#ifndef FLASH_PAGE_SIZE
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#ifdef ZCU102
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/* MT25QU512ABB - Read FlashID: 20 BB 20 */
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#define FLASH_PAGE_SIZE 256
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#else
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/* MT25QU01GBBB - Read FlashID: 20 BB 21 */
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#define FLASH_PAGE_SIZE 512
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#endif
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#endif
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#define FLASH_NUM_SECTORS (FLASH_DEVICE_SIZE/WOLFBOOT_SECTOR_SIZE)
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/* Flash Commands */
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#define WRITE_ENABLE_CMD 0x06U
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#define READ_SR_CMD 0x05U
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#define WRITE_DISABLE_CMD 0x04U
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#define READ_ID_CMD 0x9FU
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#define MULTI_IO_READ_ID_CMD 0xAFU
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#define READ_FSR_CMD 0x70U
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#define ENTER_QSPI_MODE_CMD 0x35U
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#define EXIT_QSPI_MODE_CMD 0xF5U
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#define ENTER_4B_ADDR_MODE_CMD 0xB7U
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#define EXIT_4B_ADDR_MODE_CMD 0xE9U
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#define FAST_READ_CMD 0x0BU
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#define DUAL_READ_CMD 0x3BU
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#define QUAD_READ_CMD 0x6BU
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#define FAST_READ_4B_CMD 0x0CU
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#define DUAL_READ_4B_CMD 0x3CU
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#define QUAD_READ_4B_CMD 0x6CU
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#define PAGE_PROG_CMD 0x02U
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#define DUAL_PROG_CMD 0xA2U
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#define QUAD_PROG_CMD 0x22U
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#define PAGE_PROG_4B_CMD 0x12U
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#define DUAL_PROG_4B_CMD 0x12U
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#define QUAD_PROG_4B_CMD 0x34U
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#define SEC_ERASE_CMD 0xD8U
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#define SEC_4K_ERASE_CMD 0x20U
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#define RESET_ENABLE_CMD 0x66U
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#define RESET_MEMORY_CMD 0x99U
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#define WRITE_EN_MASK 0x02 /* 0=Write Enabled, 1=Disabled Write */
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#define FLASH_READY_MASK 0x80 /* 0=Busy, 1=Ready */
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/* Return Codes */
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#define GQSPI_CODE_SUCCESS 0
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#define GQSPI_CODE_FAILED -100
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#define GQSPI_CODE_TIMEOUT -101
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/* eFUSE support */
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#define ZYNQMP_EFUSE_BASE 0xFFCC0000
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#define ZYNQMP_EFUSE_STATUS (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x0008)))
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#define ZYNQMP_EFUSE_SEC_CTRL (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x1058)))
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#define ZYNQMP_EFUSE_PPK0_0 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10A0)))
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#define ZYNQMP_EFUSE_PPK0_1 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10A4)))
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#define ZYNQMP_EFUSE_PPK0_2 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10A8)))
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#define ZYNQMP_EFUSE_PPK0_3 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10AC)))
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#define ZYNQMP_EFUSE_PPK0_4 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10B0)))
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#define ZYNQMP_EFUSE_PPK0_5 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10B4)))
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#define ZYNQMP_EFUSE_PPK0_6 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10B8)))
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#define ZYNQMP_EFUSE_PPK0_7 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10BC)))
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#define ZYNQMP_EFUSE_PPK0_8 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10C0)))
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#define ZYNQMP_EFUSE_PPK0_9 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10C4)))
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#define ZYNQMP_EFUSE_PPK0_10 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10C8)))
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#define ZYNQMP_EFUSE_PPK0_11 (*((volatile uint32_t*)(ZYNQMP_EFUSE_BASE + 0x10CC)))
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/* eFUSE STATUS Registers */
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#define ZYNQMP_EFUSE_STATUS_CACHE_DONE (1UL << 5)
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#define ZYNQMP_EFUSE_STATUS_CACHE_LOAD (1UL << 4)
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/* eFUSE SEC_CTRL Registers */
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#define ZYNQMP_EFUSE_SEC_CTRL_PPK1_INVLD (3UL << 30) /* Revokes PPK1 */
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#define ZYNQMP_EFUSE_SEC_CTRL_PPK1_WRLK (1UL << 29) /* Locks writing to PPK1 eFuses */
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#define ZYNQMP_EFUSE_SEC_CTRL_PPK0_INVLD (3UL << 27) /* Revokes PPK0 */
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#define ZYNQMP_EFUSE_SEC_CTRL_PPK0_WRLK (1UL << 26) /* Locks writing to PPK0 eFuses */
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#define ZYNQMP_EFUSE_SEC_CTRL_RSA_EN (15UL << 11) /* Enables RSA Authentication during boot. All boots must be authenticated */
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#define ZYNQMP_EFUSE_SEC_CTRL_SEC_LOCK (1UL << 10) /* Disables the reboot into JTAG mode when doing a secure lockdown. */
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#define ZYNQMP_EFUSE_SEC_CTRL_JTAG_DIS (1UL << 5) /* Disables the JTAG controller. The only instructions available are BYPASS and IDCODE. */
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#define ZYNQMP_EFUSE_SEC_CTRL_ENC_ONLY (1UL << 2) /* Requires all boots to be encrypted using the eFuse key. */
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#define ZYNQMP_EFUSE_SEC_CTRL_AES_WRLK (1UL << 1) /* Locks writing to the AES key section of eFuse */
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#define ZYNQMP_EFUSE_SEC_CTRL_AES_RDLK (1UL << 0) /* Locks the AES key CRC check function */
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/* UART Support */
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#define ZYNQMP_UART0_BASE 0xFF000000
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#define ZYNQMP_UART1_BASE 0xFF010000
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#define ZYNQMP_UART_CR (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x00)))
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#define ZYNQMP_UART_MR (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x04)))
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#define ZYNQMP_UART_IDR (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x0C))) /* Interrupt Disable Register */
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#define ZYNQMP_UART_ISR (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x14))) /* Interrupt Status Register */
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#define ZYNQMP_UART_RXTOUT (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x1C)))
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#define ZYNQMP_UART_RXWM (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x20)))
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#define ZYNQMP_UART_TXWM (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x44)))
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#define ZYNQMP_UART_SR (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x2C)))
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#define ZYNQMP_UART_FIFO (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x30)))
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#define ZYNQMP_UART_BR_GEN (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x18))) /* 2 - 65535: baud_sample */
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#define ZYNQMP_UART_BR_DIV (*((volatile uint32_t*)(DEBUG_UART_BASE + 0x34))) /* 4 - 255: Baud rate */
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/* UART Control Registers */
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#define ZYNQMP_UART_CR_TX_DIS 0x00000020 /* TX disable */
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#define ZYNQMP_UART_CR_TX_EN 0x00000010 /* TX enabled */
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#define ZYNQMP_UART_CR_RX_DIS 0x00000008 /* RX disable */
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#define ZYNQMP_UART_CR_RX_EN 0x00000004 /* RX enabled */
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#define ZYNQMP_UART_CR_TXRST 0x00000002 /* TX logic reset */
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#define ZYNQMP_UART_CR_RXRST 0x00000001 /* RX logic reset */
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/* UART ISR Mask 0-13 bits */
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#define ZYNQMP_UART_ISR_MASK 0x3FFF
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/* UART Mode Registers */
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#define ZYNQMP_UART_MR_PARITY_NONE 0x00000020 /* No parity */
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/* UART Channel Status Register (read only) */
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#define ZYNQMP_UART_SR_TXFULL 0x00000010U /* TX FIFO full */
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#define ZYNQMP_UART_SR_TXEMPTY 0x00000008U /* TX FIFO empty */
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#define ZYNQMP_UART_SR_RXFULL 0x00000004U /* RX FIFO full */
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#define ZYNQMP_UART_SR_RXEMPTY 0x00000002U /* RX FIFO empty */
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/* UART Configuration */
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#if defined(DEBUG_UART_NUM) && DEBUG_UART_NUM == 0
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#define DEBUG_UART_BASE ZYNQMP_UART0_BASE
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#elif defined(DEBUG_UART_NUM) && DEBUG_UART_NUM == 1
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#define DEBUG_UART_BASE ZYNQMP_UART1_BASE
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#endif
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#ifndef DEBUG_UART_BASE
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/* default to UART0 */
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#define DEBUG_UART_BASE ZYNQMP_UART0_BASE
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#endif
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#ifndef DEBUG_UART_BAUD
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#define DEBUG_UART_BAUD 115200
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#define DEBUG_UART_DIV 6
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#endif
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#define GICD_BASE 0xF9010000
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#define GICC_BASE 0xF9020000
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#endif /* _ZYNQMP_H_ */
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