mirror of https://github.com/wolfSSL/wolfBoot.git
262 lines
7.2 KiB
C
262 lines
7.2 KiB
C
/* uart_drv_stm32l5.c
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*
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* Driver for the back-end of the UART_FLASH module.
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*
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* Example implementation for stm32L5 Nucleo
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* using LPUART1 (VCS port through USB).
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*
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "hal/stm32h5.h"
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/* USE_UART1
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* Set to 0 for VCP over USB
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* Set to 1 for Arduino D0, D1 pins on nucleo
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* */
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#define USE_UART1 0
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#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
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#define GPIOB_AHB2ENR1_CLOCK_ER (1 << 1)
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#define GPIOD_AHB2ENR1_CLOCK_ER (1 << 3)
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#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
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#define GPIOB_OTYPE (*(volatile uint32_t *)(GPIOB_BASE + 0x04))
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#define GPIOB_OSPD (*(volatile uint32_t *)(GPIOB_BASE + 0x08))
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#define GPIOB_PUPD (*(volatile uint32_t *)(GPIOB_BASE + 0x0c))
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#define GPIOB_ODR (*(volatile uint32_t *)(GPIOB_BASE + 0x14))
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#define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18))
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#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
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#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
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#define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
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#define GPIOD_OTYPE (*(volatile uint32_t *)(GPIOD_BASE + 0x04))
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#define GPIOD_OSPD (*(volatile uint32_t *)(GPIOD_BASE + 0x08))
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#define GPIOD_PUPD (*(volatile uint32_t *)(GPIOD_BASE + 0x0c))
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#define GPIOD_ODR (*(volatile uint32_t *)(GPIOD_BASE + 0x14))
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#define GPIOD_BSRR (*(volatile uint32_t *)(GPIOD_BASE + 0x18))
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#define GPIOD_AFL (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
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#define GPIOD_AFH (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
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#define CLOCK_FREQ (64000000)
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static void uart1_pins_setup(void)
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{
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uint32_t reg;
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RCC_AHB2ENR1_CLOCK_ER|= GPIOB_AHB2ENR1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
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GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2));
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reg = GPIOB_MODE & ~ (0x03 << (UART1_TX_PIN * 2));
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GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2));
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/* Alternate function: use low pins (6 and 7) */
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reg = GPIOB_AFL & ~(0xf << (UART1_TX_PIN * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << (UART1_TX_PIN * 4));
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reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4));
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GPIOB_AFH = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4));
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}
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static void uart3_pins_setup(void)
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{
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uint32_t reg;
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RCC_AHB2ENR1_CLOCK_ER|= GPIOD_AHB2ENR1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOD_MODE & ~ (0x03 << (UART3_RX_PIN * 2));
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GPIOD_MODE = reg | (2 << (UART3_RX_PIN * 2));
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reg = GPIOD_MODE & ~ (0x03 << (UART3_TX_PIN * 2));
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GPIOD_MODE = reg | (2 << (UART3_TX_PIN * 2));
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/* Alternate function: use hi pins (8 and 9) */
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reg = GPIOD_AFH & ~(0xf << ((UART3_TX_PIN - 8) * 4));
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GPIOD_AFH = reg | (UART3_PIN_AF << ((UART3_TX_PIN - 8) * 4));
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reg = GPIOD_AFH & ~(0xf << ((UART3_RX_PIN - 8) * 4));
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GPIOD_AFH = reg | (UART3_PIN_AF << ((UART3_RX_PIN - 8) * 4));
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}
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static int uart1_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF */
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uart1_pins_setup();
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reg = RCC_CCIPR3 & (~ (RCC_CCIPR3_LPUART1SEL_MASK << RCC_CCIPR3_LPUART1SEL_SHIFT));
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RCC_CCIPR3 = reg | (0 << RCC_CCIPR3_LPUART1SEL_SHIFT); /* PLL2 */
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/* Configure clock */
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UART1_BRR |= (uint16_t)(CLOCK_FREQ / bitrate) + 1;
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/* Configure data bits */
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if (data == 8)
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UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART1_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART1_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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UART1_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART1_CR2 & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART1_CR2 = reg & (2 << 12);
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else
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UART1_CR2 = reg;
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/* Prescaler to DIV1 */
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UART1_PRE |= 2;
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/* Configure for RX+TX, turn on. */
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UART1_CR1 |= UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE | UART_CR1_UART_ENABLE;
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return 0;
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}
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static int uart1_tx(const uint8_t c)
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{
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volatile uint32_t reg;
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do {
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reg = UART1_ISR;
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART1_TDR = c;
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return 1;
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}
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static int uart1_rx(uint8_t *c)
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{
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volatile uint32_t reg;
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int i = 0;
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reg = UART1_ISR;
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if (reg & UART_ISR_RX_NOTEMPTY) {
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*c = (uint8_t)UART1_RDR;
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return 1;
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}
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return 0;
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}
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static int uart3_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF */
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uart3_pins_setup();
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reg = RCC_CCIPR1 & (~ (RCC_CCIPR1_USART3SEL_MASK << RCC_CCIPR1_USART3SEL_SHIFT));
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RCC_CCIPR1 = reg | (0 << RCC_CCIPR1_USART3SEL_SHIFT); /* PLL2 */
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/* Configure clock */
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UART3_BRR = (uint16_t)(CLOCK_FREQ / bitrate) + 1;
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/* Configure data bits */
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if (data == 8)
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UART3_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART3_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART3_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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UART3_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART3_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART3_CR2 & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART3_CR2 = reg & (2 << 12);
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else
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UART3_CR2 = reg;
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/* Prescaler to DIV1 */
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UART3_PRE |= 2;
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/* Configure for RX+TX, turn on. */
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UART3_CR1 |= UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE | UART_CR1_UART_ENABLE;
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return 0;
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}
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static int uart3_tx(const uint8_t c)
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{
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volatile uint32_t reg;
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do {
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reg = UART3_ISR;
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART3_TDR = c;
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return 1;
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}
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static int uart3_rx(uint8_t *c)
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{
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volatile uint32_t reg;
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int i = 0;
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reg = UART3_ISR;
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if (reg & UART_ISR_RX_NOTEMPTY) {
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*c = (uint8_t)UART3_RDR;
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return 1;
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}
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return 0;
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}
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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#if USE_UART1
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return uart1_init(bitrate, data, parity, stop);
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#else
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return uart3_init(bitrate, data, parity, stop);
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#endif
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}
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int uart_tx(const uint8_t c)
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{
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#if USE_UART1
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return uart1_tx(c);
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#else
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return uart3_tx(c);
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#endif
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}
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int uart_rx(uint8_t *c)
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{
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#if USE_UART1
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return uart1_rx(c);
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#else
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return uart3_rx(c);
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#endif
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}
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