mirror of https://github.com/wolfSSL/wolfBoot.git
113 lines
5.4 KiB
C
113 lines
5.4 KiB
C
/* cm4.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* Raspberry Pi Compute Module 4 (CM4) - Broadcom BCM2711, Cortex-A72.
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* Hardware register map (bases, UART, EMMC2/SDHCI) shared by the HAL and the
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* test application. This header is also included from boot_aarch64_start.S, so
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* pointer-cast accessors are guarded with __ASSEMBLER__. */
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#ifndef _CM4_H_
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#define _CM4_H_
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/* Select the compact AArch64 startup path in boot_aarch64_start.S */
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#define USE_BUILTIN_STARTUP
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#define USE_SIMPLE_STARTUP
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/* BCM2711 peripheral base addresses (low-peripheral 0xFE000000 view).
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* Integer literals - safe to include from assembly. */
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#define BCM2711_MMIO_BASE 0xFE000000
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#define BCM2711_GPIO_BASE (BCM2711_MMIO_BASE + 0x200000)
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#define BCM2711_UART0_BASE (BCM2711_GPIO_BASE + 0x1000) /* PL011 */
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/* The debug cable on GPIO14/15 is the BCM2711 mini-UART (AUX / 8250-style,
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* Linux ttyS0), NOT the PL011. The firmware leaves it enabled with a stable
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* baud (enable_uart=1 fixes core_freq), so wolfBoot inherits it. */
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#define BCM2711_AUX_BASE (BCM2711_GPIO_BASE + 0x15000) /* AUX (mini-UART) */
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/* Overridable so host unit tests can retarget the SDHCI glue at a mock buffer */
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#ifndef BCM2711_EMMC2_BASE
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#define BCM2711_EMMC2_BASE (BCM2711_MMIO_BASE + 0x340000) /* Arasan SDHCI */
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#endif
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#define BCM2711_RNG_BASE (BCM2711_MMIO_BASE + 0x104000) /* RNG200 TRNG */
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/* RNG200 (iproc-rng200) register offsets */
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#define RNG200_CTRL 0x00 /* bit0 RBGEN = enable */
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#define RNG200_SOFT_RESET 0x04
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#define RNG200_RBG_SOFT_RESET 0x08
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#define RNG200_INT_STATUS 0x18
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#define RNG200_FIFO_DATA 0x20
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#define RNG200_FIFO_COUNT 0x24 /* [7:0] = words available */
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#define RNG200_CTRL_RBGEN 0x00000001
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/* SP800-90B health-test status bits in RNG200_INT_STATUS (iproc-rng200).
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* MASTER_FAIL_LOCKOUT latches when the continuous test trips repeatedly;
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* NIST_FAIL flags a startup/continuous health-test failure. Either means the
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* entropy source is degraded and must not seed the FIPS DRBG. */
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#define RNG200_INT_MASTER_FAIL_LOCKOUT 0x80000000
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#define RNG200_INT_STARTUP_TRANSITIONS_MET 0x00020000
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#define RNG200_INT_NIST_FAIL 0x00000020
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#define RNG200_INT_TOTAL_BITS_COUNT 0x00000001
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#define RNG200_INT_HEALTH_FAIL \
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(RNG200_INT_MASTER_FAIL_LOCKOUT | RNG200_INT_NIST_FAIL)
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/* BCM2711 system counter frequency (fallback if CNTFRQ_EL0 reads 0) */
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#define BCM2711_TIMER_CLK_FREQ 54000000ULL
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/* SDHCI register offsets used by the EMMC2 glue. The generic SDHCI driver
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* addresses registers with Cadence-style SRS offsets (0x200 + std); the glue
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* translates to the standard Arasan layout below. Integers, assembler-safe. */
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#define CADENCE_SRS_OFFSET 0x200
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#define STD_SDHCI_SDMA_ADDR 0x00 /* SDMA System Address (32-bit) */
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#define STD_SDHCI_HOST_CTRL1 0x28
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#define STD_SDHCI_POWER_CTRL 0x29
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#define STD_SDHCI_BLKGAP_CTRL 0x2A
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#define STD_SDHCI_WAKEUP_CTRL 0x2B
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#define STD_SDHCI_CLK_CTRL 0x2C
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#define STD_SDHCI_TIMEOUT_CTRL 0x2E
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#define STD_SDHCI_SW_RESET 0x2F
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#define STD_SDHCI_HOST_CTRL2 0x3C
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#define STD_SDHCI_SRA 0x01 /* Software Reset for All */
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#ifndef __ASSEMBLER__
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/* PL011 UART0 register accessors (not the debug console on this board) */
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#define UART0_DR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x00))
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#define UART0_FR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x18))
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#define UART0_IBRD ((volatile unsigned int*)(BCM2711_UART0_BASE+0x24))
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#define UART0_FBRD ((volatile unsigned int*)(BCM2711_UART0_BASE+0x28))
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#define UART0_LCRH ((volatile unsigned int*)(BCM2711_UART0_BASE+0x2C))
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#define UART0_CR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x30))
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#define UART0_ICR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x44))
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/* Mini-UART (AUX) register accessors - the actual debug console (Linux ttyS0).
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* 8250/16550-style: IO at +0x40 (data), LSR at +0x54 (bit5 = TX can accept). */
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#define MU_IO ((volatile unsigned int*)(BCM2711_AUX_BASE+0x40))
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#define MU_LSR ((volatile unsigned int*)(BCM2711_AUX_BASE+0x54))
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#define MU_LSR_TXFF_EMPTY 0x20 /* transmit FIFO can accept a byte */
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/* RNG200 hardware TRNG register accessors */
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#define RNG_CTRL ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_CTRL))
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#define RNG_SOFT_RESET ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_SOFT_RESET))
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#define RNG_RBG_SOFT_RESET ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_RBG_SOFT_RESET))
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#define RNG_INT_STATUS ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_INT_STATUS))
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#define RNG_FIFO_DATA ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_FIFO_DATA))
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#define RNG_FIFO_COUNT ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_FIFO_COUNT))
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#endif /* !__ASSEMBLER__ */
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#endif /* _CM4_H_ */
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