mirror of https://github.com/wolfSSL/wolfBoot.git
615 lines
26 KiB
C
615 lines
26 KiB
C
/* nrf54l.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef _HAL_NRF54L_H_
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#define _HAL_NRF54L_H_
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#include <stdint.h>
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#include <string.h>
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void uart_write_device(int device, const char* buf, unsigned int sz);
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void uart_write(const char* buf, unsigned int sz);
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#if (UART_FLASH)
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop);
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#else
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void uart_init(void);
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#endif
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#if !defined(TZEN) || !defined(NONSECURE_APP)
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/* Use secure addresses */
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# define TZ_SECURE() 1
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#else
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/* Use non-secure addresses */
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# define TZ_SECURE() 0
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#endif
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#define CPU_CLOCK 128000000UL
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#define FLASH_BASE_ADDR (0x00000000UL)
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#define FLASH_SIZE (1560576UL) /* 1524KB (nRF54L15) */
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/* The RRAM doesn't have a page size, this is just for wolfBoot purposes */
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#define FLASH_PAGE_SIZE (0x1000UL) /* 4KB granularity */
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#define FLASH_END (FLASH_BASE_ADDR + FLASH_SIZE)
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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#define DSB() __asm__ volatile ("dsb")
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#define ISB() __asm__ volatile ("isb")
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#define NOP() __asm__ volatile ("nop")
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/* PSEL Port (bit 5) - used across UART/SPI GPIO muxing */
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#define PSEL_PORT(n) (((n) & 0x7) << 5)
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#if TZ_SECURE()
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#define CLOCK_BASE_DEFAULT (0x5010E000UL)
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#define OSCILLATORS_BASE_DEFAULT (0x50120000UL)
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#else
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#define CLOCK_BASE_DEFAULT (0x4010E000UL)
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#define OSCILLATORS_BASE_DEFAULT (0x40120000UL)
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#endif
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#define CLOCK_BASE CLOCK_BASE_DEFAULT
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#define OSCILLATORS_BASE OSCILLATORS_BASE_DEFAULT
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#define FICR_BASE (0x00FFC000UL)
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/* Clock control registers */
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#define CLOCK_TASKS_XOSTART *((volatile uint32_t *)(CLOCK_BASE + 0x000))
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#define CLOCK_TASKS_LFCLKSTART *((volatile uint32_t *)(CLOCK_BASE + 0x010))
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#define CLOCK_EVENTS_XOSTARTED *((volatile uint32_t *)(CLOCK_BASE + 0x100))
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#define CLOCK_EVENTS_LFCLKSTARTED *((volatile uint32_t *)(CLOCK_BASE + 0x108))
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#define CLOCK_XO_STAT *((volatile uint32_t *)(CLOCK_BASE + 0x40C))
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#define CLOCK_LFCLK_SRC *((volatile uint32_t *)(CLOCK_BASE + 0x440))
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#define CLOCK_LFCLK_STAT *((volatile uint32_t *)(CLOCK_BASE + 0x44C))
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#define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Trigger 0x1UL
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#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger 0x1UL
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#define CLOCK_XO_STAT_STATE_Pos 16UL
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#define CLOCK_XO_STAT_STATE_Msk (0x1UL << CLOCK_XO_STAT_STATE_Pos)
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#define CLOCK_XO_STAT_STATE_NotRunning 0x0UL
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#define CLOCK_XO_STAT_STATE_Running 0x1UL
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#define CLOCK_LFCLK_SRC_SRC_Pos 0UL
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#define CLOCK_LFCLK_SRC_SRC_Msk (0x3UL << CLOCK_LFCLK_SRC_SRC_Pos)
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#define CLOCK_LFCLK_SRC_SRC_LFRC 0x0UL
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#define CLOCK_LFCLK_SRC_SRC_LFXO 0x1UL
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#define CLOCK_LFCLK_SRC_SRC_LFSYNT 0x2UL
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#define CLOCK_LFCLK_STAT_SRC_Pos 0UL
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#define CLOCK_LFCLK_STAT_SRC_Msk (0x3UL << CLOCK_LFCLK_STAT_SRC_Pos)
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#define CLOCK_LFCLK_STAT_SRC_LFRC 0x0UL
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#define CLOCK_LFCLK_STAT_SRC_LFXO 0x1UL
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#define CLOCK_LFCLK_STAT_SRC_LFSYNT 0x2UL
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#define CLOCK_LFCLK_STAT_STATE_Pos 16UL
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#define CLOCK_LFCLK_STAT_STATE_Msk (0x1UL << CLOCK_LFCLK_STAT_STATE_Pos)
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#define CLOCK_LFCLK_STAT_STATE_NotRunning 0x0UL
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#define CLOCK_LFCLK_STAT_STATE_Running 0x1UL
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/* LFCLK source and oscillator trims */
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#define OSCILLATORS_XOSC32KI_INTCAP *((volatile uint32_t *)(OSCILLATORS_BASE + 0x904))
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#define OSCILLATORS_XOSC32KI_INTCAP_ResetValue 0x00000017UL
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#define OSCILLATORS_XOSC32KI_INTCAP_VAL_Pos 0UL
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#define OSCILLATORS_XOSC32KI_INTCAP_VAL_Msk (0x1FUL << OSCILLATORS_XOSC32KI_INTCAP_VAL_Pos)
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#define FICR_XOSC32KTRIM *((volatile uint32_t *)(FICR_BASE + 0x624))
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#define FICR_XOSC32KTRIM_ResetValue 0xFFFFFFFFUL
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#define FICR_XOSC32KTRIM_OFFSET_Pos 16UL
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#define FICR_XOSC32KTRIM_OFFSET_Msk (0x3FFUL << FICR_XOSC32KTRIM_OFFSET_Pos)
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/* RRAM controller */
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#define RRAMC_BASE_DEFAULT (0x5004B000UL)
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#define RRAMC_BASE RRAMC_BASE_DEFAULT
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#define RRAMC_TASKS_COMMITWRITEBUF *((volatile uint32_t *)(RRAMC_BASE + 0x008))
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#define RRAMC_READY *((volatile uint32_t *)(RRAMC_BASE + 0x400))
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#define RRAMC_READYNEXT *((volatile uint32_t *)(RRAMC_BASE + 0x404))
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#define RRAMC_BUFSTATUS_WRITEBUFEMPTY *((volatile uint32_t *)(RRAMC_BASE + 0x418))
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#define RRAMC_CONFIG *((volatile uint32_t *)(RRAMC_BASE + 0x500))
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#define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Trigger 0x1UL
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#define RRAMC_READY_READY_Pos 0UL
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#define RRAMC_READY_READY_Msk (0x1UL << RRAMC_READY_READY_Pos)
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#define RRAMC_READYNEXT_READYNEXT_Pos 0UL
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#define RRAMC_READYNEXT_READYNEXT_Msk (0x1UL << RRAMC_READYNEXT_READYNEXT_Pos)
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#define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos 0UL
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#define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Msk \
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(0x1UL << RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos)
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#define RRAMC_CONFIG_WEN_Pos 0UL
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#define RRAMC_CONFIG_WEN_Msk (0x1UL << RRAMC_CONFIG_WEN_Pos)
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/* TWIM */
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#if TZ_SECURE()
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#define TWIM20_BASE_DEFAULT (0x500C6000UL)
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#else
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#define TWIM20_BASE_DEFAULT (0x400C6000UL)
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#endif
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#define PMIC_TWIM_BASE TWIM20_BASE_DEFAULT
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#define TWIM_TASKS_STOP(base) (*((volatile uint32_t *)((base) + 0x004)))
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#define TWIM_TASKS_DMA_RX_START(base) (*((volatile uint32_t *)((base) + 0x028)))
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#define TWIM_TASKS_DMA_TX_START(base) (*((volatile uint32_t *)((base) + 0x050)))
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#define TWIM_EVENTS_STOPPED(base) (*((volatile uint32_t *)((base) + 0x104)))
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#define TWIM_EVENTS_ERROR(base) (*((volatile uint32_t *)((base) + 0x114)))
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#define TWIM_EVENTS_LASTRX(base) (*((volatile uint32_t *)((base) + 0x134)))
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#define TWIM_EVENTS_LASTTX(base) (*((volatile uint32_t *)((base) + 0x138)))
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#define TWIM_EVENTS_DMA_RX_END(base) (*((volatile uint32_t *)((base) + 0x14C)))
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#define TWIM_EVENTS_DMA_TX_END(base) (*((volatile uint32_t *)((base) + 0x168)))
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#define TWIM_SHORTS_REG(base) (*((volatile uint32_t *)((base) + 0x200)))
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#define TWIM_ERRORSRC_REG(base) (*((volatile uint32_t *)((base) + 0x4C4)))
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#define TWIM_ENABLE_REG(base) (*((volatile uint32_t *)((base) + 0x500)))
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#define TWIM_FREQUENCY_REG(base) (*((volatile uint32_t *)((base) + 0x524)))
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#define TWIM_ADDRESS_REG(base) (*((volatile uint32_t *)((base) + 0x588)))
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#define TWIM_PSEL_SCL_REG(base) (*((volatile uint32_t *)((base) + 0x600)))
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#define TWIM_PSEL_SDA_REG(base) (*((volatile uint32_t *)((base) + 0x604)))
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#define TWIM_DMA_RX_PTR(base) (*((volatile uint32_t *)((base) + 0x704)))
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#define TWIM_DMA_RX_MAXCNT(base) (*((volatile uint32_t *)((base) + 0x708)))
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#define TWIM_DMA_RX_TERMINATE(base) (*((volatile uint32_t *)((base) + 0x71C)))
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#define TWIM_DMA_TX_PTR(base) (*((volatile uint32_t *)((base) + 0x73C)))
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#define TWIM_DMA_TX_MAXCNT(base) (*((volatile uint32_t *)((base) + 0x740)))
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#define TWIM_DMA_TX_TERMINATE(base) (*((volatile uint32_t *)((base) + 0x754)))
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#define TWIM_TASKS_STOP_TASKS_STOP_Trigger 0x1UL
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#define TWIM_TASKS_DMA_RX_START_START_Trigger 0x1UL
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#define TWIM_TASKS_DMA_TX_START_START_Trigger 0x1UL
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#define TWIM_ENABLE_ENABLE_Disabled 0x0UL
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#define TWIM_ENABLE_ENABLE_Enabled 0x6UL
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#define TWIM_FREQUENCY_FREQUENCY_K100 0x01980000UL
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#define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled 0x1UL
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#define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled 0x1UL
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#define TWIM_SHORTS_LASTTX_DMA_RX_START_Msk (0x1UL << 7)
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#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << 9)
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#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << 12)
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/* GPIO */
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#if TZ_SECURE()
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#define GPIO_P0_S_BASE (0x5010A000UL)
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#define GPIO_P1_S_BASE (0x500D8200UL)
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#define GPIO_P2_S_BASE (0x50050400UL)
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#else
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#define GPIO_P0_NS_BASE (0x4010A000UL)
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#define GPIO_P1_NS_BASE (0x400D8200UL)
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#define GPIO_P2_NS_BASE (0x40050400UL)
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#endif
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/* GPIO configuration */
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#if TZ_SECURE()
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#define GPIO_PORT0_BASE_DEFAULT GPIO_P0_S_BASE
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#define GPIO_PORT1_BASE_DEFAULT GPIO_P1_S_BASE
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#define GPIO_PORT2_BASE_DEFAULT GPIO_P2_S_BASE
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#else
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#define GPIO_PORT0_BASE_DEFAULT GPIO_P0_NS_BASE
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#define GPIO_PORT1_BASE_DEFAULT GPIO_P1_NS_BASE
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#define GPIO_PORT2_BASE_DEFAULT GPIO_P2_NS_BASE
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#endif
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#define GPIO0_BASE GPIO_PORT0_BASE_DEFAULT
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#define GPIO1_BASE GPIO_PORT1_BASE_DEFAULT
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#define GPIO2_BASE GPIO_PORT2_BASE_DEFAULT
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static inline uintptr_t hal_gpio_port_base(unsigned int port)
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{
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switch (port) {
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case 0:
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return (uintptr_t)GPIO0_BASE;
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case 1:
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return (uintptr_t)GPIO1_BASE;
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case 2:
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return (uintptr_t)GPIO2_BASE;
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default:
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return (uintptr_t)GPIO0_BASE;
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}
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}
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#define GPIO_BASE(n) hal_gpio_port_base((unsigned int)(n))
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#define GPIO_OUT(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x000))
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#define GPIO_OUTSET(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x004))
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#define GPIO_OUTCLR(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x008))
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#define GPIO_DIRSET(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x014))
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#define GPIO_DIRCLR(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x018))
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#define GPIO_PIN_CNF(n, p) *((volatile uint32_t *)(GPIO_BASE(n) + 0x080 + ((p) * 0x4)))
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#define GPIO_CNF_IN 0 // input
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#define GPIO_CNF_OUT 1 // output
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#define GPIO_CNF_IN_DIS 2 // input, disconnect input buffer
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#define GPIO_CNF_OUT_DIS 3 // output, disconnect input buffer
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#define GPIO_CNF_PULL_DIS 0
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#define GPIO_CNF_PULL_UP (3UL << 2)
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#define GPIO_CNF_PULL_DOWN (1UL << 2)
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#define GPIO_CNF_STD_DRIVE_0 0
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#define GPIO_CNF_HIGH_DRIVE_0 (1UL << 8) // High drive
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#define GPIO_CNF_EXTRA_HIGH_DRIVE_0 (3UL << 8) // Extra-High drive
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#define GPIO_CNF_STD_DRIVE_1 0
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#define GPIO_CNF_HIGH_DRIVE_1 (1UL << 10) // High drive
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#define GPIO_CNF_EXTRA_HIGH_DRIVE_1 (3UL << 10) // Extra-High drive
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#define GPIO_CNF_SENSE_NONE 0
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#define GPIO_CNF_MCUSEL(n) (((n) & 0x7) << 28)
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/* UART */
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// UART Device P0 P1 P2
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// -----------------------------
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// NRF_UARTE00 XX (P2 dedicated)
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// NRF_UARTE20 XX (XX) (P2 cross-domain only)
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// NRF_UARTE21 XX (XX) (P2 cross-domain only)
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// NRF_UARTE22 XX
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// NRF_UARTE30 XX
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#define UARTE20_S_BASE 0x500C6000UL // monitor (secure)
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#define UARTE30_S_BASE 0x50104000UL // download (secure)
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#define UARTE20_NS_BASE 0x400C6000UL // monitor (non-secure)
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#define UARTE30_NS_BASE 0x40104000UL // download (non-secure)
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#define DEVICE_MONITOR 1
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#define DEVICE_DOWNLOAD 2
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// setup for DK board
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#define PORT_MONITOR 1
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#define PIN_TX_MONITOR 4
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#define PIN_RX_MONITOR 5
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#if TZ_SECURE()
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#define BASE_ADDR_MONITOR UARTE20_S_BASE
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#else
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#define BASE_ADDR_MONITOR UARTE20_NS_BASE
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#endif
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// setup for DK board
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#define PORT_DOWNLOAD 0
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#define PIN_TX_DOWNLOAD 0
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#define PIN_RX_DOWNLOAD 1
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#if TZ_SECURE()
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#define BASE_ADDR_DOWNLOAD UARTE30_S_BASE
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#else
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#define BASE_ADDR_DOWNLOAD UARTE30_NS_BASE
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#endif
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static inline uintptr_t hal_uart_port_base(int device)
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{
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switch (device) {
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case DEVICE_DOWNLOAD:
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return (uintptr_t) BASE_ADDR_DOWNLOAD;
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case DEVICE_MONITOR:
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default:
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return (uintptr_t) BASE_ADDR_MONITOR;
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}
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}
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static inline int hal_uart_port_num(int device)
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{
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switch (device) {
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case DEVICE_DOWNLOAD:
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return (int) PORT_DOWNLOAD;
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case DEVICE_MONITOR:
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default:
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return (int) PORT_MONITOR;
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}
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}
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static inline int hal_uart_pin_num_tx(int device)
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{
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switch (device) {
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case DEVICE_DOWNLOAD:
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return (int) PIN_TX_DOWNLOAD;
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case DEVICE_MONITOR:
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default:
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return (int) PIN_TX_MONITOR;
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}
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}
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static inline int hal_uart_pin_num_rx(int device)
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{
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switch (device) {
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case DEVICE_DOWNLOAD:
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return (int) PIN_RX_DOWNLOAD;
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case DEVICE_MONITOR:
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default:
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return (int) PIN_RX_MONITOR;
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}
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}
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/* UART Addressing */
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#define UART_PORT_NUM(n) hal_uart_port_num((unsigned int)(n))
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#define UART_PIN_NUM_TX(n) hal_uart_pin_num_tx((unsigned int)(n))
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#define UART_PIN_NUM_RX(n) hal_uart_pin_num_rx((unsigned int)(n))
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#define UART_BASE(n) hal_uart_port_base((unsigned int)(n))
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#define UART_PSEL_TXD(n) *((volatile uint32_t *)(UART_BASE(n) + 0x604 + 0x000))
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#define UART_PSEL_CTS(n) *((volatile uint32_t *)(UART_BASE(n) + 0x604 + 0x004))
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#define UART_PSEL_RXD(n) *((volatile uint32_t *)(UART_BASE(n) + 0x604 + 0x008))
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#define UART_PSEL_RTS(n) *((volatile uint32_t *)(UART_BASE(n) + 0x604 + 0x00C))
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#define UART_ENABLE(n) *((volatile uint32_t *)(UART_BASE(n) + 0x500))
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#define UART_BAUDRATE(n) *((volatile uint32_t *)(UART_BASE(n) + 0x524))
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#define UART_CONFIG(n) *((volatile uint32_t *)(UART_BASE(n) + 0x56C))
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#define UART_DMA_TX_PTR(n) *((volatile uint32_t *)(UART_BASE(n) + 0x700 + 0x038 + 0x004))
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#define UART_DMA_TX_MAXCNT(n) *((volatile uint32_t *)(UART_BASE(n) + 0x700 + 0x038 + 0x008))
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#define UART_DMA_RX_PTR(n) *((volatile uint32_t *)(UART_BASE(n) + 0x700 + 0x000 + 0x004))
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#define UART_DMA_RX_MAXCNT(n) *((volatile uint32_t *)(UART_BASE(n) + 0x700 + 0x000 + 0x008))
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#define UART_DMA_RX_AMOUNT(n) *((volatile uint32_t *)(UART_BASE(n) + 0x700 + 0x000 + 0x00C))
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#define UART_EVENTS_DMA_TX_END(n) *((volatile uint32_t *)(UART_BASE(n) + 0x14C + 0x01C + 0x000))
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#define UART_EVENTS_DMA_TX_BUSERROR(n) *((volatile uint32_t *)(UART_BASE(n) + 0x14C + 0x01C + 0x008))
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#define UART_EVENTS_DMA_RX_END(n) *((volatile uint32_t *)(UART_BASE(n) + 0x14C + 0x000 + 0x000))
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#define UART_EVENTS_DMA_RX_BUSERROR(n) *((volatile uint32_t *)(UART_BASE(n) + 0x14C + 0x000 + 0x008))
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#define UART_TASKS_DMA_TX_START(n) *((volatile uint32_t *)(UART_BASE(n) + 0x028 + 0x028 + 0x000))
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#define UART_TASKS_DMA_TX_STOP(n) *((volatile uint32_t *)(UART_BASE(n) + 0x028 + 0x028 + 0x004))
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#define UART_TASKS_DMA_RX_START(n) *((volatile uint32_t *)(UART_BASE(n) + 0x028 + 0x000 + 0x000))
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#define UART_TASKS_DMA_RX_STOP(n) *((volatile uint32_t *)(UART_BASE(n) + 0x028 + 0x000 + 0x004))
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/* UART Settings */
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#define UART_ENABLE_ENABLE_Enabled 0x8UL
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#define UART_ENABLE_ENABLE_Disabled 0x0UL
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#define UART_PSEL_TXD_PIN_Pos 0UL
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#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos)
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#define UART_PSEL_TXD_PORT_Pos 5UL
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#define UART_PSEL_TXD_PORT_Msk (0x7UL << UART_PSEL_TXD_PORT_Pos)
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#define UART_PSEL_RXD_PIN_Pos 0UL
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#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos)
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#define UART_PSEL_RXD_PORT_Pos 0x5UL
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#define UART_PSEL_RXD_PORT_Msk (0x7UL << UART_PSEL_RXD_PORT_Pos)
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#define UART_PSEL_CTS_CONNECT_Disconnected (0x1UL << 31)
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#define UART_PSEL_RTS_CONNECT_Disconnected (0x1UL << 31)
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#define UART_CONFIG_VALUE(framesize, parity, stop) \
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((framesize << 9UL) | \
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((parity == 'E') ? 0x00E : \
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(parity == 'O') ? 0x10E : \
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0x000) | \
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((stop == 2) ? 0x10 : \
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0x00))
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#define UART_TASKS_DMA_TX_START_START_Trigger 0x1UL
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#define UART_TASKS_DMA_TX_STOP_STOP_Trigger 0x1UL
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#define UART_TASKS_DMA_RX_START_START_Trigger 0x1UL
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#define UART_TASKS_DMA_RX_STOP_STOP_Trigger 0x1UL
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#define UART_BAUDRATE_VALUE(rate) (rate == 1200) ? 0x0004F000 : \
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(rate == 2400) ? 0x0009D000 : \
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(rate == 4800) ? 0x0013B000 : \
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(rate == 9600) ? 0x00275000 : \
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(rate == 14400) ? 0x003AF000 : \
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(rate == 19200) ? 0x004EA000 : \
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(rate == 28800) ? 0x0075C000 : \
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(rate == 31250) ? 0x00800000 : \
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(rate == 38400) ? 0x009D0000 : \
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(rate == 56000) ? 0x00E50000 : \
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(rate == 57600) ? 0x00EB0000 : \
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(rate == 76800) ? 0x013A9000 : \
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(rate == 115200) ? 0x01D60000 : \
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(rate == 230400) ? 0x03B00000 : \
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(rate == 250000) ? 0x04000000 : \
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(rate == 460800) ? 0x07400000 : \
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(rate == 921600) ? 0x0F000000 : \
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(rate == 1000000) ? 0x10000000 : 0
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/* Nordic PMIC */
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#define PMIC_TWIM_PORT 1
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#define PMIC_TWIM_SDA_PIN 2
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#define PMIC_TWIM_SCL_PIN 3
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#define PMIC_TWIM_TIMEOUT 1000000UL
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#define PMIC_REG_PAYLOAD_MAX 8U
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#define PMIC_I2C_ADDRESS 0x6BU // from pdf p122 (110 1011)
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#define LED_PWR_CTRL_PORT 1
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#define LED_PWR_CTRL_PIN 13
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#define NPM1300_REG_TASK_LDSW2_SET 0x0802U
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#define NPM1300_REG_TASK_LDSW2_CLR 0x0803U
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#define NPM1300_REG_LDSW2_GPISEL 0x0806U
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#define NPM1300_REG_LDSWCONFIG 0x0807U
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#define NPM1300_REG_LDSW2LDOSEL 0x0809U
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#define NPM1300_REG_GPIOMODE(n) (0x0600U + (uint16_t)(n))
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#define NPM1300_REG_GPIOPUEN(n) (0x060AU + (uint16_t)(n))
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#define NPM1300_REG_GPIOPDEN(n) (0x060FU + (uint16_t)(n))
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|
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/* SPIM */
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#if TZ_SECURE()
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#define SPIM00_BASE_DEFAULT (0x5004A000UL)
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#else
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#define SPIM00_BASE_DEFAULT (0x4004A000UL)
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#endif
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#define SPI_BASE SPIM00_BASE_DEFAULT
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#define SPI_TASKS_START (*((volatile uint32_t *)(SPI_BASE + 0x000)))
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#define SPI_TASKS_STOP (*((volatile uint32_t *)(SPI_BASE + 0x004)))
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#define SPI_EVENTS_STARTED (*((volatile uint32_t *)(SPI_BASE + 0x100)))
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#define SPI_EVENTS_STOPPED (*((volatile uint32_t *)(SPI_BASE + 0x104)))
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#define SPI_EVENTS_END (*((volatile uint32_t *)(SPI_BASE + 0x108)))
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#define SPI_EVENTS_DMA_RX_END (*((volatile uint32_t *)(SPI_BASE + 0x14C + 0x000)))
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#define SPI_EVENTS_DMA_RX_READY (*((volatile uint32_t *)(SPI_BASE + 0x14C + 0x004)))
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#define SPI_EVENTS_DMA_RX_BUSERROR (*((volatile uint32_t *)(SPI_BASE + 0x14C + 0x008)))
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#define SPI_EVENTS_DMA_TX_END (*((volatile uint32_t *)(SPI_BASE + 0x14C + 0x01C)))
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#define SPI_EVENTS_DMA_TX_READY (*((volatile uint32_t *)(SPI_BASE + 0x14C + 0x020)))
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#define SPI_EVENTS_DMA_TX_BUSERROR (*((volatile uint32_t *)(SPI_BASE + 0x14C + 0x024)))
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#define SPI_ENABLE_REG (*((volatile uint32_t *)(SPI_BASE + 0x500)))
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#define SPI_PRESCALER_REG (*((volatile uint32_t *)(SPI_BASE + 0x52C)))
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#define SPI_CONFIG_REG (*((volatile uint32_t *)(SPI_BASE + 0x554)))
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#define SPI_IFTIMING_RXDELAY (*((volatile uint32_t *)(SPI_BASE + 0x5AC)))
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#define SPI_IFTIMING_CSNDUR (*((volatile uint32_t *)(SPI_BASE + 0x5B0)))
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|
|
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#define SPI_PSEL_SCK (*((volatile uint32_t *)(SPI_BASE + 0x600)))
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#define SPI_PSEL_MOSI (*((volatile uint32_t *)(SPI_BASE + 0x604)))
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#define SPI_PSEL_MISO (*((volatile uint32_t *)(SPI_BASE + 0x608)))
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#define SPI_PSEL_CSN (*((volatile uint32_t *)(SPI_BASE + 0x610)))
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|
|
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#define SPI_DMA_RX_PTR (*((volatile uint32_t *)(SPI_BASE + 0x704)))
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#define SPI_DMA_RX_MAXCNT (*((volatile uint32_t *)(SPI_BASE + 0x708)))
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#define SPI_DMA_RX_LIST (*((volatile uint32_t *)(SPI_BASE + 0x714)))
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|
|
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#define SPI_DMA_TX_PTR (*((volatile uint32_t *)(SPI_BASE + 0x73C)))
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#define SPI_DMA_TX_MAXCNT (*((volatile uint32_t *)(SPI_BASE + 0x740)))
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#define SPI_DMA_TX_LIST (*((volatile uint32_t *)(SPI_BASE + 0x74C)))
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|
|
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#define SPIM_TASKS_START_TASKS_START_Pos 0UL
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|
#define SPIM_TASKS_START_TASKS_START_Msk \
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(0x1UL << SPIM_TASKS_START_TASKS_START_Pos)
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#define SPIM_TASKS_START_TASKS_START_Trigger 0x1UL
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|
|
|
#define SPIM_TASKS_STOP_TASKS_STOP_Pos 0UL
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|
#define SPIM_TASKS_STOP_TASKS_STOP_Msk \
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(0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos)
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|
#define SPIM_TASKS_STOP_TASKS_STOP_Trigger 0x1UL
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|
|
|
#define SPIM_ENABLE_ENABLE_Pos 0UL
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|
#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos)
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|
#define SPIM_ENABLE_ENABLE_Disabled 0x0UL
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|
#define SPIM_ENABLE_ENABLE_Enabled 0x7UL
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|
|
|
#define SPIM_CONFIG_ORDER_Pos 0UL
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#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos)
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#define SPIM_CONFIG_ORDER_MsbFirst 0x0UL
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#define SPIM_CONFIG_ORDER_LsbFirst 0x1UL
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|
|
|
#define SPIM_CONFIG_CPHA_Pos 1UL
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|
#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos)
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#define SPIM_CONFIG_CPHA_Leading 0x0UL
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|
#define SPIM_CONFIG_CPHA_Trailing 0x1UL
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|
|
|
#define SPIM_CONFIG_CPOL_Pos 2UL
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|
#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos)
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|
#define SPIM_CONFIG_CPOL_ActiveHigh 0x0UL
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|
#define SPIM_CONFIG_CPOL_ActiveLow 0x1UL
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|
|
|
#define SPI_PRESCALER_DIV 0x08UL
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|
|
|
/* SPU - Security Processing Unit
|
|
*
|
|
* nRF54L has four SPU instances, one per power domain:
|
|
* SPU00 (MCU domain) 0x50040000 covers peripherals at 0x5004xxxx-0x5007xxxx
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|
* SPU10 (RADIO domain) 0x50080000 covers peripherals at 0x5008xxxx-0x500Bxxxx
|
|
* SPU20 (PERI domain) 0x500C0000 covers peripherals at 0x500Cxxxx-0x500Fxxxx
|
|
* SPU30 (LP domain) 0x50100000 covers peripherals at 0x5010xxxx-0x5013xxxx
|
|
*/
|
|
#define SPU00_BASE (0x50040000UL) /* MCU domain */
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|
#define SPU10_BASE (0x50080000UL) /* RADIO domain */
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|
#define SPU20_BASE (0x500C0000UL) /* PERI domain */
|
|
#define SPU30_BASE (0x50100000UL) /* LP domain */
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|
|
|
/* Derive which SPU instance governs a peripheral */
|
|
#define SPU_BASE_FOR(paddr) (0x50000000UL | ((paddr) & 0x00FC0000UL))
|
|
/* Derive the slave index within that SPU */
|
|
#define SPU_SLAVE_IDX(paddr) (((paddr) & 0x0003F000UL) >> 12)
|
|
|
|
#define SPU_PERIPH_PERM(spu, n) \
|
|
(*((volatile uint32_t *)((spu) + 0x500UL + (uint32_t)(n) * 4UL)))
|
|
|
|
#define SPU_FEATURE_GPIO_PIN(spu, g, p) \
|
|
(*((volatile uint32_t *)((spu) + 0x800UL + (uint32_t)(g) * 0x80UL + \
|
|
(uint32_t)(p) * 4UL)))
|
|
|
|
#define SPU_PERIPH_PERM_SECATTR (1UL << 4)
|
|
#define SPU_FEATURE_SECATTR (1UL << 4)
|
|
|
|
/* Non-secure RAM layout */
|
|
#define NS_RAM_BASE (0x20010000UL)
|
|
#define NS_RAM_SIZE (0x00030000UL)
|
|
|
|
/* MPC00 - Memory Privilege Controller */
|
|
#define MPC00_BASE (0x50041000UL)
|
|
|
|
#define MPC_OVERRIDE_CONFIG(n) \
|
|
(*((volatile uint32_t *)(MPC00_BASE + 0x800UL + (uint32_t)(n) * 0x20UL)))
|
|
#define MPC_OVERRIDE_STARTADDR(n) \
|
|
(*((volatile uint32_t *)(MPC00_BASE + 0x804UL + (uint32_t)(n) * 0x20UL)))
|
|
#define MPC_OVERRIDE_ENDADDR(n) \
|
|
(*((volatile uint32_t *)(MPC00_BASE + 0x808UL + (uint32_t)(n) * 0x20UL)))
|
|
#define MPC_OVERRIDE_PERM(n) \
|
|
(*((volatile uint32_t *)(MPC00_BASE + 0x810UL + (uint32_t)(n) * 0x20UL)))
|
|
#define MPC_OVERRIDE_PERMMASK(n) \
|
|
(*((volatile uint32_t *)(MPC00_BASE + 0x814UL + (uint32_t)(n) * 0x20UL)))
|
|
|
|
#define MPC_CONFIG_ENABLE (1UL << 9)
|
|
#define MPC_PERM_READ (1UL << 0)
|
|
#define MPC_PERM_WRITE (1UL << 1)
|
|
#define MPC_PERM_EXECUTE (1UL << 2)
|
|
#define MPC_PERM_SECURE (1UL << 3) /* 0 = NonSecure, 1 = Secure */
|
|
|
|
/* TAMPC - Tamper controller (access port protection) */
|
|
#define TAMPC_BASE (0x500DC000UL)
|
|
#define TAMPC_PROTECT_DOMAIN0_DBGEN_CTRL (*(volatile uint32_t *)(TAMPC_BASE + 0x500))
|
|
#define TAMPC_PROTECT_DOMAIN0_NIDEN_CTRL (*(volatile uint32_t *)(TAMPC_BASE + 0x508))
|
|
#define TAMPC_PROTECT_DOMAIN0_SPIDEN_CTRL (*(volatile uint32_t *)(TAMPC_BASE + 0x510))
|
|
#define TAMPC_PROTECT_DOMAIN0_SPNIDEN_CTRL (*(volatile uint32_t *)(TAMPC_BASE + 0x518))
|
|
#define TAMPC_PROTECT_AP0_DBGEN_CTRL (*(volatile uint32_t *)(TAMPC_BASE + 0x700))
|
|
|
|
/* KEY=0x50FA at bits[31:16], WRITEPROTECTION_Clear=0xF at bits[7:4] */
|
|
#define TAMPC_SIGNAL_CLEAR_WRITEPROTECTION (0x50FA00F0UL)
|
|
/* KEY=0x50FA at bits[31:16], VALUE=High at bit[0], LOCK=Disabled at bit[1] */
|
|
#define TAMPC_SIGNAL_OPEN (0x50FA0001UL)
|
|
#define TAMPC_SIGNAL_LOCK_Msk (1UL << 1)
|
|
|
|
/* CRACEN (Crypto Accelerator) */
|
|
#define CRACEN_BASE (0x50048000UL)
|
|
#define CRACENCORE_BASE (0x51800000UL)
|
|
|
|
/* CRACEN.ENABLE register (offset 0x400) */
|
|
#define CRACEN_ENABLE (*((volatile uint32_t *)(CRACEN_BASE + 0x400)))
|
|
#define CRACEN_ENABLE_RNG_Msk (0x1UL << 1)
|
|
|
|
#define CRACENCORE_RNGCTRL_BASE (CRACENCORE_BASE + 0x1000UL)
|
|
|
|
#define CRACENCORE_RNG_CONTROL (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x000)))
|
|
#define CRACENCORE_RNG_FIFOLEVEL (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x004)))
|
|
#define CRACENCORE_RNG_KEY(n) (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x010 + (n)*4)))
|
|
#define CRACENCORE_RNG_STATUS (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x030)))
|
|
#define CRACENCORE_RNG_INITWAITVAL (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x034)))
|
|
#define CRACENCORE_RNG_SWOFFTMRVAL (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x040)))
|
|
#define CRACENCORE_RNG_CLKDIV (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x044)))
|
|
#define CRACENCORE_RNG_FIFO (*((volatile uint32_t *)(CRACENCORE_RNGCTRL_BASE + 0x080)))
|
|
|
|
#define CRACENCORE_RNG_CONTROL_ENABLE_Msk (0x1UL << 0)
|
|
#define CRACENCORE_RNG_CONTROL_SOFTRST_Msk (0x1UL << 8)
|
|
#define CRACENCORE_RNG_CONTROL_NB128BITBLOCKS_Pos 16
|
|
#define CRACENCORE_RNG_CONTROL_NB128BITBLOCKS_Msk (0xFUL << CRACENCORE_RNG_CONTROL_NB128BITBLOCKS_Pos)
|
|
|
|
#define CRACENCORE_RNG_STATUS_STATE_Pos 1
|
|
#define CRACENCORE_RNG_STATUS_STATE_Msk (0x7UL << CRACENCORE_RNG_STATUS_STATE_Pos)
|
|
#define CRACENCORE_RNG_STATUS_STATE_RESET 0x0UL
|
|
#define CRACENCORE_RNG_STATUS_STATE_STARTUP 0x1UL
|
|
|
|
/* TRNG configuration values recommended by Nordic */
|
|
#define CRACENCORE_RNG_INITWAITVAL_DEFAULT 512UL
|
|
#define CRACENCORE_RNG_NB128BITBLOCKS_DEFAULT 4UL
|
|
|
|
#endif /* _HAL_NRF54L_H_ */
|