mirror of https://github.com/wolfSSL/wolfBoot.git
999 lines
34 KiB
C
999 lines
34 KiB
C
/* nxp_ppc.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef _NXP_PPC_H_
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#define _NXP_PPC_H_
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#ifdef TARGET_nxp_p1021
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/* NXP P1021 */
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#define CPU_NUMCORES 2
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#define CORE_E500
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#define LAW_MAX_ENTRIES 12
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#define CCSRBAR_DEF (0xFF700000UL) /* P1021RM 4.3 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_1M
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#define DDR_SIZE (512UL * 1024UL * 1024UL)
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#endif
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/* Memory used for transferring blocks to/from NAND.
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* Maps to eLBC FCM internal 8KB region (by hardware) */
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#define FLASH_BASE_ADDR 0xFC000000UL
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#ifdef BUILD_LOADER_STAGE1
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/* First stage loader features */
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#define ENABLE_L2_CACHE
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#define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */
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#define L2SRAM_SIZE (256UL * 1024UL)
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#define INITIAL_SRAM_ADDR L2SRAM_ADDR
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_ELBC
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
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#else
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/* For wolfBoot features */
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#define ENABLE_L1_CACHE
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#define ENABLE_L2_CACHE
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/* Relocate CCSRBAR */
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#define CCSRBAR 0xFFE00000UL
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#define ENABLE_INTERRUPTS
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#endif
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#elif defined(TARGET_nxp_t1024)
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/* NXP T1024 */
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#define CORE_E5500
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#define CPU_NUMCORES 2
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#define CORES_PER_CLUSTER 1
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#define LAW_MAX_ENTRIES 16
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#define CCSRBAR_DEF (0xFE000000) /* T1024RM 4.4.1 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
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#define INITIAL_SRAM_ADDR 0xFDFC0000
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_PSRAM
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
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#define ENABLE_L1_CACHE
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#define ENABLE_INTERRUPTS
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#ifdef BUILD_LOADER_STAGE1
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#define ENABLE_L2_CACHE /* setup and enable L2 in first stage only */
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#else
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/* relocate to 64-bit 0xF_ */
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#define CCSRBAR_PHYS_HIGH 0xF
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#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
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#endif
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#define DDR_SIZE (2048ULL * 1024ULL * 1024ULL)
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#endif
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#define FLASH_BASE_ADDR 0xEC000000UL
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#ifndef BUILD_LOADER_STAGE1
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#define FLASH_BASE_PHYS_HIGH 0xF /* 36-bit: 0xF_EC000000 */
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#else
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#define FLASH_BASE_PHYS_HIGH 0x0 /* 32-bit stage1 */
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#endif
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#define FLASH_LAW_SIZE LAW_SIZE_64MB
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#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M
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#define USE_LONG_JUMP
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#elif defined(TARGET_nxp_t1040)
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/* NXP T1040 */
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#define CORE_E5500
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#define CPU_NUMCORES 4
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#define CORES_PER_CLUSTER 1
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#define LAW_MAX_ENTRIES 16
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#define CCSRBAR_DEF (0xFE000000) /* T1040RM 4.4.1 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
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#define ENABLE_L1_CACHE
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#define ENABLE_INTERRUPTS
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/* T1040 has a 256KB CPC (CoreNet Platform Cache), not PSRAM.
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* Stage1: Use L1 locked dcache (16KB) as initial stack before DDR.
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* wolfBoot main: DDR already initialized by stage1, use DDR stack. */
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#ifdef BUILD_LOADER_STAGE1
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#define L1_CACHE_ADDR (0xFDFC0000UL)
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#endif
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#define L2SRAM_ADDR (0xFDFE0000UL) /* CPC as SRAM (256KB) */
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#define L2SRAM_SIZE (256UL * 1024UL)
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#define INITIAL_SRAM_ADDR L2SRAM_ADDR
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1 /* CPC target per T1040RM */
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
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#ifdef BUILD_LOADER_STAGE1
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#define ENABLE_L2_CACHE
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#else
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/* relocate to 64-bit 0xF_ */
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#define CCSRBAR_PHYS_HIGH 0xF
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#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
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#endif
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* 8GB */
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#endif
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/* 128MB NOR: 0xE8000000 - 0xEFFFFFFF */
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#define FLASH_BASE_ADDR 0xE8000000UL
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#ifndef BUILD_LOADER_STAGE1
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#define FLASH_BASE_PHYS_HIGH 0xF /* 36-bit: 0xF_E8000000 */
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#else
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#define FLASH_BASE_PHYS_HIGH 0x0 /* 32-bit stage1 */
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#endif
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#define FLASH_LAW_SIZE LAW_SIZE_128MB
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/* e5500 BookE has no 128M page size (64M->256M), use 256M TLB */
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#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_256M
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#define USE_LONG_JUMP
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#elif defined(TARGET_nxp_t2080)
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/* NXP T2080: 4 cores in a single cluster with a shared 2 MB L2; each
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* core has 2 hardware threads (software sees 8 virtual CPUs). */
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#define CORE_E6500
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#define CPU_NUMCORES 4
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#define CORES_PER_CLUSTER 4
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#define LAW_MAX_ENTRIES 32
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#define ENABLE_PPC64
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#define CCSRBAR_DEF 0xFE000000 /* T2080RM 4.3.1 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
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#define ENABLE_L1_CACHE
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#define ENABLE_L2_CACHE
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/* L1 locked dcache as initial stack (16KB).
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* CPC SRAM (via CoreNet) is unreliable on cold power cycle —
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* store buffer drains cause bus errors. L1 locked cache is
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* core-local and works reliably from first instruction.
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* Address chosen below CPC SRAM range, no backing memory needed.
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*
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* VPX3-152: default addresses (0xF8E/F8F) fall within 256MB flash
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* VA range (0xF0000000-0xFFFFFFFF), causing TLB overlap on e6500.
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* Relocated below CCSRBAR (0xEF000000) to avoid conflict. */
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#ifdef BOARD_CW_VPX3152
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#define L1_CACHE_ADDR (0xEE800000UL)
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#define L2SRAM_ADDR (0xEE900000UL) /* CPC as SRAM (1MB) */
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#else
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#define L1_CACHE_ADDR (0xF8E00000UL)
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#define L2SRAM_ADDR (0xF8F00000UL) /* CPC as SRAM (1MB) */
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#endif
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#define L2SRAM_SIZE (1024UL * 1024UL)
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#define INITIAL_SRAM_ADDR L2SRAM_ADDR
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/* CPC SRAM transactions traverse the CoreNet interconnect, which
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* requires a LAW to route them. LAW_TRGT_DDR_1 (0x10) is the CPC
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* target per T2080RM Table 2-2 (Target ID Assignments). */
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_1MB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_1M
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#define ENABLE_INTERRUPTS
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#define ENABLE_FMAN
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#ifdef BOARD_CW_VPX3152
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/* Relocate CCSRBAR: default 0xFE000000 (16MB) falls within the 256MB
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* flash VA range 0xF0000000-0xFFFFFFFF. Move to 0xEF000000 (just below
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* flash). The existing relocation code in boot_ppc_start.S handles the
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* hardware CCSRBAR register write when CCSRBAR_DEF != CCSRBAR_PHYS.
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*
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* CCSR is mapped at PA=0xF_EF000000 (36-bit-aliased, PHYS_HIGH=0xF) to
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* match the cw_152_64.dtb soc.ranges entry. A 32-bit alternative
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* (PA=0x0_EF000000) was tested during bring-up but is not selectable
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* in this header. */
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#define CCSRBAR 0xEF000000
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#define CCSRBAR_PHYS_HIGH 0xF
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#define CCSRBAR_NEW_REG 0x00FEF000 /* (PHYS_HIGH << 20) | (CCSRBAR >> 12) */
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#define CCSRBAR_PHYS ((0xFULL << 32) | CCSRBAR)
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#endif
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#ifdef BOARD_CW_VPX3152
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#define DDR_SIZE (4096ULL * 1024ULL * 1024ULL) /* CW VPX3-152: 4 GB (CS0_BNDS=0x000000FF, CS1 disabled) */
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#else
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#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* T2080 RDB / NAII 68PPC2: 8 GB */
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#endif
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#endif
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/* DDR stack configuration - relocate from CPC SRAM after DDR init.
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* Stack must be ABOVE the image load area to avoid being overwritten
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* when the OS image is copied to WOLFBOOT_LOAD_ADDRESS (0x100000).
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* With WOLFBOOT_PARTITION_SIZE=0x800000 the image area ends at 0x900000.
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* Place stack at 16MB to be safely above the image + DTS regions. */
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#define DDR_STACK_SIZE (64 * 1024) /* 64KB stack in DDR */
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#define DDR_STACK_TOP 0x01000000UL /* 16MB - above image area */
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#define DDR_STACK_BASE (DDR_STACK_TOP - DDR_STACK_SIZE)
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/* DDR address where .ramcode is copied before CPC SRAM is released.
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* TLB9 is remapped: VA 0xF8F00000 -> PA DDR_RAMCODE_ADDR so that
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* RAMFUNCTION code continues to work after CPC becomes L2 cache. */
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#define DDR_RAMCODE_ADDR 0x03000000UL /* 48MB into DDR */
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/* Flash base address and size.
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* CW VPX3-152: 256 MB NOR at 0xF_F000_0000
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* Confirmed from U-Boot: IFC CSPR(0)=0xF0000105 (EXT=0xF), AMASK(0)=0xF0000000,
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* LAW0: addr=0xF_F000_0000, size=256MB, target=IFC. */
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#ifdef BOARD_CW_VPX3152
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#define FLASH_BASE_ADDR 0xF0000000UL /* 256MB NOR flash (0xF0000000-0xFFFFFFFF) */
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#define FLASH_BASE_PHYS_HIGH 0xF
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#define FLASH_LAW_SIZE LAW_SIZE_256MB
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#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_256M
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#else
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#define FLASH_BASE_ADDR 0xE8000000UL
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#define FLASH_BASE_PHYS_HIGH 0x0
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#define FLASH_LAW_SIZE LAW_SIZE_128MB
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#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M
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#endif
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#define USE_LONG_JUMP
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#else
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#error Please define TARGET (nxp_t2080, nxp_t1040, nxp_t1024, or nxp_p1021)
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#endif
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/* boot address */
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#ifndef BOOT_ROM_ADDR
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#define BOOT_ROM_ADDR 0xFFFFF000UL
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#endif
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#ifndef BOOT_ROM_SIZE
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#define BOOT_ROM_SIZE (4UL*1024UL)
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#endif
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/* reset vector */
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#define RESET_VECTOR (BOOT_ROM_ADDR + (BOOT_ROM_SIZE - 4))
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/* CCSRBAR */
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#ifndef CCSRBAR_DEF
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#define CCSRBAR_DEF 0xFE000000
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#endif
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#ifndef CCSRBAR
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#define CCSRBAR CCSRBAR_DEF
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#endif
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#ifndef CCSRBAR_PHYS
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#define CCSRBAR_PHYS CCSRBAR
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#endif
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#ifndef CCSRBAR_PHYS_HIGH
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#define CCSRBAR_PHYS_HIGH 0
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#endif
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/* Encoding written into CCSRBAR for the legacy (e500/e500mc) relocation
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* path: PHYS_HIGH in [23:20], PA[35:12] in the low bits. Boards that
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* relocate CCSRBAR but don't use USE_CORENET_INTERFACE need this
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* pre-computed because GAS @h/@l can't evaluate the shift/OR. */
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#ifndef CCSRBAR_NEW_REG
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#define CCSRBAR_NEW_REG ((CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12))
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#endif
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/* DDR */
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#ifndef DDR_ADDRESS
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#define DDR_ADDRESS 0x00000000UL
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#endif
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/* L1 */
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#ifndef L1_CACHE_SZ
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#define L1_CACHE_SZ (32 * 1024)
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#endif
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#if defined(CORE_E500) || defined(CORE_E5500)
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/* E500CORERM: 2.12.5.2 MAS Register 1 (MAS1)
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* E5500RM: 2.16.6.2 MAS Register 1 (MAS1) */
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#define BOOKE_PAGESZ_4K 1
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#define BOOKE_PAGESZ_16K 2
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#define BOOKE_PAGESZ_64K 3
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#define BOOKE_PAGESZ_256K 4
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#define BOOKE_PAGESZ_1M 5
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#define BOOKE_PAGESZ_4M 6
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#define BOOKE_PAGESZ_16M 7
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#define BOOKE_PAGESZ_64M 8
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#define BOOKE_PAGESZ_256M 9
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#define BOOKE_PAGESZ_1G 10
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#define BOOKE_PAGESZ_4G 11
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#define MAS1_TSIZE_MASK 0x00000F00
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#define MAS1_TSIZE(x) (((x) << 8) & MAS1_TSIZE_MASK)
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#elif defined(CORE_E6500)
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/* E6500RM: 2.13.10.2 MMU Assist 1 (MAS1)
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* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
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#define BOOKE_PAGESZ_4K 2
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#define BOOKE_PAGESZ_8K 3
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#define BOOKE_PAGESZ_16K 4
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#define BOOKE_PAGESZ_32K 5
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#define BOOKE_PAGESZ_64K 6
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#define BOOKE_PAGESZ_128K 7
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#define BOOKE_PAGESZ_256K 8
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#define BOOKE_PAGESZ_512K 9
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#define BOOKE_PAGESZ_1M 10
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#define BOOKE_PAGESZ_2M 11
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#define BOOKE_PAGESZ_4M 12
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#define BOOKE_PAGESZ_8M 13
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#define BOOKE_PAGESZ_16M 14
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#define BOOKE_PAGESZ_32M 15
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#define BOOKE_PAGESZ_64M 16
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#define BOOKE_PAGESZ_128M 17
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#define BOOKE_PAGESZ_256M 18
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#define BOOKE_PAGESZ_512M 19
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#define BOOKE_PAGESZ_1G 20
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#define BOOKE_PAGESZ_2G 21
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#define BOOKE_PAGESZ_4G 22
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#define MAS1_TSIZE_MASK 0x00000F80
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#define MAS1_TSIZE(x) (((x) << 7) & MAS1_TSIZE_MASK)
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#endif
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#ifdef CORE_E500
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/* PowerPC e500 */
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#define CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */
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/* P1021 LAW - Local Access Window (Memory Map) - RM 2.4 */
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#define LAWBAR_BASE(n) (0xC08 + (n * 0x20))
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#define LAWBAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0))
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#define LAWAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8))
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#define LAWAR_ENABLE (1<<31)
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#define LAWAR_TRGT_ID(id) (id<<20)
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/* P1021 Global Source/Target ID Assignments - RM Table 2-7 */
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#define LAW_TRGT_PCIE2 0x01
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#define LAW_TRGT_PCIE1 0x02
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#define LAW_TRGT_ELBC 0x04 /* eLBC (Enhanced Local Bus Controller) */
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#define LAW_TRGT_DDR 0x0F /* DDR Memory Controller */
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/* P1021 2.4.2 - size is equal to 2^(enum + 1) */
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#define LAW_SIZE_4KB 0x0B
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#define LAW_SIZE_8KB 0x0C
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#define LAW_SIZE_16KB 0x0D
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#define LAW_SIZE_32KB 0x0E
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#define LAW_SIZE_64KB 0x0F
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#define LAW_SIZE_128KB 0x10
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#define LAW_SIZE_256KB 0x11
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#define LAW_SIZE_512KB 0x12
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#define LAW_SIZE_1MB 0x13
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#define LAW_SIZE_2MB 0x14
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#define LAW_SIZE_4MB 0x15
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#define LAW_SIZE_8MB 0x16
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#define LAW_SIZE_16MB 0x17
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#define LAW_SIZE_32MB 0x18
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#define LAW_SIZE_64MB 0x19
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#define LAW_SIZE_128MB 0x1A
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#define LAW_SIZE_256MB 0x1B
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#define LAW_SIZE_512MB 0x1C
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#define LAW_SIZE_1GB 0x1D
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#define LAW_SIZE_2GB 0x1E
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#define LAW_SIZE_4GB 0x1F
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#define LAW_SIZE_8GB 0x20
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#define LAW_SIZE_16GB 0x21
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#define LAW_SIZE_32GB 0x22
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#elif defined(CORE_E6500) || defined(CORE_E5500)
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/* PowerPC e5500/e6500 */
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/* CoreNet on-chip interface between the core cluster and rest of SoC */
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#define USE_CORENET_INTERFACE
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#define HAS_EMBEDDED_HYPERVISOR /* E.HV Supported */
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#define CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */
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/* CoreNet Platform Cache Base */
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#define CPC_BASE (CCSRBAR + 0x10000)
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/* 8.2 CoreNet Platform Cache (CPC) Memory Map */
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#define CPCCSR0 (0x000)
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#define CPCEWCR0 (0x010)
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#define CPCSRCR1 (0x100)
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#define CPCSRCR0 (0x104)
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#define CPCERRDIS (0xE44)
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#define CPCHDBCR0 (0xF00)
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#define CPCCSR0_CPCE (0x80000000 >> 0)
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#define CPCCSR0_CPCPE (0x80000000 >> 1)
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#define CPCCSR0_CPCFI (0x80000000 >> 10)
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#define CPCCSR0_CPCFL (0x80000000 >> 20)
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#define CPCCSR0_CPCLFC (0x80000000 >> 21)
|
|
|
|
#ifdef CORE_E6500
|
|
/* T2080: 2MB CPC, 16 ways, 128KB per way */
|
|
#define CPCSRCR0_SRAMSZ_256 (0x1 << 1) /* ways 14-15, 256KB */
|
|
#define CPCSRCR0_SRAMSZ_512 (0x2 << 1) /* ways 12-15, 512KB */
|
|
#define CPCSRCR0_SRAMSZ_1024 (0x3 << 1) /* ways 8-15, 1MB */
|
|
#define CPCSRCR0_SRAMSZ_2048 (0x4 << 1) /* ways 0-15, 2MB */
|
|
#else /* CORE E5500 */
|
|
#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 6-7 */
|
|
#define CPCSRCR0_SRAMSZ_128 (0x2 << 1) /* ways 4-7 */
|
|
#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 0-7 */
|
|
#endif
|
|
#define CPCSRCR0_SRAMEN (0x1)
|
|
|
|
#define CPCHDBCR0_SPEC_DIS (0x80000000 >> 4)
|
|
|
|
#define CORENET_DCSR_SZ_1G 0x3
|
|
|
|
/* T1024/T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
|
|
#define LAWBAR_BASE(n) (0xC00 + (n * 0x10))
|
|
#define LAWBARH(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0))
|
|
#define LAWBARL(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x4))
|
|
#define LAWAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8))
|
|
|
|
#define LAWAR_ENABLE (1<<31)
|
|
#define LAWAR_TRGT_ID(id) (id<<20)
|
|
|
|
/* T1024/T2080 Global Source/Target ID Assignments - RM Table 2-1 */
|
|
#define LAW_TRGT_PCIE1 0x00
|
|
#define LAW_TRGT_PCIE2 0x01
|
|
#define LAW_TRGT_PCIE3 0x02
|
|
#define LAW_TRGT_PCIE4 0x03
|
|
#define LAW_TRGT_DDR_1 0x10 /* Memory Complex 1 */
|
|
#define LAW_TRGT_DDR_2 0x11
|
|
#define LAW_TRGT_BMAN 0x18 /* Buffer Manager (control) */
|
|
#define LAW_TRGT_DCSR 0x1D /* debug facilities */
|
|
#define LAW_TRGT_CORENET 0x1E /* CCSR */
|
|
#define LAW_TRGT_IFC 0x1F /* Integrated Flash Controller */
|
|
#define LAW_TRGT_QMAN 0x3C /* Queue Manager (control) */
|
|
#define LAW_TRGT_PSRAM 0x4A /* 160 KB Platform SRAM */
|
|
|
|
/* T1024/T2080 2.4.3 - size is equal to 2^(enum + 1) */
|
|
#define LAW_SIZE_4KB 0x0B
|
|
#define LAW_SIZE_8KB 0x0C
|
|
#define LAW_SIZE_16KB 0x0D
|
|
#define LAW_SIZE_32KB 0x0E
|
|
#define LAW_SIZE_64KB 0x0F
|
|
#define LAW_SIZE_128KB 0x10
|
|
#define LAW_SIZE_256KB 0x11
|
|
#define LAW_SIZE_512KB 0x12
|
|
#define LAW_SIZE_1MB 0x13
|
|
#define LAW_SIZE_2MB 0x14
|
|
#define LAW_SIZE_4MB 0x15
|
|
#define LAW_SIZE_8MB 0x16
|
|
#define LAW_SIZE_16MB 0x17
|
|
#define LAW_SIZE_32MB 0x18
|
|
#define LAW_SIZE_64MB 0x19
|
|
#define LAW_SIZE_128MB 0x1A
|
|
#define LAW_SIZE_256MB 0x1B
|
|
#define LAW_SIZE_512MB 0x1C
|
|
#define LAW_SIZE_1GB 0x1D
|
|
#define LAW_SIZE_2GB 0x1E
|
|
#define LAW_SIZE_4GB 0x1F
|
|
#define LAW_SIZE_8GB 0x20
|
|
#define LAW_SIZE_16GB 0x21
|
|
#define LAW_SIZE_32GB 0x22
|
|
#define LAW_SIZE_64GB 0x23
|
|
#define LAW_SIZE_128GB 0x24
|
|
#define LAW_SIZE_256GB 0x25
|
|
#define LAW_SIZE_512GB 0x26
|
|
#define LAW_SIZE_1TB 0x27
|
|
#endif
|
|
|
|
#ifndef CACHE_LINE_SIZE
|
|
#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
|
|
#endif
|
|
|
|
|
|
/* MMU Assist Registers
|
|
* E6500RM 2.13.10
|
|
* E5500RM 2.16.6
|
|
* E500CORERM 2.12.5
|
|
*/
|
|
#define MAS0 0x270
|
|
#define MAS1 0x271
|
|
#define MAS2 0x272
|
|
#define MAS3 0x273
|
|
#define MAS6 0x276
|
|
#define MAS7 0x3B0
|
|
#define MAS8 0x155
|
|
#define MMUCSR0 0x3F4 /* MMU control and status register 0 */
|
|
|
|
#define MAS0_TLBSEL_MSK 0x30000000
|
|
#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
|
|
#define MAS0_ESEL_MSK 0x0FFF0000
|
|
#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
|
|
#define MAS0_NV(x) ((x) & 0x00000FFF)
|
|
|
|
#define MAS1_VALID 0x80000000
|
|
#define MAS1_IPROT 0x40000000 /* can not be invalidated by tlbivax */
|
|
#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
|
|
#define MAS1_TS 0x00001000
|
|
|
|
#define MAS2_EPN 0xFFFFF000 /* Effective page number */
|
|
#define MAS2_X0 0x00000040
|
|
#define MAS2_X1 0x00000020
|
|
#define MAS2_W 0x00000010 /* Write-through */
|
|
#define MAS2_I 0x00000008 /* Caching-inhibited */
|
|
#define MAS2_M 0x00000004 /* Memory coherency required */
|
|
#define MAS2_G 0x00000002 /* Guarded */
|
|
#define MAS2_E 0x00000001 /* Endianness - 0=big, 1=little */
|
|
|
|
#define MAS3_RPN 0xFFFFF000 /* Real page number */
|
|
/* User attribute bits */
|
|
#define MAS3_U0 0x00000200
|
|
#define MAS3_U1 0x00000100
|
|
#define MAS3_U2 0x00000080
|
|
#define MAS3_U3 0x00000040
|
|
#define MAS3_UX 0x00000020
|
|
/* User and supervisor read, write, and execute permission bits */
|
|
#define MAS3_SX 0x00000010
|
|
#define MAS3_UW 0x00000008
|
|
#define MAS3_SW 0x00000004
|
|
#define MAS3_UR 0x00000002
|
|
#define MAS3_SR 0x00000001
|
|
|
|
#define MAS7_RPN 0xFF000000 /* Real page number - upper 8-bits */
|
|
|
|
|
|
/* L1 Cache */
|
|
#define L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
|
|
#define L1CSR2 0x25E /* L1 Data Cache Control and Status Register 2 */
|
|
#define L1CSR0 0x3F2 /* L1 Data */
|
|
#define L1CSR1 0x3F3 /* L1 Instruction */
|
|
|
|
#define L1CSR_CPE 0x00010000 /* cache parity enable */
|
|
#define L1CSR_CLFC 0x00000100 /* cache lock bits flash clear */
|
|
#define L1CSR_CFI 0x00000002 /* cache flash invalidate */
|
|
#define L1CSR_CE 0x00000001 /* cache enable */
|
|
|
|
/* L2 Cache */
|
|
#if defined(CORE_E6500)
|
|
/* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */
|
|
#define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000))
|
|
#define L2PID(n) (0x200 + (n * 0x10)) /* L2 Cache Partitioning ID */
|
|
#define L2PIR(n) (0x208 + (n * 0x10)) /* L2 Cache Partitioning Allocation */
|
|
#define L2PWR(n) (0x20C + (n * 0x10)) /* L2 Cache Partitioning Way */
|
|
|
|
/* MMRs */
|
|
#define L2CSR0 0x000 /* L2 Cache Control and Status 0 */
|
|
#define L2CSR1 0x004 /* L2 Cache Control and Status 1 */
|
|
#define L2CFG0 0x008 /* L2 Cache Configuration */
|
|
#else
|
|
#ifdef CORE_E5500
|
|
/* L2 Cache Control - E5500RM 2.15 L2 Cache Registers */
|
|
#define L2_BASE (CCSRBAR + 0x20000)
|
|
#else
|
|
/* E500 */
|
|
#define L2_BASE (CCSRBAR + 0x20000)
|
|
#define L2CTL 0x000 /* 0xFFE20000 - L2 control register */
|
|
#define L2SRBAR0 0x100 /* 0xFFE20100 - L2 SRAM base address register */
|
|
|
|
#define L2CTL_EN (1 << 31) /* L2 enable */
|
|
#define L2CTL_INV (1 << 30) /* L2 invalidate */
|
|
#define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */
|
|
#define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */
|
|
#endif
|
|
|
|
/* SPR */
|
|
#define L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
|
|
#define L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
|
|
#define L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
|
|
#endif
|
|
|
|
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
|
|
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
|
|
#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
|
|
#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
|
|
#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
|
|
#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
|
|
#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
|
|
#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
|
|
#define L2CSR0_L2REP_MODE 0x00000000 /* L2REP Streaming PLRU w/ Aging (U-Boot/CW default) */
|
|
#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
|
|
#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
|
|
|
|
|
|
#define SCCSRBAR 0x3FE /* Shifted CCSRBAR */
|
|
|
|
#define SPRN_DBSR 0x130 /* Debug Status Register */
|
|
#define SPRN_DEC 0x016 /* Decrement Register */
|
|
|
|
#ifdef CORE_E6500
|
|
#define SPRN_TSR 0x150 /* Timer Status Register (SPR 336) */
|
|
#define SPRN_TCR 0x154 /* Timer Control Register (SPR 340) */
|
|
#define SPRN_DEAR 0x03D /* Data Exception Address Register (SPR 61) */
|
|
#define SPRN_ESR 0x03E /* Exception Syndrome Register (SPR 62) */
|
|
#else
|
|
#define SPRN_TSR 0x3D8 /* Timer Status Register */
|
|
#define SPRN_TCR 0x3DA /* Timer Control Register */
|
|
#define SPRN_DEAR 0x3D5 /* Data Exception Address Register */
|
|
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
|
|
#endif
|
|
|
|
#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
|
|
#define TCR_DIE 0x04000000 /* Decrement Interrupt Enable */
|
|
#define SPRN_MCSR 0x23C /* Machine Check Syndrome Register */
|
|
#define SPRN_PVR 0x11F /* Processor Version */
|
|
#define SPRN_SVR 0x3FF /* System Version */
|
|
#define SPRN_HDBCR0 0x3D0
|
|
#define SPRN_HDBCR1 0x3D1
|
|
#define SPRN_HDBCR2 0x3D2
|
|
#define SPRN_HDBCR7 0x277
|
|
#define SPRN_DBCR0 0x134
|
|
#define SPRN_DBCR1 0x135
|
|
#define SPRN_EPCR 0x133
|
|
#define SPRN_MMUCFG 0x3F7
|
|
|
|
/* Hardware Implementation-Dependent Registers */
|
|
#define SPRN_HID0 0x3F0
|
|
#define HID0_TBEN (1 << 14) /* Time base enable */
|
|
#define HID0_TBCLK (1 << 13) /* select clock: 0=every 8 ccb clocks, 1=rising edge of RTC */
|
|
#define HID0_ENMAS7 (1 << 7) /* Enable hot-wire update of MAS7 register */
|
|
#define HID0_EMCP (1 << 31) /* Enable machine check pin */
|
|
|
|
#define SPRN_HID1 0x3F1
|
|
#define HID1_RFXE (1 << 17) /* Read Fault Exception Enable */
|
|
#define HID1_ASTME (1 << 13) /* Address bus streaming mode */
|
|
#define HID1_ABE (1 << 12) /* Address broadcast enable */
|
|
#define HID1_MBDD (1 << 6) /* optimized sync instruction */
|
|
|
|
|
|
/* Interrupt Vector Offset Register
|
|
* IVOR0..IVOR15 are at SPR 0x190..0x19F (contiguous).
|
|
* IVOR32..IVOR37 are at SPR 0x210..0x215.
|
|
* IVOR38..IVOR42 are at SPR 0x1B0..0x1B4 (NOT 0x216+ -- e6500 layout). */
|
|
#define IVOR(n) (0x190+(n))
|
|
#define IVOR32 0x210
|
|
#define IVOR33 0x211
|
|
#define IVOR34 0x212
|
|
#define IVOR35 0x213
|
|
#define IVOR36 0x214
|
|
#define IVOR37 0x215
|
|
#define IVOR38 0x1B0
|
|
#define IVOR39 0x1B1
|
|
#define IVOR40 0x1B2
|
|
#define IVOR41 0x1B3
|
|
#define IVOR42 0x1B4
|
|
#define IVPR 0x03F /* Interrupt Vector Prefix Register */
|
|
|
|
/* Guest Interrupt Vectors */
|
|
#define GIVOR2 (0x1B8)
|
|
#define GIVOR3 (0x1B9)
|
|
#define GIVOR4 (0x1BA)
|
|
#define GIVOR8 (0x1BB)
|
|
#define GIVOR13 (0x1BC)
|
|
#define GIVOR14 (0x1BD)
|
|
#define GIVOR35 (0x1D1)
|
|
|
|
#define SRR0 0x01A /* Save/Restore Register 0 */
|
|
#define SRR1 0x01B /* Save/Restore Register 1 */
|
|
#define SPRN_MCSRR0 0x23A /* Machine Check Save/Restore Register 0 */
|
|
#define SPRN_MCSRR1 0x23B /* Machine Check Save/Restore Register 1 */
|
|
|
|
#define MSR_DS (1<<4) /* Book E Data address space */
|
|
#define MSR_IS (1<<5) /* Book E Instruction address space */
|
|
#define MSR_RI (1<<1) /* Recoverable Interrupt */
|
|
#define MSR_DE (1<<9) /* Debug Exception Enable */
|
|
#define MSR_ME (1<<12) /* Machine check enable */
|
|
#define MSR_EE (1<<15) /* External Interrupt enable */
|
|
#define MSR_CE (1<<17) /* Critical interrupt enable */
|
|
#define MSR_PR (1<<14) /* User mode (problem state) */
|
|
|
|
/* Branch prediction */
|
|
#define SPRN_BUCSR 0x3F5 /* Branch Control and Status Register */
|
|
#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
|
|
#define BUCSR_LS_EN 0x00400000 /* Link stack enable */
|
|
#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
|
|
#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
|
|
#define BUCSR_ENABLE (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
|
|
|
|
#define SPRN_PID 0x030 /* Process ID */
|
|
#define SPRN_PIR 0x11E /* Processor Identification Register */
|
|
|
|
#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
|
|
#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
|
|
|
|
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
|
|
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
|
|
#define TLBNCFG_NENTRY_MASK 0x00000FFF
|
|
#define TLBIVAX_ALL 4
|
|
#define TLBIVAX_TLB0 0
|
|
|
|
|
|
#define BOOKE_MAS0(tlbsel, esel, nv) \
|
|
(MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
|
|
#define BOOKE_MAS1(v,iprot,tid,ts,tsize) \
|
|
((((v) << 31) & MAS1_VALID) | \
|
|
(((iprot) << 30) & MAS1_IPROT) | \
|
|
(MAS1_TID(tid)) | \
|
|
(((ts) << 12) & MAS1_TS) | \
|
|
(MAS1_TSIZE(tsize)))
|
|
#define BOOKE_MAS2(epn, wimge) \
|
|
(((epn) & MAS2_EPN) | (wimge))
|
|
#define BOOKE_MAS3(rpn, user, perms) \
|
|
(((rpn) & MAS3_RPN) | (user) | (perms))
|
|
#define BOOKE_MAS7(urpn) (urpn)
|
|
|
|
/* Stringification */
|
|
#ifndef WC_STRINGIFY
|
|
#define _WC_STRINGIFY_L2(str) #str
|
|
#define WC_STRINGIFY(str) _WC_STRINGIFY_L2(str)
|
|
#endif
|
|
|
|
#define mtspr(rn, v) __asm__ __volatile__("mtspr " WC_STRINGIFY(rn) ",%0" : : "r" (v))
|
|
#define mfspr(rn) ({ \
|
|
unsigned int rval; \
|
|
__asm__ __volatile__("mfspr %0," WC_STRINGIFY(rn) : "=r" (rval)); rval; \
|
|
})
|
|
|
|
#define mfmsr() ({ \
|
|
unsigned int rval; \
|
|
__asm__ __volatile__("mfmsr %0" : "=r" (rval)); rval; \
|
|
})
|
|
#define mtmsr(v) __asm__ __volatile__("mtmsr %0" : : "r" (v))
|
|
|
|
#ifdef __ASSEMBLER__
|
|
/* Load a 32-bit address into a register. On e6500 (64-bit GPRs) a `lis` with
|
|
* bit 31 set sign-extends into the upper 32 bits and breaks 32-bit accesses,
|
|
* so build the value with li/oris/ori. Shared by boot_ppc_start.S and
|
|
* boot_ppc_mp.S. */
|
|
#ifdef CORE_E6500
|
|
#define LOAD_ADDR32(reg, addr) \
|
|
li reg, 0; \
|
|
oris reg, reg, (addr)@h; \
|
|
ori reg, reg, (addr)@l
|
|
#else
|
|
#define LOAD_ADDR32(reg, addr) \
|
|
lis reg, (addr)@h; \
|
|
ori reg, reg, (addr)@l
|
|
#endif
|
|
#endif /* __ASSEMBLER__ */
|
|
|
|
|
|
#ifndef __ASSEMBLER__
|
|
|
|
#include <stdint.h>
|
|
|
|
/* Clock helpers, defined in nxp_ppc.c (built into the target HAL) when
|
|
* ENABLE_BUS_CLK_CALC is set. Prototyped here so drivers compiled as
|
|
* standalone objects (e.g. hal/nxp_esdhc.c) can use them. */
|
|
#if defined(CORE_E5500) || defined(CORE_E6500)
|
|
uint32_t hal_get_plat_clk(void);
|
|
uint32_t hal_get_bus_clk(void);
|
|
/* The e5500/e6500 time base increments at the platform clock / 16 */
|
|
#define TIMEBASE_CLK_DIV 16
|
|
#define TIMEBASE_HZ (hal_get_plat_clk() / TIMEBASE_CLK_DIV)
|
|
#endif
|
|
|
|
/* The data barrier / coherency safe functions for reading and writing */
|
|
static inline int get8(const volatile unsigned char *addr)
|
|
{
|
|
int ret;
|
|
__asm__ __volatile__(
|
|
"sync;\n"
|
|
"lbz%U1%X1 %0,%1;\n"
|
|
"twi 0,%0,0;\n"
|
|
"isync"
|
|
: "=r" (ret) : "m" (*addr)
|
|
);
|
|
return ret;
|
|
}
|
|
static inline void set8(volatile unsigned char *addr, int val)
|
|
{
|
|
__asm__ __volatile__(
|
|
"stb%U0%X0 %1,%0;\n"
|
|
"eieio"
|
|
: "=m" (*addr) : "r" (val)
|
|
);
|
|
}
|
|
|
|
static inline int get16(const volatile unsigned short *addr)
|
|
{
|
|
int ret;
|
|
__asm__ __volatile__(
|
|
"sync;\n"
|
|
"lhz%U1%X1 %0,%1;\n"
|
|
"twi 0,%0,0;\n"
|
|
"isync"
|
|
: "=r" (ret) : "m" (*addr)
|
|
);
|
|
return ret;
|
|
}
|
|
static inline void set16(volatile unsigned short *addr, int val)
|
|
{
|
|
__asm__ __volatile__(
|
|
"sync;\n"
|
|
"sth%U0%X0 %1,%0"
|
|
: "=m" (*addr) : "r" (val)
|
|
);
|
|
}
|
|
|
|
static inline unsigned int get32(const volatile unsigned int *addr)
|
|
{
|
|
unsigned int ret;
|
|
__asm__ __volatile__(
|
|
"sync;\n"
|
|
"lwz%U1%X1 %0,%1;\n"
|
|
"twi 0,%0,0;\n"
|
|
"isync"
|
|
: "=r" (ret) : "m" (*addr)
|
|
);
|
|
return ret;
|
|
}
|
|
static inline void set32(volatile unsigned int *addr, unsigned int val)
|
|
{
|
|
__asm__ __volatile__(
|
|
"sync;"
|
|
"stw%U0%X0 %1,%0"
|
|
: "=m" (*addr) : "r" (val)
|
|
);
|
|
}
|
|
|
|
/* longcall attribute for functions in .ramcode — callers in .text need
|
|
* indirect calls since .ramcode VMA is ~143MB from .text VMA,
|
|
* exceeding PPC bl +/-32MB range */
|
|
#if defined(__WOLFBOOT) && defined(RAM_CODE) && defined(ARCH_PPC)
|
|
#define LONGCALL_ATTR __attribute__((longcall))
|
|
#else
|
|
#define LONGCALL_ATTR
|
|
#endif
|
|
|
|
/* C version in boot_ppc.c */
|
|
extern void LONGCALL_ATTR set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn,
|
|
uint32_t rpn, uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts,
|
|
uint8_t tsize, uint8_t iprot);
|
|
extern void disable_tlb1(uint8_t esel);
|
|
extern void flush_cache(uint32_t start_addr, uint32_t size);
|
|
extern void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l,
|
|
uint32_t trgt_id, uint32_t law_sz, int reset);
|
|
|
|
/* from hal/nxp_*.c */
|
|
extern void uart_init(void);
|
|
|
|
/* from boot_ppc_start.S */
|
|
extern unsigned long long LONGCALL_ATTR get_ticks(void);
|
|
extern void LONGCALL_ATTR wait_ticks(unsigned long long);
|
|
extern unsigned long get_pc(void);
|
|
extern void relocate_code(uint32_t *dest, uint32_t *src, uint32_t length);
|
|
extern void LONGCALL_ATTR invalidate_dcache(void);
|
|
extern void LONGCALL_ATTR invalidate_icache(void);
|
|
extern void icache_enable(void);
|
|
extern void dcache_enable(void);
|
|
extern void dcache_disable(void);
|
|
|
|
#else
|
|
/* Assembly version */
|
|
#ifdef CORE_E6500
|
|
/* e6500 has 64-bit MAS registers. On 64-bit PPC, lis sign-extends to 64 bits.
|
|
* Any MAS value with bit 31 set (MAS1=0xC..., MAS2/MAS3 high addresses) gets
|
|
* upper 32 bits = 0xFFFFFFFF. Hardware may require reserved upper bits = 0.
|
|
* Use "li 0; oris; ori" pattern for MAS1, MAS2, MAS3 to avoid sign-extension. */
|
|
#define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
|
|
lis reg, BOOKE_MAS0(tlb, esel, 0)@h; \
|
|
ori reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
|
|
mtspr MAS0, reg;\
|
|
li reg, 0; \
|
|
oris reg, reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@h; \
|
|
ori reg, reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@l; \
|
|
mtspr MAS1, reg; \
|
|
li reg, 0; \
|
|
oris reg, reg, BOOKE_MAS2(epn, winge)@h; \
|
|
ori reg, reg, BOOKE_MAS2(epn, winge)@l; \
|
|
mtspr MAS2, reg; \
|
|
li reg, 0; \
|
|
oris reg, reg, BOOKE_MAS3(rpn, 0, perms)@h; \
|
|
ori reg, reg, BOOKE_MAS3(rpn, 0, perms)@l; \
|
|
mtspr MAS3, reg; \
|
|
li reg, 0; \
|
|
oris reg, reg, urpn@h; \
|
|
ori reg, reg, urpn@l; \
|
|
mtspr MAS7, reg; \
|
|
isync; \
|
|
msync; \
|
|
tlbwe; \
|
|
isync;
|
|
#else
|
|
/* e500/e5500 - 32-bit MAS registers */
|
|
#define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
|
|
lis reg, BOOKE_MAS0(tlb, esel, 0)@h; \
|
|
ori reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
|
|
mtspr MAS0, reg;\
|
|
lis reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@h; \
|
|
ori reg, reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@l; \
|
|
mtspr MAS1, reg; \
|
|
lis reg, BOOKE_MAS2(epn, winge)@h; \
|
|
ori reg, reg, BOOKE_MAS2(epn, winge)@l; \
|
|
mtspr MAS2, reg; \
|
|
lis reg, BOOKE_MAS3(rpn, 0, perms)@h; \
|
|
ori reg, reg, BOOKE_MAS3(rpn, 0, perms)@l; \
|
|
mtspr MAS3, reg; \
|
|
lis reg, urpn@h; \
|
|
ori reg, reg, urpn@l; \
|
|
mtspr MAS7, reg; \
|
|
isync; \
|
|
msync; \
|
|
tlbwe; \
|
|
isync;
|
|
#endif /* CORE_E6500 */
|
|
|
|
/* readability helpers for assembly to show register versus decimal */
|
|
#define r0 0
|
|
#define r1 1
|
|
#define r2 2
|
|
#define r3 3
|
|
#define r4 4
|
|
#define r5 5
|
|
#define r6 6
|
|
#define r7 7
|
|
#define r8 8
|
|
#define r9 9
|
|
#define r10 10
|
|
#define r11 11
|
|
#define r12 12
|
|
#define r13 13
|
|
#define r14 14
|
|
|
|
#define r15 15
|
|
#define r16 16
|
|
#define r17 17
|
|
#define r18 18
|
|
#define r19 19
|
|
#define r20 20
|
|
#define r21 21
|
|
#define r22 22
|
|
#define r23 23
|
|
|
|
#define r25 25
|
|
#define r26 26
|
|
#define r27 27
|
|
#define r28 28
|
|
#define r29 29
|
|
#define r30 30
|
|
#define r31 31
|
|
#endif
|
|
|
|
/* ePAPR 1.1 spin table */
|
|
/* For multiple core spin table communication */
|
|
/* The spin table must be WING 0b001x (memory-coherence required) */
|
|
/* For older PPC compat use dcbf to flush spin table entry */
|
|
/* Note: spin-table must be cache-line aligned in memory */
|
|
#define EPAPR_MAGIC (0x45504150) /* Book III-E CPUs */
|
|
|
|
/* Initial Mapped Area size passed to OS in r7. U-Boot uses 64MB.
|
|
* Override via CFLAGS_EXTRA+=-DWOLFBOOT_BOOTMAPSZ=... */
|
|
#ifndef WOLFBOOT_BOOTMAPSZ
|
|
#define WOLFBOOT_BOOTMAPSZ (64 * 1024 * 1024) /* 64MB */
|
|
#endif
|
|
|
|
/* Maximum DTS size for flush_cache before OS jump */
|
|
#ifndef WOLFBOOT_DTS_MAX_SIZE
|
|
#define WOLFBOOT_DTS_MAX_SIZE (64 * 1024) /* 64KB */
|
|
#endif
|
|
#define ENTRY_ADDR_UPPER 0
|
|
#define ENTRY_ADDR_LOWER 4
|
|
#define ENTRY_R3_UPPER 8
|
|
#define ENTRY_R3_LOWER 12
|
|
#define ENTRY_RESV 16
|
|
#define ENTRY_PIR 20
|
|
|
|
#define ENTRY_SIZE 64
|
|
|
|
#endif /* !_NXP_PPC_H_ */
|