mirror of https://github.com/wolfSSL/wolfBoot.git
153 lines
6.3 KiB
C
153 lines
6.3 KiB
C
/* renesas-ra.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1335, USA
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*/
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/* Base addresses */
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#define R_SYSTEM_BASE 0x4001E000UL
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#define R_FACI_BASE 0x407FE000UL
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#define R_FCACHE_BASE 0x4001C100UL
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/* Register access macros */
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#define REG8(addr) (*(volatile uint8_t *)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(addr))
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#define REG32(addr) (*(volatile uint32_t *)(addr))
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/* --- FACI HP registers --- */
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/* 0x407FE080: Flash Status Register */
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#define FLASH_FSTATR REG32(R_FACI_BASE + 0x80)
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/* 0x407FE084: P/E Mode Entry Register */
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#define FLASH_FENTRYR REG16(R_FACI_BASE + 0x84)
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/* 0x407FE030: Flash Start Address Register */
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#define FLASH_FSADDR REG32(R_FACI_BASE + 0x30)
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/* 0x407FE01C: Flash Reset Register */
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#define FLASH_FRESETR REG8 (R_FACI_BASE + 0x1C)
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/* --- System register --- */
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/* 0x4001E416: Flash Write/Erase Protect Register */
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#define FLASH_FWEPROR REG8(R_SYSTEM_BASE + 0x416)
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#define FLASH_FWEPROR_FLWE (1 << 0) /* 1 = P/E enabled */
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#define FLASH_FWEPROR_FLWD (1 << 1) /* 1 = P/E disabled */
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/* --- FACI command issuing area (code flash) --- */
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#define FACI_CMD_AREA 0x407E0000UL
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#define FACI_CMD8 (*(volatile uint8_t *)FACI_CMD_AREA)
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#define FACI_CMD16 (*(volatile uint16_t *)FACI_CMD_AREA)
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/* --- FACI command bytes --- */
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#define FACI_CMD_PROGRAM 0xE8 /* Program (128-byte unit) */
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#define FACI_CMD_PROGRAM_LEN 0x40 /* 64 words = 128 bytes */
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#define FACI_CMD_BLOCK_ERASE 0x20 /* Block erase */
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#define FACI_CMD_EXECUTE 0xD0 /* Execute */
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#define FACI_CMD_STATUS_CLR 0x50 /* Clear status */
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#define FACI_CMD_FORCED_STOP 0xB3 /* Forced stop / cancel */
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/* Minimum program unit: bytes per write operation */
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#define FACI_PROG_UNIT 128
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/* --- FSTATR status flags --- */
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#define FLASH_FSTATR_FLWEERR (1 << 6) /* P/E Protect Error */
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#define FLASH_FSTATR_PRGSPD (1 << 8) /* Program Suspend */
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#define FLASH_FSTATR_ERSSPD (1 << 9) /* Erase Suspend */
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#define FLASH_FSTATR_DBFULL (1 << 10) /* Data Buffer Full */
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#define FLASH_FSTATR_SUSRDY (1 << 11) /* Suspend Ready */
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#define FLASH_FSTATR_PRGERR (1 << 12) /* Program Error */
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#define FLASH_FSTATR_ERSERR (1 << 13) /* Erase Error */
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#define FLASH_FSTATR_ILGLERR (1 << 14) /* Illegal Error */
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#define FLASH_FSTATR_FRDY (1 << 15) /* Flash Ready */
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#define FLASH_FSTATR_OTERR (1 << 20) /* Other Error */
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#define FLASH_FSTATR_SECERR (1 << 21) /* Security Error */
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#define FLASH_FSTATR_FESETERR (1 << 22) /* FENTRY Setting Error */
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#define FLASH_FSTATR_ILGCOMERR (1 << 23) /* Illegal Command Err */
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/* 0x407FE0E4: Flash Sequencer Processing Clock Frequency Notification */
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#define FLASH_FPCKAR REG16(R_FACI_BASE + 0xE4)
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/* KEY must be written as 0x1E in bits[15:8] to enable the PCKA write.
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* PCKA[7:0] = PCLKA frequency in MHz, minus 1. */
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#define FLASH_FPCKAR_KEY (0x1E00U)
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/* PCLKA frequency for FPCKAR.PCKA (ICLK=200MHz, PCLKA_DIV=/2 -> 100MHz) */
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#ifndef RA_PCLKA
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#define RA_PCLKA 100000000U /* 100 MHz */
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#endif
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#define RA_PCLKA_MHZ (RA_PCLKA / 1000000U)
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/* --- FENTRYR constants --- */
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/* Upper byte must be 0xAA on write */
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#define FLASH_FENTRYR_KEY (0xAA00)
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#define FLASH_FENTRYR_CODE_READ (0)
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#define FLASH_FENTRYR_CODE_PR (1 << 0) /* Code Flash P/E mode */
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/* 0x407FE044: Flash P/E Mode Entry Protection Register
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* CEPROT bit0=1 silently blocks FENTRYR writes (P/E mode cannot be entered).
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* KEY=0xD9 must be written in bits[15:8] simultaneously with CEPROT.
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* Write FMEPROT_KEY|0 to clear CEPROT before entering P/E mode. */
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#define FLASH_FMEPROT REG16(R_FACI_BASE + 0x44)
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#define FLASH_FMEPROT_KEY (0xD900U)
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/* UART registers (SCI7: P613=TXD7, P614=RXD7, J23 on EK-RA6M4) */
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#define R_SCI7_BASE 0x40118700UL
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#define SCI_SMR REG8(R_SCI7_BASE + 0x00) /* Serial Mode */
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#define SCI_BRR REG8(R_SCI7_BASE + 0x01) /* Baud Rate */
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#define SCI_SCR REG8(R_SCI7_BASE + 0x02) /* Control */
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#define SCI_TDR REG8(R_SCI7_BASE + 0x03) /* Transmit Data */
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#define SCI_SSR REG8(R_SCI7_BASE + 0x04) /* Status */
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#define SCI_SCMR REG8(R_SCI7_BASE + 0x06) /* */
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#define SCI_SEMR REG8(R_SCI7_BASE + 0x07) /* */
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#define SCI_SCR_TE (1u << 5)
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#define SCI_SCR_RE (1u << 4)
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#define SCI_SSR_TEND (1u << 2)
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#define SCI_SSR_TDRE (1u << 7)
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#define SCI_SEMR_BGDM (1u << 6)
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#define SCI_SEMR_ABCS (1u << 4)
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#define SCI_SCMR_CHR1 (1u << 4)
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#define R_MSTP_MSTPCRB REG32(0x40084004UL)
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#define MSTPCRB_SCI7 (1u << 24) /* MSTPCRB bit24 = SCI7 */
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#define R_PFS_P613 REG32(0x400809B4UL)
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#define R_PFS_P614 REG32(0x400809B8UL)
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#define PFS_PMR (1u << 16)
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#define PFS_PDR (1u << 2)
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#define PFS_PODR (1u << 0)
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#define PFS_PSEL_SCI7 (0x05u << 24) /* PSEL=0x05: SCI1/3/5/7/9 odd channels */
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#define R_PMISC_PWPR REG8(0x40080D03UL)
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#define PWPR_PFSWE (1u << 6)
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#define PWPR_B0WI (1u << 7)
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#ifndef DEBUG_BAUD_RATE
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#define DEBUG_BAUD_RATE 115200U
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#endif
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/* SCI7 on RA6M4 is clocked by PCLKA (not PCLKB).
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* Default EK-RA6M4 FSP config: PLL=200MHz, PCLKA Div/2 = 100MHz. */
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#ifndef RA_PCLKA_SCI
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#define RA_PCLKA_SCI 100000000U /* PCLKA = 100MHz */
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#endif
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/* BRR: BGDM=1, ABCS=1 -> divisor=8. 100MHz/(8*115200)-1 = 107 -> 115741bps */
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#define SCI_BRR_VAL (RA_PCLKA_SCI / (8U * DEBUG_BAUD_RATE) - 1U)
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/* --- Flash error codes (used by flash_check_error) --- */
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typedef enum {
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FLASH_OK = 0,
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FLASH_ERR_ILGL,
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FLASH_ERR_PRG,
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FLASH_ERR_ERS,
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FLASH_ERR_FLWE,
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FLASH_ERR_FESET,
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FLASH_ERR_SEC,
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FLASH_ERR_OT,
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} flash_err_t;
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