mirror of https://github.com/wolfSSL/wolfBoot.git
146 lines
3.9 KiB
C
146 lines
3.9 KiB
C
/* stm32l5.c
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*
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* Test bare-metal application.
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "system.h"
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#include "hal.h"
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#include "uart_drv.h"
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#include "wolfboot/wolfboot.h"
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#include "wolfboot/wc_secure.h"
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#include "target.h"
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#ifdef SECURE_PKCS11
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#include "test_pkcs11.h"
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#include "wcs/user_settings.h"
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#include <wolfssl/wolfcrypt/settings.h>
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#endif
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#define LED_BOOT_PIN (9) /* PA9 - Nucleo - Red Led */
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#define LED_USR_PIN (7) /* PC7 - Nucleo - Green Led */
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#define LED_EXTRA_PIN (7) /* PB7 - Nucleo - Blue Led */
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/*Non-Secure */
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#define RCC_BASE (0x40021000)
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#define PWR_BASE (0x40007000)
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#define GPIOA_BASE 0x42020000
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#define GPIOB_BASE 0x42020400
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#define GPIOC_BASE 0x42020800
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#define GPIOA_MODER (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_PUPDR (*(volatile uint32_t *)(GPIOA_BASE + 0x0C))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOB_MODER (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
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#define GPIOB_PUPDR (*(volatile uint32_t *)(GPIOB_BASE + 0x0C))
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#define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18))
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#define GPIOC_MODER (*(volatile uint32_t *)(GPIOC_BASE + 0x00))
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#define GPIOC_PUPDR (*(volatile uint32_t *)(GPIOC_BASE + 0x0C))
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#define GPIOC_BSRR (*(volatile uint32_t *)(GPIOC_BASE + 0x18))
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#define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x4C ))
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#define GPIOA_AHB2_CLOCK_ER (1 << 0)
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#define GPIOB_AHB2_CLOCK_ER (1 << 1)
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#define GPIOC_AHB2_CLOCK_ER (1 << 2)
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#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
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#define PWR_CR2_IOSV (1 << 9)
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static void boot_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_BOOT_PIN;
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RCC_AHB2_CLOCK_ER|= GPIOA_AHB2_CLOCK_ER;
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/* Delay after an RCC peripheral clock enabling */
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reg = RCC_AHB2_CLOCK_ER;
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PWR_CR2 |= PWR_CR2_IOSV;
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reg = GPIOA_MODER & ~(0x03 << (pin * 2));
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GPIOA_MODER = reg | (1 << (pin * 2));
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GPIOA_PUPDR &= ~(0x03 << (pin * 2));
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GPIOA_BSRR |= (1 << (LED_BOOT_PIN));
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}
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static void boot_led_off(void)
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{
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GPIOA_BSRR |= (1 << (LED_BOOT_PIN + 16));
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}
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void usr_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_USR_PIN;
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RCC_AHB2_CLOCK_ER|= GPIOC_AHB2_CLOCK_ER;
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/* Delay after an RCC peripheral clock enabling */
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reg = RCC_AHB2_CLOCK_ER;
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reg = GPIOC_MODER & ~(0x03 << (pin * 2));
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GPIOC_MODER = reg | (1 << (pin * 2));
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GPIOC_PUPDR &= ~(0x03 << (pin * 2));
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GPIOC_BSRR |= (1 << (LED_USR_PIN));
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}
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void usr_led_off(void)
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{
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GPIOC_BSRR |= (1 << (LED_USR_PIN + 16));
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}
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void extra_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_EXTRA_PIN;
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RCC_AHB2_CLOCK_ER|= GPIOB_AHB2_CLOCK_ER;
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/* Delay after an RCC peripheral clock enabling */
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reg = RCC_AHB2_CLOCK_ER;
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reg = GPIOB_MODER & ~(0x03 << (pin * 2));
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GPIOB_MODER = reg | (1 << (pin * 2));
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GPIOB_PUPDR &= ~(0x03 << (pin * 2));
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GPIOB_BSRR |= (1 << (LED_EXTRA_PIN));
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}
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void extra_led_off(void)
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{
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GPIOB_BSRR |= (1 << (LED_EXTRA_PIN + 16));
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}
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void main(void)
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{
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#ifdef SECURE_PKCS11
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int ret;
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boot_led_on();
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ret = test_pkcs11_start();
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if (ret != PKCS11_TEST_FAIL)
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usr_led_on();
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#endif
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while(1)
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;
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/* Never reached */
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}
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