mirror of https://github.com/wolfSSL/wolfBoot.git
390 lines
18 KiB
C
390 lines
18 KiB
C
/* max32666.h
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*
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* Copyright (C) 2025 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* Hardware register definitions for Analog Devices MAX32665/MAX32666
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* MAX32666: Dual Cortex-M4 @ 96 MHz, 1MB Flash, 560KB SRAM, BLE 5
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*
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* Register offsets verified against MSDK:
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* ~/GitHub/msdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/
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*/
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#ifndef MAX32666_H
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#define MAX32666_H
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#include <stdint.h>
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/* ============== Memory Map ============== */
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#define FLASH_BASE 0x10000000UL
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#define FLASH_SIZE (1024 * 1024) /* 1MB */
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#define FLASH_PAGE_SIZE 8192 /* 8KB page erase */
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#define FLASH_WRITE_SIZE 16 /* 128-bit write unit */
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#define SRAM_BASE 0x20000000UL
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#define SRAM_SIZE (560 * 1024) /* 560KB */
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/* ============== GCR - Global Control Registers ============== */
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/* MSDK: gcr_regs.h */
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#define GCR_BASE 0x40000000UL
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#define GCR_SCON (*(volatile uint32_t *)(GCR_BASE + 0x00UL))
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#define GCR_RSTR0 (*(volatile uint32_t *)(GCR_BASE + 0x04UL))
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#define GCR_CLKCN (*(volatile uint32_t *)(GCR_BASE + 0x08UL))
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#define GCR_PM (*(volatile uint32_t *)(GCR_BASE + 0x0CUL))
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#define GCR_PCKDIV (*(volatile uint32_t *)(GCR_BASE + 0x18UL))
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#define GCR_PERCKCN0 (*(volatile uint32_t *)(GCR_BASE + 0x24UL))
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#define GCR_MEMCKCN (*(volatile uint32_t *)(GCR_BASE + 0x28UL))
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#define GCR_MEMZCN (*(volatile uint32_t *)(GCR_BASE + 0x2CUL))
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#define GCR_SYSST (*(volatile uint32_t *)(GCR_BASE + 0x40UL))
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#define GCR_RSTR1 (*(volatile uint32_t *)(GCR_BASE + 0x44UL))
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#define GCR_PERCKCN1 (*(volatile uint32_t *)(GCR_BASE + 0x48UL))
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#define GCR_EVENTEN (*(volatile uint32_t *)(GCR_BASE + 0x4CUL))
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#define GCR_REVISION (*(volatile uint32_t *)(GCR_BASE + 0x50UL))
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#define GCR_SYSSIE (*(volatile uint32_t *)(GCR_BASE + 0x54UL))
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/* GCR_CLKCN fields (MSDK: CLKCN register) */
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#define GCR_CLKCN_PSC_SHIFT 6 /* Prescaler: bits [8:6] */
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#define GCR_CLKCN_PSC_MASK (0x7UL << 6)
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#define GCR_CLKCN_CLKSEL_SHIFT 9 /* Clock source: bits [11:9] */
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#define GCR_CLKCN_CLKSEL_MASK (0x7UL << 9)
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#define GCR_CLKCN_CKRDY (1UL << 13) /* Clock ready */
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#define GCR_CLKCN_X32M_EN (1UL << 16) /* 32 MHz XTAL enable */
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#define GCR_CLKCN_X32K_EN (1UL << 17) /* 32.768 kHz XTAL enable */
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#define GCR_CLKCN_HIRC_EN (1UL << 18) /* 60 MHz HIRC enable */
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#define GCR_CLKCN_HIRC96M_EN (1UL << 19) /* 96 MHz HIRC enable */
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#define GCR_CLKCN_HIRC8M_EN (1UL << 20) /* 7.3728 MHz HIRC8M enable */
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#define GCR_CLKCN_HIRC8M_VS (1UL << 21) /* HIRC8M valid status */
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#define GCR_CLKCN_X32M_RDY (1UL << 24) /* 32 MHz XTAL ready */
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#define GCR_CLKCN_X32K_RDY (1UL << 25) /* 32.768 kHz XTAL ready */
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#define GCR_CLKCN_HIRC_RDY (1UL << 26) /* 60 MHz HIRC ready */
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#define GCR_CLKCN_HIRC96M_RDY (1UL << 27) /* 96 MHz HIRC ready */
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#define GCR_CLKCN_HIRC8M_RDY (1UL << 28) /* 7.3728 MHz HIRC8M ready */
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/* Clock source selection values for CLKSEL field */
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#define GCR_CLKCN_CLKSEL_HIRC (0UL << 9) /* 60 MHz HIRC */
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#define GCR_CLKCN_CLKSEL_XTAL32M (2UL << 9) /* 32 MHz XTAL */
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#define GCR_CLKCN_CLKSEL_LIRC8 (3UL << 9) /* 8 kHz LIRC */
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#define GCR_CLKCN_CLKSEL_HIRC96 (4UL << 9) /* 96 MHz HIRC */
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#define GCR_CLKCN_CLKSEL_HIRC8 (5UL << 9) /* 7.3728 MHz HIRC8M */
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#define GCR_CLKCN_CLKSEL_XTAL32K (6UL << 9) /* 32.768 kHz XTAL */
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/* GCR_PERCKCN0 bits (1 = clock disabled) - MSDK: PERCKCN0 register */
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#define GCR_PERCKCN0_GPIO0D (1UL << 0)
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#define GCR_PERCKCN0_GPIO1D (1UL << 1)
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#define GCR_PERCKCN0_USBD (1UL << 3)
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#define GCR_PERCKCN0_DMAD (1UL << 5)
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#define GCR_PERCKCN0_SPI1D (1UL << 6)
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#define GCR_PERCKCN0_SPI2D (1UL << 7)
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#define GCR_PERCKCN0_UART0D (1UL << 9)
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#define GCR_PERCKCN0_UART1D (1UL << 10)
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#define GCR_PERCKCN0_I2C0D (1UL << 13)
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#define GCR_PERCKCN0_CRYPTOD (1UL << 14) /* TPU/Crypto engine */
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#define GCR_PERCKCN0_TIMER0D (1UL << 15)
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#define GCR_PERCKCN0_TIMER1D (1UL << 16)
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#define GCR_PERCKCN0_TIMER2D (1UL << 17)
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#define GCR_PERCKCN0_I2C1D (1UL << 28)
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/* GCR_PERCKCN1 bits */
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#define GCR_PERCKCN1_UART2D (1UL << 1)
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#define GCR_PERCKCN1_TRNGD (1UL << 2)
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#define GCR_PERCKCN1_FLCD (1UL << 3)
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#define GCR_PERCKCN1_ICCD (1UL << 11)
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#define GCR_PERCKCN1_WDT0D (1UL << 27)
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#define GCR_PERCKCN1_WDT1D (1UL << 28)
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/* ============== FLC - Flash Controller ============== */
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/* Bank 0: 0x10000000 - 0x1007FFFF (512KB) */
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/* Bank 1: 0x10080000 - 0x100FFFFF (512KB) */
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/* MSDK: flc_regs.h */
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#define FLC0_BASE 0x40029000UL
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#define FLC1_BASE 0x40029400UL
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/* FLC register offsets */
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#define FLC_ADDR_OFF 0x00UL
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#define FLC_CLKDIV_OFF 0x04UL
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#define FLC_CN_OFF 0x08UL
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#define FLC_INTR_OFF 0x024UL
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#define FLC_DATA_OFF 0x030UL /* DATA[0..3] = 128-bit write data */
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/* FLC0 registers */
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#define FLC0_ADDR (*(volatile uint32_t *)(FLC0_BASE + FLC_ADDR_OFF))
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#define FLC0_CLKDIV (*(volatile uint32_t *)(FLC0_BASE + FLC_CLKDIV_OFF))
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#define FLC0_CN (*(volatile uint32_t *)(FLC0_BASE + FLC_CN_OFF))
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#define FLC0_INTR (*(volatile uint32_t *)(FLC0_BASE + FLC_INTR_OFF))
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/* FLC1 registers */
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#define FLC1_ADDR (*(volatile uint32_t *)(FLC1_BASE + FLC_ADDR_OFF))
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#define FLC1_CLKDIV (*(volatile uint32_t *)(FLC1_BASE + FLC_CLKDIV_OFF))
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#define FLC1_CN (*(volatile uint32_t *)(FLC1_BASE + FLC_CN_OFF))
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#define FLC1_INTR (*(volatile uint32_t *)(FLC1_BASE + FLC_INTR_OFF))
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/* FLC_CN (Control) register bits */
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#define FLC_CN_WR (1UL << 0) /* Start write */
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#define FLC_CN_ME (1UL << 1) /* Mass erase */
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#define FLC_CN_PGE (1UL << 2) /* Page erase */
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#define FLC_CN_ERASE_CODE_SHIFT 8 /* Erase code: bits [15:8] */
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#define FLC_CN_ERASE_CODE_MASK (0xFFUL << 8)
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#define FLC_CN_ERASE_CODE_PGE (0x55UL << 8) /* Page erase code */
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#define FLC_CN_ERASE_CODE_ME (0xAAUL << 8) /* Mass erase code */
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#define FLC_CN_PEND (1UL << 24) /* Operation pending */
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#define FLC_CN_UNLOCK_SHIFT 28 /* Unlock: bits [31:28] */
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#define FLC_CN_UNLOCK_MASK (0xFUL << 28)
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#define FLC_CN_UNLOCK_UNLOCKED (0x2UL << 28) /* Unlock value */
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#define FLC_CN_UNLOCK_LOCKED (0x3UL << 28) /* Lock value */
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/* FLC_INTR register bits */
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#define FLC_INTR_DONE (1UL << 0) /* Operation done */
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#define FLC_INTR_AF (1UL << 1) /* Access fault */
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#define FLC_INTR_DONEIE (1UL << 8) /* Done interrupt enable */
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#define FLC_INTR_AFIE (1UL << 9) /* Fault interrupt enable */
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/* FLC clock divider: flash requires 1 MHz clock
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* CLKDIV = SystemClock / 1MHz
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* At 96 MHz: CLKDIV = 96
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*/
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#define FLC_CLKDIV_VALUE 96
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/* ============== ICC - Internal Cache Controller ============== */
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/* MSDK: icc_regs.h */
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#define ICC0_BASE 0x4002A000UL
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#define ICC0_INFO (*(volatile uint32_t *)(ICC0_BASE + 0x0000UL))
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#define ICC0_SZ (*(volatile uint32_t *)(ICC0_BASE + 0x0004UL))
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#define ICC0_CTRL (*(volatile uint32_t *)(ICC0_BASE + 0x0100UL))
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#define ICC0_INVALIDATE (*(volatile uint32_t *)(ICC0_BASE + 0x0700UL))
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#define ICC_CTRL_EN (1UL << 0) /* Cache enable */
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#define ICC_CTRL_RDY (1UL << 16) /* Cache ready */
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/* ============== WDT - Watchdog Timer ============== */
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/* MSDK: wdt_regs.h */
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#define WDT0_BASE 0x40003000UL
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#define WDT0_CTRL (*(volatile uint32_t *)(WDT0_BASE + 0x00UL))
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#define WDT0_RST (*(volatile uint32_t *)(WDT0_BASE + 0x04UL))
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/* WDT_CTRL bits */
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#define WDT_CTRL_INT_PERIOD_SHIFT 0
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#define WDT_CTRL_RST_PERIOD_SHIFT 4
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#define WDT_CTRL_EN (1UL << 8)
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#define WDT_CTRL_INT_FLAG (1UL << 9)
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#define WDT_CTRL_INT_EN (1UL << 10)
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#define WDT_CTRL_RST_EN (1UL << 11)
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#define WDT_CTRL_RST_FLAG (1UL << 31)
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/* WDT reset sequence */
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#define WDT_RST_SEQ1 0x00A5
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#define WDT_RST_SEQ2 0x005A
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/* ============== UART ============== */
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/* MSDK: uart_regs.h */
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#define UART0_BASE 0x40042000UL
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#define UART1_BASE 0x40043000UL
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#define UART2_BASE 0x40044000UL
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/* UART register offsets (verified against MSDK) */
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#define UART_CTRL_OFF 0x00UL
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#define UART_THRESH_CTRL_OFF 0x04UL
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#define UART_STATUS_OFF 0x08UL
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#define UART_INT_EN_OFF 0x0CUL
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#define UART_INT_FL_OFF 0x10UL
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#define UART_BAUD0_OFF 0x14UL
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#define UART_BAUD1_OFF 0x18UL
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#define UART_FIFO_OFF 0x1CUL
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#define UART_DMA_OFF 0x20UL
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#define UART_TX_FIFO_OFF 0x24UL
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/* UART0 registers */
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#define UART0_CTRL (*(volatile uint32_t *)(UART0_BASE + UART_CTRL_OFF))
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#define UART0_STATUS (*(volatile uint32_t *)(UART0_BASE + UART_STATUS_OFF))
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#define UART0_INT_EN (*(volatile uint32_t *)(UART0_BASE + UART_INT_EN_OFF))
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#define UART0_INT_FL (*(volatile uint32_t *)(UART0_BASE + UART_INT_FL_OFF))
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#define UART0_BAUD0 (*(volatile uint32_t *)(UART0_BASE + UART_BAUD0_OFF))
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#define UART0_BAUD1 (*(volatile uint32_t *)(UART0_BASE + UART_BAUD1_OFF))
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#define UART0_FIFO (*(volatile uint32_t *)(UART0_BASE + UART_FIFO_OFF))
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/* UART1 registers */
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#define UART1_CTRL (*(volatile uint32_t *)(UART1_BASE + UART_CTRL_OFF))
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#define UART1_STATUS (*(volatile uint32_t *)(UART1_BASE + UART_STATUS_OFF))
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#define UART1_INT_EN (*(volatile uint32_t *)(UART1_BASE + UART_INT_EN_OFF))
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#define UART1_INT_FL (*(volatile uint32_t *)(UART1_BASE + UART_INT_FL_OFF))
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#define UART1_BAUD0 (*(volatile uint32_t *)(UART1_BASE + UART_BAUD0_OFF))
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#define UART1_BAUD1 (*(volatile uint32_t *)(UART1_BASE + UART_BAUD1_OFF))
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#define UART1_FIFO (*(volatile uint32_t *)(UART1_BASE + UART_FIFO_OFF))
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/* UART_CTRL fields */
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#define UART_CTRL_ENABLE (1UL << 0)
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#define UART_CTRL_PARITY_EN (1UL << 1)
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#define UART_CTRL_TX_FLUSH (1UL << 5)
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#define UART_CTRL_RX_FLUSH (1UL << 6)
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#define UART_CTRL_CHAR_SZ_SHIFT 8 /* Character size: bits [9:8] */
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#define UART_CTRL_CHAR_SZ_8 (3UL << 8) /* 8-bit characters */
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#define UART_CTRL_STOPBITS (1UL << 10) /* 1=2 stop bits */
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#define UART_CTRL_FLOW_CTRL (1UL << 11)
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#define UART_CTRL_CLKSEL (1UL << 15) /* 1=HIRC8M (7.3728MHz) as baud clock */
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/* UART_STATUS fields */
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#define UART_STATUS_TX_BUSY (1UL << 0)
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#define UART_STATUS_RX_BUSY (1UL << 1)
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#define UART_STATUS_RX_EMPTY (1UL << 4) /* RX FIFO empty */
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#define UART_STATUS_RX_FULL (1UL << 5) /* RX FIFO full */
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#define UART_STATUS_TX_EMPTY (1UL << 6) /* TX FIFO empty */
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#define UART_STATUS_TX_FULL (1UL << 7) /* TX FIFO full */
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/* UART_BAUD0 fields */
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#define UART_BAUD0_IBAUD_SHIFT 0 /* Integer baud divisor: bits [11:0] */
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#define UART_BAUD0_IBAUD_MASK (0xFFFUL << 0)
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#define UART_BAUD0_FACTOR_SHIFT 16 /* Baud factor: bits [17:16] */
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#define UART_BAUD0_FACTOR_MASK (0x3UL << 16)
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#define UART_BAUD0_FACTOR_128 (0UL << 16) /* Oversampling 128 */
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#define UART_BAUD0_FACTOR_64 (1UL << 16) /* Oversampling 64 */
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#define UART_BAUD0_FACTOR_32 (2UL << 16) /* Oversampling 32 */
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#define UART_BAUD0_FACTOR_16 (3UL << 16) /* Oversampling 16 */
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/* Baud rate: baud = uart_clk / ((IBAUD + DBAUD/128) * (128 >> FACTOR))
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*
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* Per errata #8, HIRC8M causes a spurious TX pulse.
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* Use PCLK (SYSCLK/2 = 48 MHz) instead.
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*
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* For 115200 with PCLK=48MHz, FACTOR=0 (prescale 128):
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* divisor = 48000000/115200 = 416.667
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* IBAUD = 416/128 = 3, remainder = 416.667 - 3*128 = 32.667
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* DBAUD = 33, adjusted for ME10-650 errata: 33 - 3 = 30
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*/
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#define HIRC8M_FREQ 7372800UL
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#define HIRC96M_FREQ 96000000UL
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#ifndef HIRC_FREQ
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#define HIRC_FREQ 60000000UL
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#endif
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#ifndef UART_BAUDRATE
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#define UART_BAUDRATE 115200
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#endif
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/* Select debug UART instance
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* MAX32666FTHR uses UART1 MAP_B (P1.12 RX, P1.13 TX) through external PICO
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* MAX32666FTHR2 uses UART0 MAP_A (P0.9 TX, P0.10 RX) through onboard DAPLINK
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*/
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#ifndef DEBUG_UART_NUM
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#ifdef MAX32666_FTHR2
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#define DEBUG_UART_NUM 0
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#else
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#define DEBUG_UART_NUM 1
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#endif
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#endif
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#if DEBUG_UART_NUM == 0
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#define DEBUG_UART_CTRL UART0_CTRL
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#define DEBUG_UART_STATUS UART0_STATUS
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#define DEBUG_UART_INT_EN UART0_INT_EN
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#define DEBUG_UART_INT_FL UART0_INT_FL
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#define DEBUG_UART_BAUD0 UART0_BAUD0
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#define DEBUG_UART_BAUD1 UART0_BAUD1
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#define DEBUG_UART_FIFO UART0_FIFO
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#define DEBUG_UART_PCLKDIS GCR_PERCKCN0_UART0D
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#elif DEBUG_UART_NUM == 1
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#define DEBUG_UART_CTRL UART1_CTRL
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#define DEBUG_UART_STATUS UART1_STATUS
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#define DEBUG_UART_INT_EN UART1_INT_EN
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#define DEBUG_UART_INT_FL UART1_INT_FL
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#define DEBUG_UART_BAUD0 UART1_BAUD0
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#define DEBUG_UART_BAUD1 UART1_BAUD1
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#define DEBUG_UART_FIFO UART1_FIFO
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#define DEBUG_UART_PCLKDIS GCR_PERCKCN0_UART1D
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#endif
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/* ============== GPIO ============== */
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/* MSDK: gpio_regs.h */
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#define GPIO0_BASE 0x40008000UL
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#define GPIO1_BASE 0x40009000UL
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/* GPIO register offsets */
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#define GPIO_EN0_OFF 0x00UL /* GPIO function enable (1=GPIO, 0=AF) */
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#define GPIO_EN0_SET_OFF 0x04UL
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#define GPIO_EN0_CLR_OFF 0x08UL
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#define GPIO_OUT_EN_OFF 0x0CUL /* Output enable */
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#define GPIO_OUT_EN_SET_OFF 0x10UL
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#define GPIO_OUT_EN_CLR_OFF 0x14UL
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#define GPIO_OUT_OFF 0x18UL /* Output data */
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#define GPIO_OUT_SET_OFF 0x1CUL
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#define GPIO_OUT_CLR_OFF 0x20UL
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#define GPIO_IN_OFF 0x24UL /* Input data */
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#define GPIO_EN1_OFF 0x68UL /* Alternate function select */
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#define GPIO_EN1_SET_OFF 0x6CUL
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#define GPIO_EN1_CLR_OFF 0x70UL
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#define GPIO_EN2_OFF 0x74UL
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#define GPIO_EN2_SET_OFF 0x78UL
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#define GPIO_EN2_CLR_OFF 0x7CUL
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/* GPIO0 registers */
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#define GPIO0_EN0 (*(volatile uint32_t *)(GPIO0_BASE + GPIO_EN0_OFF))
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#define GPIO0_EN0_SET (*(volatile uint32_t *)(GPIO0_BASE + GPIO_EN0_SET_OFF))
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#define GPIO0_EN0_CLR (*(volatile uint32_t *)(GPIO0_BASE + GPIO_EN0_CLR_OFF))
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#define GPIO0_EN1 (*(volatile uint32_t *)(GPIO0_BASE + GPIO_EN1_OFF))
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#define GPIO0_EN1_SET (*(volatile uint32_t *)(GPIO0_BASE + GPIO_EN1_SET_OFF))
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#define GPIO0_EN1_CLR (*(volatile uint32_t *)(GPIO0_BASE + GPIO_EN1_CLR_OFF))
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#define GPIO0_OUT_EN (*(volatile uint32_t *)(GPIO0_BASE + GPIO_OUT_EN_OFF))
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#define GPIO0_OUT_SET (*(volatile uint32_t *)(GPIO0_BASE + GPIO_OUT_SET_OFF))
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#define GPIO0_OUT_CLR (*(volatile uint32_t *)(GPIO0_BASE + GPIO_OUT_CLR_OFF))
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#define GPIO0_IN (*(volatile uint32_t *)(GPIO0_BASE + GPIO_IN_OFF))
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/* GPIO1 registers */
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#define GPIO1_EN0 (*(volatile uint32_t *)(GPIO1_BASE + GPIO_EN0_OFF))
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#define GPIO1_EN0_SET (*(volatile uint32_t *)(GPIO1_BASE + GPIO_EN0_SET_OFF))
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#define GPIO1_EN0_CLR (*(volatile uint32_t *)(GPIO1_BASE + GPIO_EN0_CLR_OFF))
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#define GPIO1_EN1 (*(volatile uint32_t *)(GPIO1_BASE + GPIO_EN1_OFF))
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#define GPIO1_EN1_SET (*(volatile uint32_t *)(GPIO1_BASE + GPIO_EN1_SET_OFF))
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#define GPIO1_EN1_CLR (*(volatile uint32_t *)(GPIO1_BASE + GPIO_EN1_CLR_OFF))
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#define GPIO1_OUT_EN (*(volatile uint32_t *)(GPIO1_BASE + GPIO_OUT_EN_OFF))
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#define GPIO1_OUT_SET (*(volatile uint32_t *)(GPIO1_BASE + GPIO_OUT_SET_OFF))
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#define GPIO1_OUT_CLR (*(volatile uint32_t *)(GPIO1_BASE + GPIO_OUT_CLR_OFF))
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#define GPIO1_IN (*(volatile uint32_t *)(GPIO1_BASE + GPIO_IN_OFF))
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/* Pin definitions for MAX32666FTHR:
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* UART1 MAP_B: P1.13 = TX, P1.12 = RX (AF3: EN0=1, EN1=1)
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*
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* Pin definitions for MAX32666FTHR2:
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* UART0 MAP_A: P0.9 = TX, P0.10 = RX (AF3: EN0=1, EN1=1)
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*/
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#define UART0A_TX_PIN (1UL << 9) /* P0.9 */
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#define UART0A_RX_PIN (1UL << 10) /* P0.10 */
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#define UART0A_PINS (UART0A_TX_PIN | UART0A_RX_PIN)
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#define UART1B_TX_PIN (1UL << 13) /* P1.13 */
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#define UART1B_RX_PIN (1UL << 12) /* P1.12 */
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#define UART1B_PINS (UART1B_TX_PIN | UART1B_RX_PIN)
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/* ============== ARM Cortex-M4 System Registers ============== */
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#ifndef SCB_BASE
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#define SCB_BASE 0xE000ED00UL
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#endif
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#define SCB_CPUID (*(volatile uint32_t *)(SCB_BASE + 0x00UL))
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#define SCB_ICSR (*(volatile uint32_t *)(SCB_BASE + 0x04UL))
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#define SCB_VTOR (*(volatile uint32_t *)(SCB_BASE + 0x08UL))
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#define SCB_AIRCR (*(volatile uint32_t *)(SCB_BASE + 0x0CUL))
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#define AIRCR_VECTKEY (0x05FAUL << 16)
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#define AIRCR_SYSRESETREQ (1UL << 2)
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/* ============== Function Declarations ============== */
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#ifdef DEBUG_UART
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void uart_init(void);
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void uart_write(const char* buf, unsigned int sz);
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int uart_read(char* c);
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#endif
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#endif /* MAX32666_H */
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