mirror of https://github.com/wolfSSL/wolfBoot.git
224 lines
9.5 KiB
C
224 lines
9.5 KiB
C
/* stm32c5.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* STM32C5 family (e.g. STM32C5A3ZGT6 on NUCLEO-C5A3ZG).
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* Cortex-M33, no TrustZone in this configuration.
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* 1 MB dual-bank flash on the -ZG variant (2 x 512 KB, 8 KB pages).
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* Reference: stm32c5a3xx.h from STM32CubeC5 v2.0.0.
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*
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* Bus base addresses (from PERIPH_BASE 0x40000000):
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* APB2 at 0x40010000 (USART1)
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* AHB1 at 0x40020000 (FLASH controller, ICACHE)
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* AHB2 at 0x42020000 (GPIO)
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* AHB3 at 0x44020000 (PWR, RCC)
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*/
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#ifndef _STM32C5_H_
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#define _STM32C5_H_
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#include <stdint.h>
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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#define ISB() __asm__ volatile ("isb")
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#define DSB() __asm__ volatile ("dsb")
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/* -------- RCC (AHB3 + 0x0C00 = 0x44020C00) -------- */
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#define RCC_BASE (0x44020C00)
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#define RCC_CR1 (*(volatile uint32_t *)(RCC_BASE + 0x000))
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#define RCC_CR1_HSISON (1 << 0)
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#define RCC_CR1_HSIDIV3ON (1 << 1)
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#define RCC_CR1_HSISRDY (1 << 4)
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#define RCC_CR1_HSIDIV3RDY (1 << 5)
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#define RCC_CR1_PSISON (1 << 8)
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#define RCC_CR1_PSISRDY (1 << 12)
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#define RCC_CR1_HSEON (1 << 16)
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#define RCC_CR1_HSERDY (1 << 17)
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#define RCC_CR1_HSEBYP (1 << 18)
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/* PSI configuration register. PSIREFSRC[17:16], PSIREF[22:20] and
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* PSIFREQ[29:28] together pick the PSI source/reference/output.
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*/
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#define RCC_CR2 (*(volatile uint32_t *)(RCC_BASE + 0x004))
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#define RCC_CR2_PSIREFSRC_HSE (0u << 16)
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#define RCC_CR2_PSIREF_48MHZ ((1u << 22) | (1u << 21))
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#define RCC_CR2_PSIFREQ_144MHZ (1u << 28)
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#define RCC_CR2_PSI_FIELDS_MASK ((3u << 16) | (7u << 20) | (3u << 28))
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#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x01C))
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#define RCC_CFGR1_SW_MASK (0x3u << 0)
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#define RCC_CFGR1_SW_HSIDIV3 (0x0u << 0)
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#define RCC_CFGR1_SW_PSIS (0x3u << 0)
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#define RCC_CFGR1_SWS_MASK (0x3u << 3)
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#define RCC_CFGR1_SWS_HSIDIV3 (0x0u << 3)
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#define RCC_CFGR1_SWS_PSIS (0x3u << 3)
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#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x020))
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#define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x088))
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#define RCC_AHB1ENR_FLASHEN (1 << 8)
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#define RCC_AHB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x08C))
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#define RCC_AHB2ENR_GPIOAEN (1 << 0)
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#define RCC_AHB2ENR_GPIOBEN (1 << 1)
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#define RCC_AHB2ENR_GPIOCEN (1 << 2)
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#define RCC_AHB2ENR_GPIODEN (1 << 3)
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#define RCC_AHB2ENR_GPIOGEN (1 << 6)
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#define RCC_AHB4ENR (*(volatile uint32_t *)(RCC_BASE + 0x094))
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#define RCC_APB1LENR (*(volatile uint32_t *)(RCC_BASE + 0x09C))
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#define RCC_APB1LENR_USART2EN (1 << 17)
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x0A4))
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x0A8))
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/* -------- FLASH controller (AHB1 + 0x2000 = 0x40022000) -------- */
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#define FLASH_BASE (0x40022000)
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_ACR_LATENCY_MASK (0x0F)
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#define FLASH_ACR_LATENCY_4WS (0x4u)
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#define FLASH_ACR_WRHIGHFREQ_MASK (0x3u << 4)
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#define FLASH_ACR_WRHIGHFREQ_DELAY2 (0x2u << 4)
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x04))
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#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
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#define FLASH_OPSR (*(volatile uint32_t *)(FLASH_BASE + 0x18))
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#define FLASH_OPTCR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
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#define FLASH_CCR (*(volatile uint32_t *)(FLASH_BASE + 0x30))
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#define FLASH_OPTSR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x50))
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#define FLASH_OPTSR_PRG (*(volatile uint32_t *)(FLASH_BASE + 0x54))
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/* OPTSR (current and program) bit defs - bit 31 mirrors OPTCR.SWAP_BANK. */
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#define FLASH_OPTSR_SWAP_BANK (1u << 31)
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/* FLASH_SR bits */
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_WBNE (1 << 1)
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#define FLASH_SR_DBNE (1 << 3)
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#define FLASH_SR_EOP (1 << 16)
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#define FLASH_SR_WRPERR (1 << 17)
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#define FLASH_SR_PGSERR (1 << 18)
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#define FLASH_SR_STRBERR (1 << 19)
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#define FLASH_SR_INCERR (1 << 20)
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#define FLASH_SR_OPTCHANGEERR (1 << 23)
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/* FLASH_CR bits */
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#define FLASH_CR_LOCK (1 << 0)
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#define FLASH_CR_PG (1 << 1)
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#define FLASH_CR_PER (1 << 2)
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#define FLASH_CR_BER (1 << 3)
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#define FLASH_CR_FW (1 << 4)
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#define FLASH_CR_STRT (1 << 5)
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#define FLASH_CR_PNB_SHIFT (6)
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#define FLASH_CR_PNB_MASK (0x3F)
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#define FLASH_CR_MER (1 << 15)
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#define FLASH_CR_BKSEL (1u << 31)
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/* FLASH_OPTCR bits */
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_SWAP_BANK (1u << 31)
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/* FLASH_CCR bits (write 1 to clear corresponding SR flag) */
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#define FLASH_CCR_CLR_EOP (1 << 16)
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#define FLASH_CCR_CLR_WRPERR (1 << 17)
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#define FLASH_CCR_CLR_PGSERR (1 << 18)
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#define FLASH_CCR_CLR_STRBERR (1 << 19)
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#define FLASH_CCR_CLR_INCERR (1 << 20)
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#define FLASH_CCR_CLR_OPTCHANGEERR (1 << 23)
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#define FLASHMEM_ADDRESS_SPACE (0x08000000)
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#define FLASH_PAGE_SIZE (0x2000) /* 8 KB */
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#define FLASH_BANK2_BASE (0x08080000) /* 512 KB bank size, 1 MB total */
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#define FLASH_TOP (0x080FFFFF) /* end of 1 MB */
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/* Bootloader region length, derived from the partition layout. Used by
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* fork_bootloader() to mirror wolfBoot into bank 2 for DUALBANK_SWAP.
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*/
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#define BOOTLOADER_SIZE (WOLFBOOT_PARTITION_BOOT_ADDRESS - \
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FLASHMEM_ADDRESS_SPACE)
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#define FLASH_KEY1 (0x45670123)
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#define FLASH_KEY2 (0xCDEF89AB)
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#define FLASH_OPTKEY1 (0x08192A3BU)
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#define FLASH_OPTKEY2 (0x4C5D6E7FU)
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/* -------- GPIO (AHB2 + 0x0000 = 0x42020000) -------- */
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#define GPIOA_BASE (0x42020000)
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#define GPIOB_BASE (0x42020400)
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#define GPIOC_BASE (0x42020800)
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#define GPIOD_BASE (0x42020C00)
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#define GPIOG_BASE (0x42021800)
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#define GPIOA_MODER (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_PUPDR (*(volatile uint32_t *)(GPIOA_BASE + 0x0C))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOA_AFRL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFRH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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#define GPIOG_MODER (*(volatile uint32_t *)(GPIOG_BASE + 0x00))
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#define GPIOG_PUPDR (*(volatile uint32_t *)(GPIOG_BASE + 0x0C))
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#define GPIOG_BSRR (*(volatile uint32_t *)(GPIOG_BASE + 0x18))
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/* -------- USART2 (APB1 + 0x4400 = 0x40004400) -------- */
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#define USART2_BASE (0x40004400U)
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#define USART2_CR1 (*(volatile uint32_t *)(USART2_BASE + 0x00))
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#define USART2_BRR (*(volatile uint32_t *)(USART2_BASE + 0x0C))
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#define USART2_ISR (*(volatile uint32_t *)(USART2_BASE + 0x1C))
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#define USART2_TDR (*(volatile uint32_t *)(USART2_BASE + 0x28))
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#define UART_CR1_UE (1 << 0)
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#define UART_CR1_RE (1 << 2)
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#define UART_CR1_TE (1 << 3)
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#define UART_ISR_TC (1 << 6)
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#define UART_ISR_TXE (1 << 7)
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/* -------- ICACHE (AHB1 + 0x10400 = 0x40030400) -------- */
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#define ICACHE_BASE (0x40030400)
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#define ICACHE_CR (*(volatile uint32_t *)(ICACHE_BASE + 0x00))
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#define ICACHE_CR_WAYSEL (1 << 2)
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#define ICACHE_CR_1WAY 0U
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#define ICACHE_CR_2WAYS ICACHE_CR_WAYSEL
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#define ICACHE_CR_CACHEINV (1 << 1)
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#define ICACHE_CR_CEN (1 << 0)
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#define ICACHE_SR (*(volatile uint32_t *)(ICACHE_BASE + 0x04))
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#define ICACHE_SR_BUSYF (1 << 0)
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#define ICACHE_SR_BSYENDF (1 << 1)
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#define ICACHE_SR_ERRF (1 << 2)
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/* -------- Reset -------- */
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#define AIRCR (*(volatile uint32_t *)(0xE000ED0C))
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#define AIRCR_VKEY (0x05FA << 16)
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#define AIRCR_SYSRESETREQ (1 << 2)
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void hal_cache_invalidate(void);
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void hal_cache_enable(int way);
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void hal_cache_disable(void);
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#endif /* _STM32C5_H_ */
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