mirror of https://github.com/wolfSSL/wolfBoot.git
329 lines
9.2 KiB
C
329 lines
9.2 KiB
C
/* stm32f7.c
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*
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* Test bare-metal application with UART update
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*
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* Copyright (C) 2018 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "system.h"
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#include "wolfboot/wolfboot.h"
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#include "hal.h"
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/* UART module */
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#define UART1_PIN_AF 7
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#define UART1_RX_PIN 10
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#define UART1_TX_PIN 9
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#define UART1 (0x40011000)
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#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x00))
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#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x04))
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#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x0C))
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#define UART1_ISR (*(volatile uint32_t *)(UART1 + 0x1C))
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#define UART1_RDR (*(volatile uint32_t *)(UART1 + 0x24))
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#define UART1_TDR (*(volatile uint32_t *)(UART1 + 0x28))
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR1_SYMBOL_LEN (1 << 28)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_ISR_TX_EMPTY (1 << 7)
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#define UART_ISR_RX_NOTEMPTY (1 << 5)
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#define CLOCK_SPEED (216000000)
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define UART1_APB2_CLOCK_ER (1 << 4)
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#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOA_AHB1_CLOCK_ER (1 << 0)
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#define GPIOD_AHB1_CLOCK_ER (1 << 3)
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#define GPIOA_BASE 0x40020000
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#define GPIOD_BASE 0x40020c00
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#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c))
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#define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
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#define GPIOD_OTYPE (*(volatile uint32_t *)(GPIOD_BASE + 0x04))
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#define GPIOD_OSPD (*(volatile uint32_t *)(GPIOD_BASE + 0x08))
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#define GPIOD_PUPD (*(volatile uint32_t *)(GPIOD_BASE + 0x0c))
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#define GPIOD_ODR (*(volatile uint32_t *)(GPIOD_BASE + 0x14))
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#define GPIOD_BSRR (*(volatile uint32_t *)(GPIOD_BASE + 0x18))
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#define GPIOD_AFL (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
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#define GPIOD_AFH (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
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void hal_erase_bank2(void);
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void uart_write(const char c)
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{
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uint32_t reg;
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do {
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reg = UART1_ISR;
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART1_TDR = c;
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}
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void uart_print(const char *s)
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{
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int i = 0;
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while(s[i])
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uart_write(s[i++]);
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}
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static void uart_pins_setup(void)
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{
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uint32_t reg;
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AHB1_CLOCK_ER |= GPIOA_AHB1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOA_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART1_RX_PIN * 2));
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reg = GPIOA_MODE & ~ (0x03 << (UART1_TX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART1_TX_PIN * 2));
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/* Alternate function: use hi pins (9 and 10) */
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reg = GPIOA_AFH & ~(0xf << ((UART1_TX_PIN - 8) * 4));
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GPIOA_AFH = reg | (UART1_PIN_AF << ((UART1_TX_PIN - 8) * 4));
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reg = GPIOA_AFH & ~(0xf << ((UART1_RX_PIN - 8) * 4));
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GPIOA_AFH = reg | (UART1_PIN_AF << ((UART1_RX_PIN - 8) * 4));
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}
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int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF7 */
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uart_pins_setup();
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/* Turn on the device */
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APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER;
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/* Configure for TX + RX */
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UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
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/* Configure clock */
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UART1_BRR = CLOCK_SPEED / bitrate;
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/* Configure data bits */
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if (data == 8)
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UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART1_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART1_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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case 'E':
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UART1_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits (not supported)*/
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(void)stop;
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/* Turn on uart */
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UART1_CR1 |= UART_CR1_UART_ENABLE;
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return 0;
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}
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char uart_read(void)
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{
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char c;
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volatile uint32_t reg;
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do {
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reg = UART1_ISR;
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} while ((reg & UART_ISR_RX_NOTEMPTY) == 0);
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c = (char)(UART1_RDR & 0xff);
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return c;
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}
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#define MSGSIZE 16
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#define PAGESIZE (256)
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static uint8_t page[PAGESIZE];
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static const char ERR='!';
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static const char START='*';
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static const char UPDATE='U';
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static const char ACK='#';
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static uint8_t msg[MSGSIZE];
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static void ack(uint32_t _off)
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{
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uint8_t *off = (uint8_t *)(&_off);
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int i;
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uart_write(ACK);
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for (i = 0; i < 4; i++) {
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uart_write(off[i]);
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}
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}
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static int check(uint8_t *pkt, int size)
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{
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int i;
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uint16_t c = 0;
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uint16_t c_rx = *((uint16_t *)(pkt + 2));
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uint16_t *p = (uint16_t *)(pkt + 4);
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for (i = 0; i < ((size - 4) >> 1); i++)
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c += p[i];
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if (c == c_rx)
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return 0;
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return -1;
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}
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void uart_update_mgr(void)
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{
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uint32_t tlen = 0;
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volatile uint32_t recv_seq;
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uint32_t r_total = 0;
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uint32_t tot_len = 0;
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uint32_t next_seq = 0;
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uint32_t version = 0;
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uint8_t *v_array = (uint8_t *)&version;
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int i;
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memset(page, 0xFF, PAGESIZE);
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hal_flash_unlock();
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version = wolfBoot_current_firmware_version();
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// if ((version & 0x01) == 0)
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// wolfBoot_success();
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uart_write(START);
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for (i = 3; i >= 0; i--) {
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uart_write(v_array[i]);
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}
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while (1) {
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r_total = 0;
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do {
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while(r_total < 2) {
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msg[r_total++] = uart_read();
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if ((r_total == 2) && ((msg[0] != 0xA5) || msg[1] != 0x5A)) {
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r_total = 0;
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continue;
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}
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}
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msg[r_total++] = uart_read();
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if ((tot_len == 0) && r_total == 2 + sizeof(uint32_t))
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break;
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if ((r_total > 8) && (tot_len <= ((r_total - 8) + next_seq)))
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break;
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} while (r_total < MSGSIZE);
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if (tot_len == 0) {
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tlen = msg[2] + (msg[3] << 8) + (msg[4] << 16) + (msg[5] << 24);
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if (tlen > 2048 * 1024) {
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uart_write(ERR);
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uart_write(ERR);
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uart_write(ERR);
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uart_write(ERR);
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uart_write(START);
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recv_seq = 0;
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tot_len = 0;
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continue;
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}
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tot_len = tlen;
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hal_erase_bank2();
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ack(0);
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continue;
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}
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if (check(msg, r_total) < 0) {
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ack(next_seq);
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continue;
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}
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recv_seq = msg[4] + (msg[5] << 8) + (msg[6] << 16) + (msg[7] << 24);
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if (recv_seq == next_seq)
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{
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int psize = r_total - 8;
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int page_idx = recv_seq % PAGESIZE;
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memcpy(&page[recv_seq % PAGESIZE], msg + 8, psize);
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page_idx += psize;
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if ((page_idx == PAGESIZE) || (next_seq + psize >= tot_len)) {
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uint32_t dst = (0x08120000, recv_seq + psize) - page_idx;
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hal_flash_write(dst, page, PAGESIZE);
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memset(page, 0xFF, PAGESIZE);
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}
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next_seq += psize;
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}
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ack(next_seq);
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if (next_seq >= tot_len) {
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/* Update complete */
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//wolfBoot_update_trigger();
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hal_flash_lock();
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break;
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}
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}
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/* Wait for reboot */
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while(1)
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;
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}
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#define LED_BOOT_PIN (4)
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#define LED_USR_PIN (12)
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static void boot_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_BOOT_PIN;
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AHB1_CLOCK_ER |= GPIOD_AHB1_CLOCK_ER;
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reg = GPIOD_MODE & ~(0x03 << (pin * 2));
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GPIOD_MODE = reg | (1 << (pin * 2));
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reg = GPIOD_PUPD & ~(0x03 << (pin * 2));
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GPIOD_PUPD = reg | (1 << (pin * 2));
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GPIOD_BSRR |= (1 << pin);
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}
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static void boot_led_off(void)
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{
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GPIOD_BSRR |= (1 << (LED_BOOT_PIN + 16));
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}
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void usr_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_USR_PIN;
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AHB1_CLOCK_ER |= GPIOA_AHB1_CLOCK_ER;
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reg = GPIOA_MODE & ~(0x03 << (pin * 2));
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GPIOA_MODE = reg | (1 << (pin * 2));
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reg = GPIOA_PUPD & ~(0x03 << (pin * 2));
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GPIOA_PUPD = reg | (1 << (pin * 2));
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GPIOA_BSRR |= (1 << pin);
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}
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void usr_led_off(void)
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{
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GPIOA_BSRR |= (1 << (LED_USR_PIN + 16));
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}
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void main(void)
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{
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hal_init();
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boot_led_on();
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usr_led_on();
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boot_led_off();
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// usr_led_off();
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uart_setup(115200, 8, 'N', 1);
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uart_update_mgr();
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while(1)
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;
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}
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