mirror of https://github.com/wolfSSL/wolfBoot.git
754 lines
24 KiB
C
754 lines
24 KiB
C
/* nxp_ppc.h
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef _NXP_PPC_H_
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#define _NXP_PPC_H_
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#ifdef PLATFORM_nxp_p1021
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/* NXP P1021 */
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#define CPU_NUMCORES 2
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#define CORE_E500
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#define LAW_MAX_ENTRIES 12
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#define CCSRBAR_DEF (0xFF700000UL) /* P1021RM 4.3 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_1M
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#define DDR_SIZE (512UL * 1024UL * 1024UL)
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#endif
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/* Memory used for transferring blocks to/from NAND.
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* Maps to eLBC FCM internal 8KB region (by hardware) */
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#define FLASH_BASE_ADDR 0xFC000000UL
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#ifdef BUILD_LOADER_STAGE1
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/* First stage loader features */
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#define ENABLE_L2_CACHE
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#define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */
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#define L2SRAM_SIZE (256UL * 1024UL)
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#define INITIAL_SRAM_ADDR L2SRAM_ADDR
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_ELBC
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
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#else
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/* For wolfBoot features */
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#define ENABLE_L1_CACHE
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#define ENABLE_L2_CACHE
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/* Relocate CCSRBAR */
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#define CCSRBAR 0xFFE00000UL
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#define ENABLE_INTERRUPTS
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#endif
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#elif defined(PLATFORM_nxp_t1024)
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/* NXP T1024 */
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#define CORE_E5500
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#define CPU_NUMCORES 2
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#define CORES_PER_CLUSTER 1
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#define LAW_MAX_ENTRIES 16
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#define CCSRBAR_DEF (0xFE000000) /* T1024RM 4.4.1 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
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#define INITIAL_SRAM_ADDR 0xFDFC0000
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_PSRAM
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
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#define ENABLE_L1_CACHE
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#define ENABLE_INTERRUPTS
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#ifdef BUILD_LOADER_STAGE1
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#define ENABLE_L2_CACHE /* setup and enable L2 in first stage only */
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#else
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/* relocate to 64-bit 0xF_ */
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#define CCSRBAR_PHYS_HIGH 0xFULL
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#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
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#endif
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#define DDR_SIZE (2048ULL * 1024ULL * 1024ULL)
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#endif
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#define FLASH_BASE_ADDR 0xEC000000UL
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#define FLASH_BASE_PHYS_HIGH 0xFULL
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#define FLASH_LAW_SIZE LAW_SIZE_64MB
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#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M
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#define USE_LONG_JUMP
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#elif defined(PLATFORM_nxp_t2080)
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/* NXP T0280 */
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#define CORE_E6500
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#define CPU_NUMCORES 4
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#define CORES_PER_CLUSTER 4
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#define LAW_MAX_ENTRIES 32
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#define ENABLE_PPC64
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#define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */
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#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
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/* relocate to 64-bit 0xE_ */
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//#define CCSRBAR_PHYS_HIGH 0xEULL
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//#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
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#define ENABLE_L1_CACHE
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#define ENABLE_L2_CACHE
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#define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */
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#define L2SRAM_SIZE (256UL * 1024UL)
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#define INITIAL_SRAM_ADDR L2SRAM_ADDR
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#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
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#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
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#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
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#define ENABLE_INTERRUPTS
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#define ENABLE_DDR
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#ifndef DDR_SIZE
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#define DDR_SIZE (8192UL * 1024UL * 1024UL)
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#endif
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#define FLASH_BASE_ADDR 0xE8000000UL
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#define FLASH_BASE_PHYS_HIGH 0x0ULL
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#define FLASH_LAW_SIZE LAW_SIZE_128MB
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#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M
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#define USE_LONG_JUMP
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#else
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#error Please define platform PowerPC core version and CCSRBAR
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#endif
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/* boot address */
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#ifndef BOOT_ROM_ADDR
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#define BOOT_ROM_ADDR 0xFFFFF000UL
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#endif
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#ifndef BOOT_ROM_SIZE
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#define BOOT_ROM_SIZE (4UL*1024UL)
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#endif
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/* reset vector */
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#define RESET_VECTOR (BOOT_ROM_ADDR + (BOOT_ROM_SIZE - 4))
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/* CCSRBAR */
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#ifndef CCSRBAR_DEF
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#define CCSRBAR_DEF 0xFE000000UL
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#endif
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#ifndef CCSRBAR
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#define CCSRBAR CCSRBAR_DEF
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#endif
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#ifndef CCSRBAR_PHYS
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#define CCSRBAR_PHYS CCSRBAR
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#endif
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#ifndef CCSRBAR_PHYS_HIGH
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#define CCSRBAR_PHYS_HIGH 0
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#endif
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/* DDR */
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#ifndef DDR_ADDRESS
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#define DDR_ADDRESS 0x00000000UL
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#endif
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/* L1 */
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#ifndef L1_CACHE_SZ
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#define L1_CACHE_SZ (32 * 1024)
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#endif
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#if defined(CORE_E500) || defined(CORE_E5500)
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/* E500CORERM: 2.12.5.2 MAS Register 1 (MAS1)
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* E5500RM: 2.16.6.2 MAS Register 1 (MAS1) */
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#define BOOKE_PAGESZ_4K 1
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#define BOOKE_PAGESZ_16K 2
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#define BOOKE_PAGESZ_64K 3
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#define BOOKE_PAGESZ_256K 4
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#define BOOKE_PAGESZ_1M 5
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#define BOOKE_PAGESZ_4M 6
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#define BOOKE_PAGESZ_16M 7
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#define BOOKE_PAGESZ_64M 8
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#define BOOKE_PAGESZ_256M 9
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#define BOOKE_PAGESZ_1G 10
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#define BOOKE_PAGESZ_4G 11
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#define MAS1_TSIZE_MASK 0x00000F00
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#define MAS1_TSIZE(x) (((x) << 8) & MAS1_TSIZE_MASK)
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#elif defined(CORE_E6500)
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/* E6500RM: 2.13.10.2 MMU Assist 1 (MAS1)
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* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
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#define BOOKE_PAGESZ_4K 2
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#define BOOKE_PAGESZ_8K 3
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#define BOOKE_PAGESZ_16K 4
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#define BOOKE_PAGESZ_32K 5
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#define BOOKE_PAGESZ_64K 6
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#define BOOKE_PAGESZ_128K 7
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#define BOOKE_PAGESZ_256K 8
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#define BOOKE_PAGESZ_512K 9
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#define BOOKE_PAGESZ_1M 10
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#define BOOKE_PAGESZ_2M 11
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#define BOOKE_PAGESZ_4M 12
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#define BOOKE_PAGESZ_8M 13
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#define BOOKE_PAGESZ_16M 14
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#define BOOKE_PAGESZ_32M 15
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#define BOOKE_PAGESZ_64M 16
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#define BOOKE_PAGESZ_128M 17
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#define BOOKE_PAGESZ_256M 18
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#define BOOKE_PAGESZ_512M 19
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#define BOOKE_PAGESZ_1G 20
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#define BOOKE_PAGESZ_2G 21
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#define BOOKE_PAGESZ_4G 22
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#define MAS1_TSIZE_MASK 0x00000F80
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#define MAS1_TSIZE(x) (((x) << 7) & MAS1_TSIZE_MASK)
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#endif
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#ifdef CORE_E500
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/* PowerPC e500 */
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#define CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */
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/* P1021 LAW - Local Access Window (Memory Map) - RM 2.4 */
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#define LAWBAR_BASE(n) (0xC08 + (n * 0x20))
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#define LAWBAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0))
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#define LAWAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8))
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#define LAWAR_ENABLE (1<<31)
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#define LAWAR_TRGT_ID(id) (id<<20)
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/* P1021 Global Source/Target ID Assignments - RM Table 2-7 */
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#define LAW_TRGT_PCIE2 0x01
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#define LAW_TRGT_PCIE1 0x02
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#define LAW_TRGT_ELBC 0x04 /* eLBC (Enhanced Local Bus Controller) */
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#define LAW_TRGT_DDR 0x0F /* DDR Memory Controller */
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/* P1021 2.4.2 - size is equal to 2^(enum + 1) */
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#define LAW_SIZE_4KB 0x0B
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#define LAW_SIZE_8KB 0x0C
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#define LAW_SIZE_16KB 0x0D
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#define LAW_SIZE_32KB 0x0E
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#define LAW_SIZE_64KB 0x0F
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#define LAW_SIZE_128KB 0x10
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#define LAW_SIZE_256KB 0x11
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#define LAW_SIZE_512KB 0x12
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#define LAW_SIZE_1MB 0x13
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#define LAW_SIZE_2MB 0x14
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#define LAW_SIZE_4MB 0x15
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#define LAW_SIZE_8MB 0x16
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#define LAW_SIZE_16MB 0x17
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#define LAW_SIZE_32MB 0x18
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#define LAW_SIZE_64MB 0x19
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#define LAW_SIZE_128MB 0x1A
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#define LAW_SIZE_256MB 0x1B
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#define LAW_SIZE_512MB 0x1C
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#define LAW_SIZE_1GB 0x1D
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#define LAW_SIZE_2GB 0x1E
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#define LAW_SIZE_4GB 0x1F
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#define LAW_SIZE_8GB 0x20
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#define LAW_SIZE_16GB 0x21
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#define LAW_SIZE_32GB 0x22
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#elif defined(CORE_E6500) || defined(CORE_E5500)
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/* PowerPC e5500/e6500 */
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/* CoreNet on-chip interface between the core cluster and rest of SoC */
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#define USE_CORENET_INTERFACE
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#define HAS_EMBEDDED_HYPERVISOR /* E.HV Supported */
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#define CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */
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/* CoreNet Platform Cache Base */
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#define CPC_BASE (CCSRBAR + 0x10000)
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/* 8.2 CoreNet Platform Cache (CPC) Memory Map */
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#define CPCCSR0 (0x000)
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#define CPCSRCR1 (0x100)
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#define CPCSRCR0 (0x104)
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#define CPCHDBCR0 (0xF00)
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#define CPCCSR0_CPCE (0x80000000 >> 0)
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#define CPCCSR0_CPCPE (0x80000000 >> 1)
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#define CPCCSR0_CPCFI (0x80000000 >> 10)
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#define CPCCSR0_CPCLFC (0x80000000 >> 21)
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#define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
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#ifdef CORE_E6500
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#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 14-15 */
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#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
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#define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
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#else /* CORE E5500 */
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#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 6-7 */
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#define CPCSRCR0_SRAMSZ_128 (0x2 << 1) /* ways 4-7 */
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#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 0-7 */
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#endif
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#define CPCSRCR0_SRAMEN (0x1)
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#define CPCHDBCR0_SPEC_DIS (0x80000000 >> 4)
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#define CORENET_DCSR_SZ_1G 0x3
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/* T1024/T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
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#define LAWBAR_BASE(n) (0xC00 + (n * 0x10))
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#define LAWBARH(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0))
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#define LAWBARL(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x4))
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#define LAWAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8))
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#define LAWAR_ENABLE (1<<31)
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#define LAWAR_TRGT_ID(id) (id<<20)
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/* T1024/T2080 Global Source/Target ID Assignments - RM Table 2-1 */
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#define LAW_TRGT_PCIE1 0x00
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#define LAW_TRGT_PCIE2 0x01
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#define LAW_TRGT_PCIE3 0x02
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#define LAW_TRGT_DDR_1 0x10 /* Memory Complex 1 */
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#define LAW_TRGT_DDR_2 0x11
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#define LAW_TRGT_BMAN 0x18 /* Buffer Manager (control) */
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#define LAW_TRGT_DCSR 0x1D /* debug facilities */
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#define LAW_TRGT_CORENET 0x1E /* CCSR */
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#define LAW_TRGT_IFC 0x1F /* Integrated Flash Controller */
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#define LAW_TRGT_QMAN 0x3C /* Queue Manager (control) */
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#define LAW_TRGT_PSRAM 0x4A /* 160 KB Platform SRAM */
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/* T1024/T2080 2.4.3 - size is equal to 2^(enum + 1) */
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#define LAW_SIZE_4KB 0x0B
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#define LAW_SIZE_8KB 0x0C
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#define LAW_SIZE_16KB 0x0D
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#define LAW_SIZE_32KB 0x0E
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#define LAW_SIZE_64KB 0x0F
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#define LAW_SIZE_128KB 0x10
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#define LAW_SIZE_256KB 0x11
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#define LAW_SIZE_512KB 0x12
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#define LAW_SIZE_1MB 0x13
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#define LAW_SIZE_2MB 0x14
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#define LAW_SIZE_4MB 0x15
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#define LAW_SIZE_8MB 0x16
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#define LAW_SIZE_16MB 0x17
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#define LAW_SIZE_32MB 0x18
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#define LAW_SIZE_64MB 0x19
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#define LAW_SIZE_128MB 0x1A
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#define LAW_SIZE_256MB 0x1B
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#define LAW_SIZE_512MB 0x1C
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#define LAW_SIZE_1GB 0x1D
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#define LAW_SIZE_2GB 0x1E
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#define LAW_SIZE_4GB 0x1F
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#define LAW_SIZE_8GB 0x20
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#define LAW_SIZE_16GB 0x21
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#define LAW_SIZE_32GB 0x22
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#define LAW_SIZE_64GB 0x23
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#define LAW_SIZE_128GB 0x24
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#define LAW_SIZE_256GB 0x25
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#define LAW_SIZE_512GB 0x26
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#define LAW_SIZE_1TB 0x27
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#endif
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#ifndef CACHE_LINE_SIZE
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
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#endif
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/* MMU Assist Registers
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* E6500RM 2.13.10
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* E5500RM 2.16.6
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* E500CORERM 2.12.5
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*/
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#define MAS0 0x270
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#define MAS1 0x271
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#define MAS2 0x272
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#define MAS3 0x273
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#define MAS6 0x276
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#define MAS7 0x3B0
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#define MAS8 0x155
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#define MMUCSR0 0x3F4 /* MMU control and status register 0 */
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#define MAS0_TLBSEL_MSK 0x30000000
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#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
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#define MAS0_ESEL_MSK 0x0FFF0000
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#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
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#define MAS0_NV(x) ((x) & 0x00000FFF)
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000 /* can not be invalidated by tlbivax */
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#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
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#define MAS1_TS 0x00001000
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#define MAS2_EPN 0xFFFFF000 /* Effective page number */
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#define MAS2_X0 0x00000040
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#define MAS2_X1 0x00000020
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#define MAS2_W 0x00000010 /* Write-through */
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#define MAS2_I 0x00000008 /* Caching-inhibited */
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#define MAS2_M 0x00000004 /* Memory coherency required */
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#define MAS2_G 0x00000002 /* Guarded */
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#define MAS2_E 0x00000001 /* Endianness - 0=big, 1=little */
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#define MAS3_RPN 0xFFFFF000 /* Real page number */
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/* User attribute bits */
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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/* User and supervisor read, write, and execute permission bits */
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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#define MAS7_RPN 0xFF000000 /* Real page number - upper 8-bits */
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/* L1 Cache */
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#define L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
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#define L1CSR2 0x25E /* L1 Data Cache Control and Status Register 2 */
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#define L1CSR0 0x3F2 /* L1 Data */
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#define L1CSR1 0x3F3 /* L1 Instruction */
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#define L1CSR_CPE 0x00010000 /* cache parity enable */
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#define L1CSR_CLFC 0x00000100 /* cache lock bits flash clear */
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#define L1CSR_CFI 0x00000002 /* cache flash invalidate */
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#define L1CSR_CE 0x00000001 /* cache enable */
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/* L2 Cache */
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#if defined(CORE_E6500)
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/* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */
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#define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000))
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#define L2PID(n) (0x200 + (n * 0x10)) /* L2 Cache Partitioning ID */
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#define L2PIR(n) (0x208 + (n * 0x10)) /* L2 Cache Partitioning Allocation */
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#define L2PWR(n) (0x20C + (n * 0x10)) /* L2 Cache Partitioning Way */
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/* MMRs */
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#define L2CSR0 0x000 /* L2 Cache Control and Status 0 */
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#define L2CSR1 0x004 /* L2 Cache Control and Status 1 */
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#define L2CFG0 0x008 /* L2 Cache Configuration */
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#else
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#ifdef CORE_E5500
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/* L2 Cache Control - E5500RM 2.15 L2 Cache Registers */
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#define L2_BASE (CCSRBAR + 0x20000)
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#else
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/* E500 */
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#define L2_BASE (CCSRBAR + 0x20000)
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#define L2CTL 0x000 /* 0xFFE20000 - L2 control register */
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#define L2SRBAR0 0x100 /* 0xFFE20100 - L2 SRAM base address register */
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#define L2CTL_EN (1 << 31) /* L2 enable */
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#define L2CTL_INV (1 << 30) /* L2 invalidate */
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#define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */
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#define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */
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#endif
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/* SPR */
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#define L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
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#define L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
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#define L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
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#endif
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#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
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#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
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#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
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#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
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#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
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#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
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#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
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#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
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#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
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#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
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#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
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#define SCCSRBAR 0x3FE /* Shifted CCSRBAR */
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#define SPRN_DBSR 0x130 /* Debug Status Register */
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#define SPRN_DEC 0x016 /* Decrement Register */
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#define SPRN_TSR 0x3D8 /* Timer Status Register */
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#define SPRN_TCR 0x3DA /* Timer Control Register */
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#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
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#define TCR_DIE 0x04000000 /* Decrement Interrupt Enable */
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#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
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#define SPRN_MCSR 0x23C /* Machine Check Syndrome Register */
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#define SPRN_PVR 0x11F /* Processor Version */
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#define SPRN_SVR 0x3FF /* System Version */
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#define SPRN_HDBCR0 0x3D0
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/* Hardware Implementation-Dependent Registers */
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#define SPRN_HID0 0x3F0
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#define HID0_TBEN (1 << 14) /* Time base enable */
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#define HID0_ENMAS7 (1 << 7) /* Enable hot-wire update of MAS7 register */
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#define HID0_EMCP (1 << 31) /* Enable machine check pin */
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#define SPRN_HID1 0x3F1
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#define HID1_RFXE (1 << 17) /* Read Fault Exception Enable */
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#define HID1_ASTME (1 << 13) /* Address bus streaming mode */
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#define HID1_ABE (1 << 12) /* Address broadcast enable */
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#define HID1_MBDD (1 << 6) /* optimized sync instruction */
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/* Interrupt Vector Offset Register */
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#define IVOR(n) (0x190+(n))
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#define IVPR 0x03F /* Interrupt Vector Prefix Register */
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/* Guest Interrupt Vectors */
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#define GIVOR2 (0x1B8)
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#define GIVOR3 (0x1B9)
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#define GIVOR4 (0x1BA)
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#define GIVOR8 (0x1BB)
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#define GIVOR13 (0x1BC)
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#define GIVOR14 (0x1BD)
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#define GIVOR35 (0x1D1)
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#define SRR0 0x01A /* Save/Restore Register 0 */
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#define SRR1 0x01B /* Save/Restore Register 1 */
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#define MSR_DS (1<<4) /* Book E Data address space */
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#define MSR_IS (1<<5) /* Book E Instruction address space */
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#define MSR_DE (1<<9) /* Debug Exception Enable */
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#define MSR_ME (1<<12) /* Machine check enable */
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#define MSR_EE (1<<15) /* External Interrupt enable */
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#define MSR_CE (1<<17) /* Critical interrupt enable */
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#define MSR_PR (1<<14) /* User mode (problem state) */
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/* Branch prediction */
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#define SPRN_BUCSR 0x3F5 /* Branch Control and Status Register */
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#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
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#define BUCSR_LS_EN 0x00400000 /* Link stack enable */
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#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
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#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
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#define BUCSR_ENABLE (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
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#define SPRN_PID 0x030 /* Process ID */
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#define SPRN_PIR 0x11E /* Processor Identification Register */
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#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
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#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
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#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
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#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
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#define TLBNCFG_NENTRY_MASK 0x00000FFF
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#define TLBIVAX_ALL 4
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#define TLBIVAX_TLB0 0
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#define BOOKE_MAS0(tlbsel, esel, nv) \
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(MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
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#define BOOKE_MAS1(v,iprot,tid,ts,tsize) \
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((((v) << 31) & MAS1_VALID) | \
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(((iprot) << 30) & MAS1_IPROT) | \
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(MAS1_TID(tid)) | \
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(((ts) << 12) & MAS1_TS) | \
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(MAS1_TSIZE(tsize)))
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#define BOOKE_MAS2(epn, wimge) \
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(((epn) & MAS2_EPN) | (wimge))
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#define BOOKE_MAS3(rpn, user, perms) \
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(((rpn) & MAS3_RPN) | (user) | (perms))
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#define BOOKE_MAS7(urpn) (urpn)
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/* Stringification */
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#ifndef WC_STRINGIFY
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#define _WC_STRINGIFY_L2(str) #str
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#define WC_STRINGIFY(str) _WC_STRINGIFY_L2(str)
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#endif
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#define mtspr(rn, v) __asm__ __volatile__("mtspr " WC_STRINGIFY(rn) ",%0" : : "r" (v))
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#define mfmsr() ({ \
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unsigned int rval; \
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__asm__ __volatile__("mfmsr %0" : "=r" (rval)); rval; \
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})
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#define mtmsr(v) __asm__ __volatile__("mtmsr %0" : : "r" (v))
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#ifndef __ASSEMBLER__
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/* The data barrier / coherency safe functions for reading and writing */
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static inline int get8(const volatile unsigned char *addr)
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{
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int ret;
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__asm__ __volatile__(
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"sync;\n"
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"lbz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync"
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: "=r" (ret) : "m" (*addr)
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);
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return ret;
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}
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static inline void set8(volatile unsigned char *addr, int val)
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{
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__asm__ __volatile__(
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"stb%U0%X0 %1,%0;\n"
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"eieio"
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: "=m" (*addr) : "r" (val)
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);
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}
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static inline int get16(const volatile unsigned short *addr)
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{
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int ret;
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__asm__ __volatile__(
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"sync;\n"
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"lhz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync"
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: "=r" (ret) : "m" (*addr)
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);
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return ret;
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}
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static inline void set16(volatile unsigned short *addr, int val)
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{
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__asm__ __volatile__(
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"sync;\n"
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"sth%U0%X0 %1,%0"
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: "=m" (*addr) : "r" (val)
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);
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}
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static inline unsigned int get32(const volatile unsigned int *addr)
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{
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unsigned int ret;
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__asm__ __volatile__(
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"sync;\n"
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"lwz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync"
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: "=r" (ret) : "m" (*addr)
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);
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return ret;
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}
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static inline void set32(volatile unsigned int *addr, unsigned int val)
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{
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__asm__ __volatile__(
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"sync;"
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"stw%U0%X0 %1,%0"
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: "=m" (*addr) : "r" (val)
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);
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}
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/* C version in boot_ppc.c */
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extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn,
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uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize,
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uint8_t iprot);
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extern void disable_tlb1(uint8_t esel);
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extern void flush_cache(uint32_t start_addr, uint32_t size);
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extern void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l,
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uint32_t trgt_id, uint32_t law_sz, int reset);
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/* from hal/nxp_*.c */
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extern void uart_init(void);
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/* from boot_ppc_start.S */
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extern unsigned long long get_ticks(void);
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extern void wait_ticks(unsigned long long);
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extern unsigned long get_pc(void);
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extern void relocate_code(uint32_t *dest, uint32_t *src, uint32_t length);
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extern void invalidate_dcache(void);
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extern void invalidate_icache(void);
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extern void icache_enable(void);
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extern void dcache_enable(void);
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extern void dcache_disable(void);
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#else
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/* Assembly version */
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#define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
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lis reg, BOOKE_MAS0(tlb, esel, 0)@h; \
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ori reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
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mtspr MAS0, reg;\
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lis reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@h; \
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ori reg, reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@l; \
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mtspr MAS1, reg; \
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lis reg, BOOKE_MAS2(epn, winge)@h; \
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ori reg, reg, BOOKE_MAS2(epn, winge)@l; \
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mtspr MAS2, reg; \
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lis reg, BOOKE_MAS3(rpn, 0, perms)@h; \
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ori reg, reg, BOOKE_MAS3(rpn, 0, perms)@l; \
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mtspr MAS3, reg; \
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lis reg, urpn@h; \
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ori reg, reg, urpn@l; \
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mtspr MAS7, reg; \
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isync; \
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msync; \
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tlbwe; \
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isync;
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/* readability helpers for assembly to show register versus decimal */
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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#endif
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/* ePAPR 1.1 spin table */
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/* For multiple core spin table communication */
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/* The spin table must be WING 0b001x (memory-coherence required) */
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/* For older PPC compat use dcbf to flush spin table entry */
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/* Note: spin-table must be cache-line aligned in memory */
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#define EPAPR_MAGIC (0x45504150) /* Book III-E CPUs */
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#define ENTRY_ADDR_UPPER 0
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#define ENTRY_ADDR_LOWER 4
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#define ENTRY_R3_UPPER 8
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#define ENTRY_R3_LOWER 12
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#define ENTRY_RESV 16
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#define ENTRY_PIR 20
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/* not used for ePAPR 1.1 */
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#define ENTRY_R6_UPPER 24
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#define ENTRY_R6_LOWER 28
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#define ENTRY_SIZE 64
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#endif /* !_NXP_PPC_H_ */
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