mirror of https://github.com/wolfSSL/wolfBoot.git
274 lines
11 KiB
C
274 lines
11 KiB
C
/* stm32l5.h
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef STM32L5_DEF_INCLUDED
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#define STM32L5_DEF_INCLUDED
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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#define ISB() __asm__ volatile ("isb")
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#define DSB() __asm__ volatile ("dsb")
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/* STM32 L5 register configuration */
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/*** RCC ***/
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/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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/*Secure */
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#define RCC_BASE (0x50021000) //RM0438 - Table 4
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#else
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/*Non-Secure */
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#define RCC_BASE (0x40021000) //RM0438 - Table 4
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#endif
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#define FLASH_SECURE_MMAP_BASE (0x0C000000)
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) //RM0438 - Table 77
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#define RCC_CR_PLLRDY (1 << 25) //RM0438 - 9.8.1
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#define RCC_CR_PLLON (1 << 24) //RM0438 - 9.8.1
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#define RCC_CR_HSEBYP (1 << 18) //RM0438 - 9.8.1
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#define RCC_CR_HSERDY (1 << 17) //RM0438 - 9.8.1
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#define RCC_CR_HSEON (1 << 16) //RM0438 - 9.8.1
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#define RCC_CR_HSIRDY (1 << 10) //RM0438 - 9.8.1
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#define RCC_CR_HSION (1 << 8) //RM0438 - 9.8.1
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#define RCC_CR_MSIRANGE_SHIFT (4) //RM0438 - 9.8.1
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#define RCC_CR_MSIRANGE_11 (11)
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#define RCC_CR_MSIRGSEL (1 << 3) //RM0438 - 9.8.1
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#define RCC_CR_MSIPLLEN (1 << 2) //RM0438 - 9.8.1
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#define RCC_CR_MSIRDY (1 << 1) //RM0438 - 9.8.1
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#define RCC_CR_MSION (1 << 0) //RM0438 - 9.8.1
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#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) //RM0438 - Table 77
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/*** APB1&2 PRESCALER ***/
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#define RCC_APB_PRESCALER_DIV_NONE 0x0 // 0xx: HCLK not divided
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#define RCC_APB_PRESCALER_DIV_2 0x4 // 100: HCLK divided by 2
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#define RCC_APB_PRESCALER_DIV_4 0x5 // 101: HCLK divided by 4
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#define RCC_APB_PRESCALER_DIV_8 0x6 // 110: HCLK divided by 8
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#define RCC_APB_PRESCALER_DIV_16 0x7 // 111: HCLK divided by 16
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/*** AHB PRESCALER ***/
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#define RCC_AHB_PRESCALER_DIV_NONE 0x0 // 0xxx: SYSCLK not divided
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#define RCC_AHB_PRESCALER_DIV_2 0x8 // 1000: SYSCLK divided by 2
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#define RCC_AHB_PRESCALER_DIV_4 0x9 // 1001: SYSCLK divided by 4
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#define RCC_AHB_PRESCALER_DIV_8 0xA // 1010: SYSCLK divided by 8
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#define RCC_AHB_PRESCALER_DIV_16 0xB // 1011: SYSCLK divided by 16
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#define RCC_AHB_PRESCALER_DIV_64 0xC // 1100: SYSCLK divided by 64
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#define RCC_AHB_PRESCALER_DIV_128 0xD // 1101: SYSCLK divided by 128
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#define RCC_AHB_PRESCALER_DIV_256 0xE // 1110: SYSCLK divided by 256
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#define RCC_AHB_PRESCALER_DIV_512 0xF // 1111: SYSCLK divided by 512
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#define RCC_CFGR_HPRE_SHIFT (0x04)
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#define RCC_CFGR_PPRE2_SHIFT (0x0B)
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#define RCC_CFGR_PPRE1_SHIFT (0x08)
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#define RCC_CFGR_SW_MSI 0x0
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#define RCC_CFGR_SW_HSI16 0x1
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#define RCC_CFGR_SW_HSE 0x2
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#define RCC_CFGR_SW_PLL 0x3
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#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C)) //RM0438 - Table 77
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#define RCC_PLLCFGR_PLLP_SHIFT (27)
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#define RCC_PLLCFGR_PLLR_SHIFT (25)
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#define RCC_PLLCFGR_PLLREN (1 << 24)
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#define RCC_PLLCFGR_PLLQ_SHIFT (21)
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#define RCC_PLLCFGR_PLLQEN (1 << 20)
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#define RCC_PLLCFGR_PLLN_SHIFT (8)
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#define RCC_PLLCFGR_PLLM_SHIFT (4)
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#define RCC_PLLCFGR_QR_DIV_2 0x0
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#define RCC_PLLCFGR_QR_DIV_4 0x1
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#define RCC_PLLCFGR_QR_DIV_6 0x2
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#define RCC_PLLCFGR_QR_DIV_8 0x3
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#define RCC_PLLCFGR_P_DIV_7 0x0
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#define RCC_PLLCFGR_P_DIV_17 0x1
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#define RCC_PLLCKSELR_PLLSRC_NONE 0x0
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#define RCC_PLLCKSELR_PLLSRC_MSI 0x1
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#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2
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#define RCC_PLLCKSELR_PLLSRC_HSE 0x3
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#define RCC_APB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x58))
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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#define RCC_CCIPR1 (*(volatile uint32_t *)(RCC_BASE + 0x88))
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#define RCC_CCIPR1_LPUART1SEL_SHIFT (10)
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#define RCC_CCIPR1_LPUART1SEL_MASK (0x3)
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#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98))
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#define RCC_CRRCR_HSI48ON (1 << 0)
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#define RCC_CRRCR_HSI48RDY (1 << 1)
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/*** PWR ***/
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/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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/*Secure */
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#define PWR_BASE (0x50007000) //RM0438 - Table 4
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#else
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/*Non-Secure */
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#define PWR_BASE (0x40007000) //RM0438 - Table 4
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#endif
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#define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
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#define PWR_CR1_VOS_SHIFT (9)
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#define PWR_CR1_VOS_0 (0x0)
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#define PWR_CR1_VOS_1 (0x1)
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#define PWR_CR1_VOS_2 (0x2)
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#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
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#define PWR_CR2_IOSV (1 << 9)
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#define PWR_CR3 (*(volatile uint32_t *)(PWR_BASE + 0x08))
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#define PWR_CR3_UCPD_DBDIS (1 << 14)
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#define PWR_CR4 (*(volatile uint32_t *)(PWR_BASE + 0x0C))
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#define PWR_SR1 (*(volatile uint32_t *)(PWR_BASE + 0x10))
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#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x14))
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#define PWR_SR2_VOSF (1 << 10)
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#define SYSCFG_BASE (0x50010000) //RM0438 - Table 4
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/*** FLASH ***/
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#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) //RM0438 - RCC_APB2ENR - SYSCFGEN
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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/*Secure*/
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#define FLASH_BASE (0x50022000) //RM0438 - Table 4
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#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
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#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x24))
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x2C))
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#define FLASH_SECBB1 ((volatile uint32_t *)(FLASH_BASE + 0x80)) /* Array */
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#define FLASH_SECBB2 ((volatile uint32_t *)(FLASH_BASE + 0xA0)) /* Array */
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#define FLASH_SECBB_NREGS 4 /* Array length for the two above */
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#define FLASH_NS_BASE (0x40022000) //RM0438 - Table 4
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#define FLASH_NS_KEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x08))
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#define FLASH_NS_OPTKEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x10))
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#define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x20))
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#define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x28))
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#define TZSC_PRIVCFGR1 *((uint32_t *)(0x50032420))
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#define TZSC_PRIVCFG1_LPUARTPRIV (1 << 21)
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#else
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/* Non-Secure only */
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#define FLASH_BASE (0x40022000) //RM0438 - Table 4
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#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08))
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#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
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#endif
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/* Register values (for both secure and non secure registers) */
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#define FLASH_SR_EOP (1 << 0)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_PROGERR (1 << 3)
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_PGAERR (1 << 5)
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#define FLASH_SR_SIZERR (1 << 6)
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#define FLASH_SR_PGSERR (1 << 7)
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#define FLASH_SR_OPTWERR (1 << 13)
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#define FLASH_SR_BSY (1 << 16)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_MER1 (1 << 2)
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#define FLASH_CR_PNB_SHIFT 3
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#define FLASH_CR_PNB_MASK 0x7F
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#define FLASH_CR_BKER (1 << 11)
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#define FLASH_CR_MER2 (1 << 15)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_OPTSTRT (1 << 17)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_CR_OBL_LAUNCH (1 << 27)
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#define FLASH_CR_INV (1 << 29)
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#define FLASH_CR_OPTLOCK (1 << 30)
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#define FLASH_CR_LOCK (1 << 31)
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_ACR_LATENCY_MASK (0x0F)
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#define FLASH_OPTR (*(volatile uint32_t *)(FLASH_BASE + 0x40))
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#define FLASH_OPTR_DBANK (1 << 22)
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#define FLASH_OPTR_SWAP_BANK (1 << 20)
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#define FLASHMEM_ADDRESS_SPACE (0x08000000)
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#define FLASH_PAGE_SIZE (0x800) /* 2KB */
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#define FLASH_BANK2_BASE (0x08040000) /*!< Base address of Flash Bank2 */
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#define BOOTLOADER_SIZE (0x8000)
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#define FLASH_TOP (0x0807FFFF) /*!< FLASH end address */
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#define FLASH_KEY1 (0x45670123)
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#define FLASH_KEY2 (0xCDEF89AB)
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#define FLASH_OPTKEY1 (0x08192A3BU)
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#define FLASH_OPTKEY2 (0x4C5D6E7FU)
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/* GPIO*/
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#define GPIOA_BASE 0x52020000
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#define GPIOB_BASE 0x52020400
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#define GPIOC_BASE 0x52020800
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#define GPIOD_BASE 0x52020C00
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#define GPIOG_BASE 0x52021800
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#define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x4C ))
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#define GPIOA_AHB2_CLOCK_ER (1 << 0)
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#define GPIOB_AHB2_CLOCK_ER (1 << 1)
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#define GPIOC_AHB2_CLOCK_ER (1 << 2)
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#define GPIOD_AHB2_CLOCK_ER (1 << 3)
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#define GPIOG_AHB2_CLOCK_ER (1 << 6)
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#define TRNG_AHB2_CLOCK_ER (1 << 18)
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#define RCC_APB1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x5C ))
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#define UART1_APB1_CLOCK_ER_VAL (1 << 0)
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#define UART1_PIN_AF 8
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#define UART1_RX_PIN 8
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#define UART1_TX_PIN 7
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#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30))
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#ifdef STM32_DISCOVERY
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#define LED_AHB2_ENABLE (GPIOD_AHB2_CLOCK_ER | GPIOG_AHB2_CLOCK_ER)
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#define LED_BOOT_PIN (12) /* PG12 - Discovery - Green Led */
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#define LED_USR_PIN (3) /* PD3 - Discovery - Red Led */
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#else
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#define LED_AHB2_ENABLE (GPIOA_AHB2_CLOCK_ER | GPIOB_AHB2_CLOCK_ER | \
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GPIOC_AHB2_CLOCK_ER)
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#define LED_BOOT_PIN (9) /* PA9 - Nucleo board - Red Led */
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#define LED_USR_PIN (7) /* PC7 - Nucleo board - Green Led */
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#define LED_EXTRA_PIN (7) /* PB7 - Nucleo board - Blue Led */
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#endif
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#endif /* STM32L5_DEF_INCLUDED */
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