mirror of https://github.com/wolfSSL/wolfBoot.git
149 lines
4.4 KiB
C
149 lines
4.4 KiB
C
/* uart_drv_stm32.c
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*
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* Driver for the back-end of the UART_FLASH module.
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*
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* Example implementation for stm32F4, using UART3.
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*
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* Pinout: RX=PD9, TX=PD8
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*
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* Copyright (C) 2021 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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/* Driver hardcoded to work on UART3 (PD8/PD9) */
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#define UART3 (0x40004800)
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#define UART3_PIN_AF 7
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#define UART3_RX_PIN 9
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#define UART3_TX_PIN 8
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#define UART3_SR (*(volatile uint32_t *)(UART3))
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#define UART3_DR (*(volatile uint32_t *)(UART3 + 0x04))
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#define UART3_BRR (*(volatile uint32_t *)(UART3 + 0x08))
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#define UART3_CR1 (*(volatile uint32_t *)(UART3 + 0x0c))
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#define UART3_CR2 (*(volatile uint32_t *)(UART3 + 0x10))
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#define UART_CR1_UART_ENABLE (1 << 13)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR2_STOPBITS (3 << 12)
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#define UART_SR_TX_EMPTY (1 << 7)
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#define UART_SR_RX_NOTEMPTY (1 << 5)
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#define CLOCK_SPEED (168000000)
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#define APB1_CLOCK_ER (*(volatile uint32_t *)(0x40023840))
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#define UART3_APB1_CLOCK_ER_VAL (1 << 18)
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#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOD_AHB1_CLOCK_ER (1 << 3)
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#define GPIOD_BASE 0x40020c00
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#define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
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#define GPIOD_AFL (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
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#define GPIOD_AFH (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
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#define GPIO_MODE_AF (2)
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static void uart_pins_setup(void)
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{
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uint32_t reg;
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AHB1_CLOCK_ER |= GPIOD_AHB1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOD_MODE & ~ (0x03 << (UART3_RX_PIN * 2));
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GPIOD_MODE = reg | (2 << (UART3_RX_PIN * 2));
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reg = GPIOD_MODE & ~ (0x03 << (UART3_TX_PIN * 2));
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GPIOD_MODE = reg | (2 << (UART3_TX_PIN * 2));
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/* Alternate function: use high pins (8 and 9) */
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reg = GPIOD_AFH & ~(0xf << ((UART3_TX_PIN - 8) * 4));
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GPIOD_AFH = reg | (UART3_PIN_AF << ((UART3_TX_PIN - 8) * 4));
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reg = GPIOD_AFH & ~(0xf << ((UART3_RX_PIN - 8) * 4));
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GPIOD_AFH = reg | (UART3_PIN_AF << ((UART3_RX_PIN - 8) * 4));
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}
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int uart_tx(const uint8_t c)
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{
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uint32_t reg;
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do {
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reg = UART3_SR;
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} while ((reg & UART_SR_TX_EMPTY) == 0);
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UART3_DR = c;
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return 1;
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}
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int uart_rx(uint8_t *c)
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{
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volatile uint32_t reg = UART3_SR;
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if ((reg & UART_SR_RX_NOTEMPTY) != 0) {
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reg = UART3_DR;
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*c = (uint8_t)(reg & 0xff);
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return 1;
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}
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return 0;
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}
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF7 */
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uart_pins_setup();
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/* Turn on the device */
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APB1_CLOCK_ER |= UART3_APB1_CLOCK_ER_VAL;
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UART3_CR1 &= ~(UART_CR1_UART_ENABLE);
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/* Configure for TX + RX */
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UART3_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
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/* Configure clock */
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UART3_BRR = CLOCK_SPEED / bitrate;
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/* Configure data bits */
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if (data == 8)
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UART3_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART3_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART3_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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UART3_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART3_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART3_CR2 & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART3_CR2 = reg & (2 << 12);
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else
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UART3_CR2 = reg;
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/* Turn on uart */
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UART3_CR1 |= UART_CR1_UART_ENABLE;
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return 0;
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}
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