mirror of https://github.com/wolfSSL/wolfBoot.git
159 lines
5.0 KiB
C
159 lines
5.0 KiB
C
/* uart_drv_stm32l5.c
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*
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* Driver for the back-end of the UART_FLASH module.
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*
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* Example implementation for stm32L5 Nucleo
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* using LPUART1 (VCS port through USB).
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*
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "hal/stm32l5.h"
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#define UART1 (0x50008000) /* Using LPUART1 */
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#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x00))
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#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x04))
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#define UART1_CR3 (*(volatile uint32_t *)(UART1 + 0x08))
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#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x0c))
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#define UART1_ISR (*(volatile uint32_t *)(UART1 + 0x1c))
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#define UART1_ICR (*(volatile uint32_t *)(UART1 + 0x20))
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#define UART1_RDR (*(volatile uint32_t *)(UART1 + 0x24))
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#define UART1_TDR (*(volatile uint32_t *)(UART1 + 0x28))
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_OVER8 (1 << 15)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR2_STOPBITS (3 << 12)
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#define UART_CR2_LINEN (1 << 14)
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#define UART_CR2_CLKEN (1 << 11)
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#define UART_CR3_HDSEL (1 << 3)
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#define UART_CR3_SCEN (1 << 5)
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#define UART_CR3_IREN (1 << 1)
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#define UART_ISR_TX_EMPTY (1 << 7)
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#define UART_ISR_RX_NOTEMPTY (1 << 5)
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#define GPIOG_MODE (*(volatile uint32_t *)(GPIOG_BASE + 0x00))
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#define GPIOG_OTYPE (*(volatile uint32_t *)(GPIOG_BASE + 0x04))
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#define GPIOG_OSPD (*(volatile uint32_t *)(GPIOG_BASE + 0x08))
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#define GPIOG_PUPD (*(volatile uint32_t *)(GPIOG_BASE + 0x0c))
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#define GPIOG_ODR (*(volatile uint32_t *)(GPIOG_BASE + 0x14))
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#define GPIOG_BSRR (*(volatile uint32_t *)(GPIOG_BASE + 0x18))
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#define GPIOG_AFL (*(volatile uint32_t *)(GPIOG_BASE + 0x20))
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#define GPIOG_AFH (*(volatile uint32_t *)(GPIOG_BASE + 0x24))
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#define GPIO_MODE_AF (2)
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#define CPU_FREQ (110000000)
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static void uart1_pins_setup(void)
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{
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uint32_t reg;
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/* Set mode = AF */
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reg = GPIOG_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
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GPIOG_MODE = reg | (2 << (UART1_RX_PIN * 2));
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reg = GPIOG_MODE & ~ (0x03 << (UART1_TX_PIN * 2));
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GPIOG_MODE = reg | (2 << (UART1_TX_PIN * 2));
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/* Alternate function: use low pins (2 and 3) */
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reg = GPIOG_AFL & ~(0xf << (UART1_TX_PIN * 4));
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GPIOG_AFL = reg | (UART1_PIN_AF << (UART1_TX_PIN * 4));
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reg = GPIOG_AFH & ~(0xf << ((UART1_RX_PIN - 8) * 4));
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GPIOG_AFH = reg | (UART1_PIN_AF << ((UART1_RX_PIN - 8) * 4));
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}
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF */
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uart1_pins_setup();
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reg = RCC_CCIPR1 & (~ (RCC_CCIPR1_LPUART1SEL_MASK << RCC_CCIPR1_LPUART1SEL_SHIFT));
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RCC_CCIPR1 = reg | (1 << RCC_CCIPR1_LPUART1SEL_SHIFT);
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/* Enable 16-bit oversampling */
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UART1_CR1 &= (~UART_CR1_OVER8);
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/* Configure clock */
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UART1_BRR |= (uint16_t)(CPU_FREQ / bitrate);
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/* Configure data bits */
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if (data == 8)
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UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART1_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART1_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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UART1_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART1_CR2 & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART1_CR2 = reg & (2 << 12);
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else
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UART1_CR2 = reg;
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/* Clear flags for async mode */
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UART1_CR2 &= ~(UART_CR2_LINEN | UART_CR2_CLKEN);
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UART1_CR3 &= ~(UART_CR3_SCEN | UART_CR3_HDSEL | UART_CR3_IREN);
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/* Configure for RX+TX, turn on. */
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UART1_CR1 |= UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE | UART_CR1_UART_ENABLE;
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return 0;
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}
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int uart_tx(const uint8_t c)
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{
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volatile uint32_t reg;
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do {
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reg = UART1_ISR;
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART1_TDR = c;
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return 1;
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}
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int uart_rx(uint8_t *c, int len)
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{
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volatile uint32_t reg;
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int i = 0;
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reg = UART1_ISR;
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if (reg & UART_ISR_RX_NOTEMPTY) {
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*c = (uint8_t)UART1_RDR;
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return 1;
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}
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return 0;
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}
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