mirror of https://github.com/wolfSSL/wolfBoot.git
178 lines
3.8 KiB
C
178 lines
3.8 KiB
C
/* x86_uart.c
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*
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* Implementation of a very basic 8250 UART driver for x86
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <uart_drv.h>
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#include <x86/common.h>
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#ifndef X86_UART_BASE
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#define X86_UART_BASE 0x3f8
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#undef X86_UART_MMIO
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#define X86_UART_REG_WIDTH 1
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#endif
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#define X86_UART_REG(REG) (X86_UART_BASE + (REG*X86_UART_REG_WIDTH))
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#define X86_UART_THR (X86_UART_REG(0))
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#define X86_UART_RBR (X86_UART_REG(0))
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#define X86_UART_DLL (X86_UART_REG(0))
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#define X86_UART_IER (X86_UART_REG(1))
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#define X86_UART_DLH (X86_UART_REG(1))
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#define X86_UART_LCR (X86_UART_REG(3))
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#define X86_UART_LSR (X86_UART_REG(5))
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#define PARITY_ODD 0x01
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#define PARITY_EVEN 0x03
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#define PARITY_NONE 0x0
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#define DATA_5_BIT 0x0
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#define DATA_6_BIT 0x1
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#define DATA_7_BIT 0x2
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#define DATA_8_BIT 0x3
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#define ENABLE_DLA (0x1 << 7)
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#define EMPTY_THR_BIT (0x1 << 5)
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#define LSR_DR_BIT (0x1 << 0)
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#ifdef X86_UART_MMIO
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#if X86_UART_REG_WIDTH != 4
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#error "x86_uart: reg width not supported"
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#endif /* X86_UART_REG_WIDTH != 4 */
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static void write_reg(uint32_t address, uint8_t value)
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{
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mmio_write32(address, value);
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}
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static uint8_t read_reg(uint32_t address)
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{
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uint32_t reg;
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reg = mmio_read32(address);
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return (uint8_t)(reg & 0xff);
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}
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#else
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static void write_reg(uint32_t port, uint8_t value)
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{
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io_write8((uint16_t)port, value);
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}
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static uint8_t read_reg(uint32_t port)
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{
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return io_read8((uint16_t)port);
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}
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#endif /* X86_UART_MMIO */
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static void serial_wait_tx_ready()
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{
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while ((read_reg(X86_UART_LSR) & EMPTY_THR_BIT) == 0)
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{
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}
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}
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/* defaults to 115200 8-N-1 */
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint8_t parity_bits, mode, stops;
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uint16_t divisor;
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switch (parity) {
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case 'O':
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parity_bits = PARITY_ODD;
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break;
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case 'E':
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parity_bits = PARITY_EVEN;
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break;
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case 'N':
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parity_bits = PARITY_NONE;
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break;
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default:
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return -1;
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}
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switch (data) {
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case 5:
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data = DATA_5_BIT;
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break;
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case 6:
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data = DATA_6_BIT;
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break;
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case 7:
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data = DATA_7_BIT;
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break;
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case 8:
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data = DATA_8_BIT;
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break;
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default:
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return -1;
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}
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stops = 0;
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if (stops > 1)
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stops = 0x01;
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if (bitrate == 0)
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return -1;
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divisor = 115200 / bitrate;
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write_reg(X86_UART_LCR, ENABLE_DLA);
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write_reg(X86_UART_DLL, (uint8_t)divisor);
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write_reg(X86_UART_DLH, (uint8_t)(divisor >> 8));
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mode = 0;
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mode |= data;
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mode |= (stop << 2);
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mode |= (parity_bits << 3);
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write_reg(X86_UART_LCR, mode);
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return 0;
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}
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int uart_tx(const uint8_t c)
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{
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serial_wait_tx_ready();
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write_reg(X86_UART_THR, c);
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return 1;
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}
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int uart_rx(uint8_t *c)
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{
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uint8_t lsr;
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lsr = read_reg(X86_UART_LSR);
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if ((lsr & LSR_DR_BIT) == 0)
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return -1;
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*c = read_reg(X86_UART_RBR) & 0xff;
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return 0;
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}
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void uart_write(const char *buf, unsigned int len)
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{
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while (len--) {
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uart_tx(*buf);
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buf++;
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}
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}
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