mirror of https://github.com/wolfSSL/wolfBoot.git
122 lines
3.8 KiB
C
122 lines
3.8 KiB
C
/* pci.h
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef PCI_H
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#define PCI_H
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#include <stdint.h>
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#define PCI_VENDOR_ID_OFFSET 0x00
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#define PCI_DEVICE_ID_OFFSET 0x02
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#define PCI_COMMAND_OFFSET 0x04
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/* Programming interface, Rev. ID and class code */
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#define PCI_RID_CC_OFFSET 0x08
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#define PCI_HEADER_TYPE_OFFSET 0x0E
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#define PCI_BAR0_OFFSET (0x10)
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#define PCI_BAR5_OFFSET 0x24
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#define PCI_BAR_MASK (~0x3)
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#define PCI_INTR_OFFSET 0x3C
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#define PCI_HEADER_TYPE_MULTIFUNC_MASK 0x80
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#define PCI_HEADER_TYPE_TYPE_MASK 0x7F
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#define PCI_HEADER_TYPE_DEVICE 0x0
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#define PCI_HEADER_TYPE_BRIDGE 0x1
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_SUBCLASS_SATA 0x06
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#define PCI_INTERFACE_AHCI 0x01
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#define PCI_PRIMARY_BUS 0x18
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#define PCI_SECONDARY_BUS 0x19
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#define PCI_SUB_SEC_BUS 0x1a
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#define PCI_SUB_LAT_TIME 0x1b
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#define PCI_PREFETCH_BASE_OFF 0x24
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#define PCI_PREFETCH_LIMIT_OFF 0x26
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#define PCI_MMIO_BASE_OFF 0x20
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#define PCI_MMIO_LIMIT_OFF 0x22
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#define PCI_IO_BASE_OFF 0x30
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#define PCI_IO_LIMIT_OFF 0x32
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#define PCI_PWR_MGMT_CTRL_STATUS 0x84
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#define PCI_POWER_STATE_MASK 0x3
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/* Shifts & masks for CONFIG_ADDRESS register */
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#define PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT 31
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#define PCI_CONFIG_ADDRESS_BUS_SHIFT 16
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#define PCI_CONFIG_ADDRESS_DEVICE_SHIFT 11
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#define PCI_CONFIG_ADDRESS_FUNCTION_SHIFT 8
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#define PCI_CONFIG_ADDRESS_OFFSET_MASK 0xFF
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/* COMMAND bits */
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#define PCI_COMMAND_INT_DIS (1 << 10)
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#define PCI_COMMAND_FAST_B2B_EN (1 << 9)
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#define PCI_COMMAND_SERR_EN (1 << 8)
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#define PCI_COMMAND_PE_RESP (1 << 6)
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#define PCI_COMMAND_VGASNOOP (1 << 5)
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#define PCI_COMMAND_MW_INV_EN (1 << 4)
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#define PCI_COMMAND_SPECIAL_CYCLE (1 << 3)
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#define PCI_COMMAND_BUS_MASTER (1 << 2)
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#define PCI_COMMAND_MEM_SPACE (1 << 1)
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#define PCI_COMMAND_IO_SPACE (1 << 0)
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typedef struct {
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int bus;
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int device;
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int function;
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uint32_t device_id;
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} pci_ctrlr_info_t;
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struct pci_enum_info {
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uint32_t mem;
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uint32_t mem_limit;
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uint32_t io;
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uint32_t mem_pf;
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uint32_t mem_pf_limit;
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uint8_t curr_bus_number;
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};
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#ifdef PCH_HAS_PCR
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uint32_t pch_read32(uint8_t port_id, uint16_t offset);
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void pch_write32(uint8_t port_id, uint16_t offset, uint32_t val);
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#endif
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uint32_t pci_config_read32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off);
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void pci_config_write32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off,
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uint32_t value);
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uint16_t pci_config_read16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off);
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void pci_config_write16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off,
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uint16_t value);
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uint8_t pci_config_read8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off);
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void pci_config_write8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off,
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uint8_t value);
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uint64_t pci_get_mmio_addr(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t bar);
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uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info);
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int pci_enum_do(void);
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int pci_pre_enum(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PCI_H */
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