From 4b56cfa313388dc56c0a0a311c0351ce21894be6 Mon Sep 17 00:00:00 2001 From: David Garske Date: Tue, 17 Sep 2024 09:36:18 -0700 Subject: [PATCH] Fix for STM32 GPIO SPI CS control to use pin number as bit offset, not direct. --- hal/tpm_io_st.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hal/tpm_io_st.c b/hal/tpm_io_st.c index 3bedd96..3e3f995 100644 --- a/hal/tpm_io_st.c +++ b/hal/tpm_io_st.c @@ -169,7 +169,7 @@ __HAL_SPI_ENABLE(hspi); #ifndef USE_HW_SPI_CS - HAL_GPIO_WritePin(USE_SPI_CS_PORT, USE_SPI_CS_PIN, GPIO_PIN_RESET); /* active low */ + HAL_GPIO_WritePin(USE_SPI_CS_PORT, (1 << USE_SPI_CS_PIN), GPIO_PIN_RESET); /* active low */ #endif #ifdef WOLFTPM_CHECK_WAIT_STATE @@ -178,7 +178,7 @@ TPM_TIS_HEADER_SZ, STM32_CUBEMX_SPI_TIMEOUT); if (status != HAL_OK) { #ifndef USE_HW_SPI_CS - HAL_GPIO_WritePin(USE_SPI_CS_PORT, USE_SPI_CS_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(USE_SPI_CS_PORT, (1 << USE_SPI_CS_PIN), GPIO_PIN_SET); #endif __HAL_SPI_DISABLE(hspi); return TPM_RC_FAILURE; @@ -198,7 +198,7 @@ #endif if (timeout <= 0) { #ifndef USE_HW_SPI_CS - HAL_GPIO_WritePin(USE_SPI_CS_PORT, USE_SPI_CS_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(USE_SPI_CS_PORT, (1 << USE_SPI_CS_PIN), GPIO_PIN_SET); #endif __HAL_SPI_DISABLE(hspi); return TPM_RC_FAILURE; @@ -217,7 +217,7 @@ #endif /* WOLFTPM_CHECK_WAIT_STATE */ #ifndef USE_HW_SPI_CS - HAL_GPIO_WritePin(USE_SPI_CS_PORT, USE_SPI_CS_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(USE_SPI_CS_PORT, (1 << USE_SPI_CS_PIN), GPIO_PIN_SET); #endif __HAL_SPI_DISABLE(hspi);