From 17ed483f41550eefdfccaa02f630d460bc53c542 Mon Sep 17 00:00:00 2001 From: Anthony Hu Date: Fri, 25 Mar 2022 14:38:15 -0400 Subject: [PATCH] Add the post-quantum TLS 1.3 STM32CubeIDE example project --- pq/README.md | 7 +- pq/stm32/Makefile | 36 ++ pq/stm32/README.md | 145 ++++++ pq/{ => stm32}/client-tls-uart.c | 0 pq/{ => stm32}/server-tls-uart.c | 4 +- pq/stm32/setup_kyber.patch | 24 + pq/stm32/setup_kyber.sh | 83 ++++ pq/stm32/wolfssl_stm32_pq/.cproject | 184 ++++++++ pq/stm32/wolfssl_stm32_pq/.mxproject | 7 + pq/stm32/wolfssl_stm32_pq/.project | 32 ++ pq/stm32/wolfssl_stm32_pq/Core/Inc/main.h | 103 +++++ pq/stm32/wolfssl_stm32_pq/Core/Src/main.c | 432 ++++++++++++++++++ .../wolfssl_stm32_pq/wolfssl_stm32_pq.ioc | 286 ++++++++++++ 13 files changed, 1336 insertions(+), 7 deletions(-) create mode 100644 pq/stm32/Makefile create mode 100644 pq/stm32/README.md rename pq/{ => stm32}/client-tls-uart.c (100%) rename pq/{ => stm32}/server-tls-uart.c (98%) create mode 100644 pq/stm32/setup_kyber.patch create mode 100755 pq/stm32/setup_kyber.sh create mode 100644 pq/stm32/wolfssl_stm32_pq/.cproject create mode 100644 pq/stm32/wolfssl_stm32_pq/.mxproject create mode 100644 pq/stm32/wolfssl_stm32_pq/.project create mode 100644 pq/stm32/wolfssl_stm32_pq/Core/Inc/main.h create mode 100644 pq/stm32/wolfssl_stm32_pq/Core/Src/main.c create mode 100644 pq/stm32/wolfssl_stm32_pq/wolfssl_stm32_pq.ioc diff --git a/pq/README.md b/pq/README.md index 674902bf..88057202 100644 --- a/pq/README.md +++ b/pq/README.md @@ -8,14 +8,11 @@ This directory contains: connection. - A client application that perform a completely quantum-safe TLS 1.3 connection with the server above. +- An STM32CubeIDE project for doing quantum-safe TLS 1.3 connection over UART + and some applications that run on the Linux side to connect with it. # Prerequisites -Support for the quantum-safe signature scheme FALCON is new and has not made it -into a release yet. You can try these examples against the following github PR: - -https://github.com/wolfSSL/wolfssl/pull/4530 - Please see wolfssl/INSTALL for instructions on how to build and install the Open Quantum Safe project's liboqs. For a quick start, you can go into wolfssl and do the following: diff --git a/pq/stm32/Makefile b/pq/stm32/Makefile new file mode 100644 index 00000000..ca4907ba --- /dev/null +++ b/pq/stm32/Makefile @@ -0,0 +1,36 @@ +# PQ Examples Makefile +CC = gcc +LIB_PATH = /usr/local +CFLAGS = -Wall -I$(LIB_PATH)/include +LIBS = -L$(LIB_PATH)/lib -lm + +# option variables +DYN_LIB = -lwolfssl +STATIC_LIB = $(LIB_PATH)/lib/libwolfssl.a +DEBUG_FLAGS = -g -DDEBUG +DEBUG_INC_PATHS = -MD +OPTIMIZE = -Os + +# Options +#CFLAGS+=$(DEBUG_FLAGS) +CFLAGS+=$(OPTIMIZE) +#LIBS+=$(STATIC_LIB) +LIBS+=$(DYN_LIB) + +# build targets +SRC=$(wildcard *.c) +TARGETS=$(patsubst %.c, %, $(SRC)) + +.PHONY: clean all + +all: $(TARGETS) + +debug: CFLAGS+=$(DEBUG_FLAGS) +debug: all + +# build template +%: %.c + $(CC) -o $@ $< $(CFLAGS) $(LIBS) + +clean: + rm -f $(TARGETS) diff --git a/pq/stm32/README.md b/pq/stm32/README.md new file mode 100644 index 00000000..9f98b9d6 --- /dev/null +++ b/pq/stm32/README.md @@ -0,0 +1,145 @@ +# wolfSSL Post-Quantum Cryptography Example + +This directory contains: + +- server-tls-uart.c: A server application that can perform a completely + quantum-safe TLS 1.3 connection over UART via a USB to TTL serial cable. +- client-tls-uart.c: A client application that can perform a completely + quantum-safe TLS 1.3 connection over UART via a USB to TTL serial cable. +- wolfssl_stm32_pq: An STM32CubeIDE project that has already been configured to + work with the applications above to do TLS 1.3 connections as both the server + and client using KYBER_LEVEL1 KEM for key establishment. + +# Prerequisites + +Support for quantum-safe key establishment on STM32 platforms in STM32CubeIDE +is new and has not made it into a release as of the time of the writing of this +document. Support will start as of release 5.3.0. + +Please see README.md in the parent of this directory for insructions on how to +build and install liboqs and wolfSSL on your linux machine. They will be +required to build the applications on the linux side that will talk to the +STM32 board over UART. + +## Building the Applications for the Linux Side + +``` +$ make +``` + +## Configuring the STM32CubeIDE Project + +Please see the following video for highlights on how the project was configured +and how to configure wolfSSL to enable our PQM4 integration. + +https://www.youtube.com/watch?v=OK6MKXYiVBY + +To setup the required PQM4 source files, please run the `setup_kyber.sh` script +in this directory. It will clone releveant git repos from github and generate +the directories and files you need. + +Once you have successfully built and flashed the project, the STM32 terminal +should should display the following menu: + +``` + MENU + + t. wolfCrypt Test + b. wolfCrypt Benchmark + l. wolfSSL TLS Bench + e. Show Cipher List + s. Run TLS 1.3 Server over UART + c. Run TLS 1.3 Client over UART +Please select one of the above options: +``` + +## Benchmarks to Compare Against Conventional Algorithms + +On the STM32 console terminal, press the b key to run the benchmarks. + +Here is some sample output taken on a NUCLEO-F446ZE at 168MHz using SP Math +with Assembly Optimizations: + +``` +Running wolfCrypt Benchmarks... +wolfCrypt Benchmark (block bytes 1024, min 1.0 sec each) +RNG 1 MB took 1.004 seconds, 1.070 MB/s +AES-128-CBC-enc 1 MB took 1.000 seconds, 1.172 MB/s +AES-128-CBC-dec 1 MB took 1.008 seconds, 1.187 MB/s +AES-192-CBC-enc 1 MB took 1.000 seconds, 1.001 MB/s +AES-192-CBC-dec 1 MB took 1.004 seconds, 0.997 MB/s +AES-256-CBC-enc 900 KB took 1.007 seconds, 893.744 KB/s +AES-256-CBC-dec 900 KB took 1.004 seconds, 896.414 KB/s +AES-128-GCM-enc 75 KB took 1.094 seconds, 68.556 KB/s +AES-128-GCM-dec 75 KB took 1.094 seconds, 68.556 KB/s +AES-192-GCM-enc 75 KB took 1.118 seconds, 67.084 KB/s +AES-192-GCM-dec 75 KB took 1.117 seconds, 67.144 KB/s +AES-256-GCM-enc 75 KB took 1.134 seconds, 66.138 KB/s +AES-256-GCM-dec 75 KB took 1.130 seconds, 66.372 KB/s +GMAC Small 75 KB took 1.008 seconds, 74.405 KB/s +CHACHA 4 MB took 1.004 seconds, 4.426 MB/s +CHA-POLY 3 MB took 1.000 seconds, 2.905 MB/s +POLY1305 12 MB took 1.000 seconds, 12.183 MB/s +SHA-256 3 MB took 1.000 seconds, 2.832 MB/s +HMAC-SHA256 3 MB took 1.000 seconds, 2.808 MB/s +RSA 2048 public 78 ops took 1.016 sec, avg 13.026 ms, 76.772 ops/sec +RSA 2048 private 4 ops took 1.836 sec, avg 459.000 ms, 2.179 ops/sec +DH 2048 key gen 5 ops took 1.196 sec, avg 239.200 ms, 4.181 ops/sec +DH 2048 agree 6 ops took 1.439 sec, avg 239.833 ms, 4.170 ops/sec +ECC [ SECP256R1] 256 key gen 113 ops took 1.000 sec, avg 8.850 ms, 113.000 ops/sec +ECDHE [ SECP256R1] 256 agree 54 ops took 1.008 sec, avg 18.667 ms, 53.571 ops/sec +ECDSA [ SECP256R1] 256 sign 78 ops took 1.019 sec, avg 13.064 ms, 76.546 ops/sec +ECDSA [ SECP256R1] 256 verify 38 ops took 1.012 sec, avg 26.632 ms, 37.549 ops/sec +kyber_level1-kg 62 ops took 1.004 sec, avg 16.194 ms, 61.753 ops/sec +kyber_level1-ed 28 ops took 1.043 sec, avg 37.250 ms, 26.846 ops/sec +Benchmark complete +``` + +## Quantum safe TLS 1.3 Connection Over UART (Linux server, STM32 client) + +You will need to use sudo as the USB serial device requires root access. +In a terminal, execute the server: + +```sh +$ sudo ./server-tls-uart +``` + +On the STM32 console terminal, press the c key to run the client. + +## Quantum safe TLS 1.3 Connection Over UART (STM32 server, Linux client) + +On the STM32 console terminal, press the s key to run the server. This will put +the STM32 board into an infinite loop waiting for a client to connect over UART. +If you pressed the s key by accident, simply reset the board to bring yourself +back to the menu prompt. + +You will need to use sudo as the USB serial device requires root access. +In your Linux terminal, execute the client: + +```sh +$ sudo ./client-tls-uart +``` + +## Expected Output + +The server should have the following output: + +``` +Running TLS 1.3 server... +Waiting for client +TLS Accept handshake done +Read (0): Testing 1, 2 and 3 + +Sent (0): Testing 1, 2 and 3 +``` + +The client should have the following output: + +``` +Using quantum-safe KYBER_LEVEL1. +TLS Connect handshake done +Sending test string +Sent (0): Testing 1, 2 and 3 + +Read (0): Testing 1, 2 and 3 +``` diff --git a/pq/client-tls-uart.c b/pq/stm32/client-tls-uart.c similarity index 100% rename from pq/client-tls-uart.c rename to pq/stm32/client-tls-uart.c diff --git a/pq/server-tls-uart.c b/pq/stm32/server-tls-uart.c similarity index 98% rename from pq/server-tls-uart.c rename to pq/stm32/server-tls-uart.c index be22b78c..ed72bdcf 100644 --- a/pq/server-tls-uart.c +++ b/pq/stm32/server-tls-uart.c @@ -47,8 +47,8 @@ #include #include -#define CERT_FILE "../certs/server-cert.pem" -#define KEY_FILE "../certs/server-key.pem" +#define CERT_FILE "../../certs/server-cert.pem" +#define KEY_FILE "../../certs/server-key.pem" /* build with: gcc -lwolfssl -o server-tls-uart server-tls-uart.c diff --git a/pq/stm32/setup_kyber.patch b/pq/stm32/setup_kyber.patch new file mode 100644 index 00000000..5a6f5fdc --- /dev/null +++ b/pq/stm32/setup_kyber.patch @@ -0,0 +1,24 @@ +diff -u pqm4_kyber512.old/kem.c pqm4_kyber512/kem.c +--- pqm4_kyber512.old/kem.c 2022-03-28 16:36:40.045941053 -0400 ++++ pqm4_kyber512/kem.c 2022-03-11 13:38:07.166786818 -0500 +@@ -1,4 +1,4 @@ +-#include "api.h" ++#include "api_kyber.h" + #include "indcpa.h" + #include "params.h" + #include "randombytes.h" +diff -u pqm4_kyber512.old/randombytes.c pqm4_kyber512/randombytes.c +--- pqm4_kyber512.old/randombytes.c 2022-03-28 16:36:40.037940919 -0400 ++++ pqm4_kyber512/randombytes.c 2022-03-11 14:38:18.192717915 -0500 +@@ -320,6 +320,10 @@ + /* Use windows API */ + return randombytes_win32_randombytes(buf, n); + #else +-#error "randombytes(...) is not supported on this platform" ++ #warning randombytes() is not supported on this platform! ++ for (size_t i = 0; i < n; i++) { ++ buf[i] = (uint8_t)i; ++ } ++ return 0; + #endif + } diff --git a/pq/stm32/setup_kyber.sh b/pq/stm32/setup_kyber.sh new file mode 100755 index 00000000..d98f4c6a --- /dev/null +++ b/pq/stm32/setup_kyber.sh @@ -0,0 +1,83 @@ +#!/bin/bash + +mkdir pqm4_kyber512 +mkdir Inc +mkdir tmp + +cur_dir=$PWD +cd pqm4_kyber512 +code_dir=$PWD +cd ../Inc +inc_dir=$PWD +cd ../tmp +tmp_dir=$PWD + +git clone https://github.com/mupq/pqm4.git $tmp_dir/pqm4 +cd $tmp_dir/pqm4 +git checkout 3bfbbfd30401bd1dce3c497feb2a152713f2e735 + +git clone https://github.com/mupq/mupq.git $tmp_dir/mupq +cd $tmp_dir/mupq +git checkout 0235e325b60dcbd41bc82cdee55b5e3940e70b3e + +git clone https://github.com/pqclean/pqclean.git $tmp_dir/pqclean +cd $tmp_dir/pqclean +git checkout 964469d5506f3068c5afb504e3406f3291f6c336 + +# Populate include directory +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/params.h $inc_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/api.h $inc_dir + +# Get what we need from pqclean +cp $tmp_dir/pqclean/common/randombytes.c $code_dir +cp $tmp_dir/pqclean/common/randombytes.h $code_dir + +# Get what we need from mupq +cp $tmp_dir/mupq/common/keccakf1600.c $code_dir +cp $tmp_dir/mupq/common/keccakf1600.h $code_dir +cp $tmp_dir/mupq/common/fips202.c $code_dir +cp $tmp_dir/mupq/common/fips202.h $code_dir + +# Get what we need from pqm4 +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/cbd.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/cbd.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/fastaddsub.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/fastbasemul.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/fastinvntt.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/fastntt.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/indcpa.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/indcpa.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/kem.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/macros.i $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/matacc.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/matacc.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/matacc.i $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/matacc.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/ntt.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/ntt.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/poly.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/poly.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/poly.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/polyvec.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/polyvec.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/reduce.S $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/symmetric-fips202.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/symmetric.h $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/verify.c $code_dir +cp $tmp_dir/pqm4/crypto_kem/kyber512/m4fspeed/verify.h $code_dir + +# Rename some files +mv $inc_dir/api.h $inc_dir/api_kyber.h +mv $code_dir/matacc.S $code_dir/matacc_renamed.S +mv $code_dir/poly.S $code_dir/poly_renamed.S + +# Patch in some small fixups. +cd $cur_dir +patch -p0 < setup_kyber.patch + +# give the user some instructions +echo "Created $code_dir . Plese add it to your project's Core directory." +echo "Created $inc_dir . Plese add the files it contains to you project's Core/Inc directory." + +# Cleanup +rm -rf $tmp_dir diff --git a/pq/stm32/wolfssl_stm32_pq/.cproject b/pq/stm32/wolfssl_stm32_pq/.cproject new file mode 100644 index 00000000..b8e7b057 --- /dev/null +++ b/pq/stm32/wolfssl_stm32_pq/.cproject @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pq/stm32/wolfssl_stm32_pq/.mxproject b/pq/stm32/wolfssl_stm32_pq/.mxproject new file mode 100644 index 00000000..46b88305 --- /dev/null +++ b/pq/stm32/wolfssl_stm32_pq/.mxproject @@ -0,0 +1,7 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mml.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/stm32f4xx_it.c;Core/Src/stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;;; +HeaderPath=Drivers/STM32F4xx_HAL_Driver/Inc;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F4xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_HAL_DRIVER;STM32F446xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/pq/stm32/wolfssl_stm32_pq/.project b/pq/stm32/wolfssl_stm32_pq/.project new file mode 100644 index 00000000..1a685883 --- /dev/null +++ b/pq/stm32/wolfssl_stm32_pq/.project @@ -0,0 +1,32 @@ + + + wolfssl_stm32_pq + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/pq/stm32/wolfssl_stm32_pq/Core/Inc/main.h b/pq/stm32/wolfssl_stm32_pq/Core/Inc/main.h new file mode 100644 index 00000000..18b8855b --- /dev/null +++ b/pq/stm32/wolfssl_stm32_pq/Core/Inc/main.h @@ -0,0 +1,103 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define USER_Btn_Pin GPIO_PIN_13 +#define USER_Btn_GPIO_Port GPIOC +#define MCO_Pin GPIO_PIN_0 +#define MCO_GPIO_Port GPIOH +#define LD1_Pin GPIO_PIN_0 +#define LD1_GPIO_Port GPIOB +#define LD3_Pin GPIO_PIN_14 +#define LD3_GPIO_Port GPIOB +#define STLK_RX_Pin GPIO_PIN_8 +#define STLK_RX_GPIO_Port GPIOD +#define STLK_TX_Pin GPIO_PIN_9 +#define STLK_TX_GPIO_Port GPIOD +#define USB_PowerSwitchOn_Pin GPIO_PIN_6 +#define USB_PowerSwitchOn_GPIO_Port GPIOG +#define USB_OverCurrent_Pin GPIO_PIN_7 +#define USB_OverCurrent_GPIO_Port GPIOG +#define USB_SOF_Pin GPIO_PIN_8 +#define USB_SOF_GPIO_Port GPIOA +#define USB_VBUS_Pin GPIO_PIN_9 +#define USB_VBUS_GPIO_Port GPIOA +#define USB_ID_Pin GPIO_PIN_10 +#define USB_ID_GPIO_Port GPIOA +#define USB_DM_Pin GPIO_PIN_11 +#define USB_DM_GPIO_Port GPIOA +#define USB_DP_Pin GPIO_PIN_12 +#define USB_DP_GPIO_Port GPIOA +#define TMS_Pin GPIO_PIN_13 +#define TMS_GPIO_Port GPIOA +#define TCK_Pin GPIO_PIN_14 +#define TCK_GPIO_Port GPIOA +#define LD2_Pin GPIO_PIN_7 +#define LD2_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/pq/stm32/wolfssl_stm32_pq/Core/Src/main.c b/pq/stm32/wolfssl_stm32_pq/Core/Src/main.c new file mode 100644 index 00000000..d5761f2f --- /dev/null +++ b/pq/stm32/wolfssl_stm32_pq/Core/Src/main.c @@ -0,0 +1,432 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +RTC_HandleTypeDef hrtc; + +UART_HandleTypeDef huart2; +UART_HandleTypeDef huart3; +DMA_HandleTypeDef hdma_usart2_rx; + +PCD_HandleTypeDef hpcd_USB_OTG_FS; + +/* USER CODE BEGIN PV */ +/* Retargets the C library printf function to the USART. */ +#include +#include +#ifdef __GNUC__ +int __io_putchar(int ch) +#else +int fputc(int ch, FILE *f) +#endif +{ + HAL_UART_Transmit(&HAL_CONSOLE_UART, (uint8_t *)&ch, 1, 0xFFFF); + + return ch; +} +#ifdef __GNUC__ +int _write(int file,char *ptr, int len) +{ + int DataIdx; + for (DataIdx= 0; DataIdx< len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; +} +#endif +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_DMA_Init(void); +static void MX_USART2_UART_Init(void); +static void MX_USB_OTG_FS_PCD_Init(void); +static void MX_RTC_Init(void); +/* USER CODE BEGIN PFP */ +extern void wolfCryptDemo(void *argument); +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + /* Turn off buffers, so I/O occurs immediately */ + setvbuf(stdin, NULL, _IONBF, 0); + setvbuf(stdout, NULL, _IONBF, 0); + setvbuf(stderr, NULL, _IONBF, 0); + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_DMA_Init(); + MX_USART2_UART_Init(); + MX_USB_OTG_FS_PCD_Init(); + MX_RTC_Init(); + /* USER CODE BEGIN 2 */ + + wolfCryptDemo(NULL); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + printf("hellow\n"); + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief USB_OTG_FS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_FS_PCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_FS_Init 0 */ + + /* USER CODE END USB_OTG_FS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_FS_Init 1 */ + + /* USER CODE END USB_OTG_FS_Init 1 */ + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_FS_Init 2 */ + + /* USER CODE END USB_OTG_FS_Init 2 */ + +} + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : USER_Btn_Pin */ + GPIO_InitStruct.Pin = USER_Btn_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */ + GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : USB_PowerSwitchOn_Pin */ + GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : USB_OverCurrent_Pin */ + GPIO_InitStruct.Pin = USB_OverCurrent_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/pq/stm32/wolfssl_stm32_pq/wolfssl_stm32_pq.ioc b/pq/stm32/wolfssl_stm32_pq/wolfssl_stm32_pq.ioc new file mode 100644 index 00000000..485119e4 --- /dev/null +++ b/pq/stm32/wolfssl_stm32_pq/wolfssl_stm32_pq.ioc @@ -0,0 +1,286 @@ +#MicroXplorer Configuration settings - do not modify +Dma.Request0=USART2_RX +Dma.RequestsNb=1 +Dma.USART2_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART2_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_RX.0.Instance=DMA1_Stream5 +Dma.USART2_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_RX.0.MemInc=DMA_MINC_ENABLE +Dma.USART2_RX.0.Mode=DMA_NORMAL +Dma.USART2_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_RX.0.Priority=DMA_PRIORITY_LOW +Dma.USART2_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=DMA +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=RTC +Mcu.IP4=SYS +Mcu.IP5=USART2 +Mcu.IP6=USART3 +Mcu.IP7=USB_OTG_FS +Mcu.IPNb=8 +Mcu.Name=STM32F446Z(C-E)Tx +Mcu.Package=LQFP144 +Mcu.Pin0=PC13 +Mcu.Pin1=PC14-OSC32_IN +Mcu.Pin10=PG7 +Mcu.Pin11=PA8 +Mcu.Pin12=PA9 +Mcu.Pin13=PA10 +Mcu.Pin14=PA11 +Mcu.Pin15=PA12 +Mcu.Pin16=PA13 +Mcu.Pin17=PA14 +Mcu.Pin18=PD5 +Mcu.Pin19=PD6 +Mcu.Pin2=PC15-OSC32_OUT +Mcu.Pin20=PB7 +Mcu.Pin21=VP_RTC_VS_RTC_Activate +Mcu.Pin22=VP_SYS_VS_Systick +Mcu.Pin3=PH0-OSC_IN +Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin5=PB0 +Mcu.Pin6=PB14 +Mcu.Pin7=PD8 +Mcu.Pin8=PD9 +Mcu.Pin9=PG6 +Mcu.PinsNb=23 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F446ZETx +MxCube.Version=6.3.0 +MxDb.Version=DB.6.0.30 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.DMA1_Stream5_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +PA10.GPIOParameters=GPIO_Label +PA10.GPIO_Label=USB_ID +PA10.Locked=true +PA10.Signal=USB_OTG_FS_ID +PA11.GPIOParameters=GPIO_Label +PA11.GPIO_Label=USB_DM +PA11.Locked=true +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.GPIOParameters=GPIO_Label +PA12.GPIO_Label=USB_DP +PA12.Locked=true +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP +PA13.GPIOParameters=GPIO_Label +PA13.GPIO_Label=TMS +PA13.Locked=true +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.GPIOParameters=GPIO_Label +PA14.GPIO_Label=TCK +PA14.Locked=true +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA8.GPIOParameters=GPIO_Label +PA8.GPIO_Label=USB_SOF [TP1] +PA8.Locked=true +PA8.Mode=Activate_SOF_FS +PA8.Signal=USB_OTG_FS_SOF +PA9.GPIOParameters=GPIO_Label +PA9.GPIO_Label=USB_VBUS +PA9.Locked=true +PA9.Mode=Activate_VBUS +PA9.Signal=USB_OTG_FS_VBUS +PB0.GPIOParameters=GPIO_Label +PB0.GPIO_Label=LD1 [Green] +PB0.Locked=true +PB0.Signal=GPIO_Output +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=LD3 [Red] +PB14.Locked=true +PB14.Signal=GPIO_Output +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=LD2 [Blue] +PB7.Locked=true +PB7.Signal=GPIO_Output +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=USER_Btn [B1] +PC13.Locked=true +PC13.Signal=GPXTI13 +PC14-OSC32_IN.Locked=true +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Locked=true +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PD5.Locked=true +PD5.Mode=Asynchronous +PD5.Signal=USART2_TX +PD6.Locked=true +PD6.Mode=Asynchronous +PD6.Signal=USART2_RX +PD8.GPIOParameters=GPIO_Label +PD8.GPIO_Label=STLK_RX [STM32F103CBT6_PA3] +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.GPIOParameters=GPIO_Label +PD9.GPIO_Label=STLK_TX [STM32F103CBT6_PA2] +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG6.GPIOParameters=GPIO_Label +PG6.GPIO_Label=USB_PowerSwitchOn [STMPS2151STR_EN] +PG6.Locked=true +PG6.Signal=GPIO_Output +PG7.GPIOParameters=GPIO_Label +PG7.GPIO_Label=USB_OverCurrent [STMPS2151STR_FAULT] +PG7.Locked=true +PG7.Signal=GPIO_Input +PH0-OSC_IN.GPIOParameters=GPIO_Label +PH0-OSC_IN.GPIO_Label=MCO [STM32F103CBT6_PA8] +PH0-OSC_IN.Locked=true +PH0-OSC_IN.Mode=HSE-External-Clock-Source +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Locked=true +PH1-OSC_OUT.Mode=HSE-External-Clock-Source +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F446ZETx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.26.2 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=wolfssl_stm32_pq.ioc +ProjectManager.ProjectName=wolfssl_stm32_pq +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_DMA_Init-DMA-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true +RCC.48MHZClocksFreq_Value=24000000 +RCC.ADC12outputFreq_Value=72000000 +RCC.ADC34outputFreq_Value=72000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=8000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FMPI2C1Freq_Value=42000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=8000000 +RCC.I2C2Freq_Value=8000000 +RCC.I2C3Freq_Value=8000000 +RCC.I2S1Freq_Value=48000000 +RCC.I2S2Freq_Value=48000000 +RCC.I2SClocksFreq_Value=48000000 +RCC.IPParameters=48MHZClocksFreq_Value,ADC12outputFreq_Value,ADC34outputFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FMPI2C1Freq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2S1Freq_Value,I2S2Freq_Value,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SoutputFreq_Value,PLLM,PLLMCOFreq_Value,PLLMUL,PLLN,PLLQ,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIoutputFreq_Value,PRESCALERUSB,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SDIOFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,SYSCLKSourceVirtual,TIM15Freq_Value,TIM16Freq_Value,TIM17Freq_Value,TIM1Freq_Value,TIM20Freq_Value,TIM2Freq_Value,TIM3Freq_Value,TIM8Freq_Value,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOI2SInputFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutput2Freq_Value,VCOOutputFreq_Value,VCOSAIInputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ,WatchDogFreq_Value +RCC.LCDTFTFreq_Value=6125000 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=16000000 +RCC.MCO2PinFreq_Value=168000000 +RCC.MCOFreq_Value=72000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLI2SPCLKFreq_Value=48000000 +RCC.PLLI2SQCLKFreq_Value=48000000 +RCC.PLLI2SRCLKFreq_Value=48000000 +RCC.PLLI2SoutputFreq_Value=48000000 +RCC.PLLM=4 +RCC.PLLMCOFreq_Value=72000000 +RCC.PLLMUL=RCC_PLL_MUL9 +RCC.PLLN=168 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLRCLKFreq_Value=168000000 +RCC.PLLSAIPCLKFreq_Value=48000000 +RCC.PLLSAIQCLKFreq_Value=48000000 +RCC.PLLSAIoutputFreq_Value=48000000 +RCC.PRESCALERUSB=RCC_USBCLKSOURCE_PLL_DIV1_5 +RCC.PWRFreq_Value=168000000 +RCC.RTCFreq_Value=32000 +RCC.RTCHSEDivFreq_Value=4000000 +RCC.SAIAFreq_Value=48000000 +RCC.SAIBFreq_Value=48000000 +RCC.SAI_AClocksFreq_Value=6125000 +RCC.SAI_BClocksFreq_Value=6125000 +RCC.SDIOFreq_Value=48000000 +RCC.SPDIFRXFreq_Value=168000000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK +RCC.TIM15Freq_Value=72000000 +RCC.TIM16Freq_Value=72000000 +RCC.TIM17Freq_Value=72000000 +RCC.TIM1Freq_Value=72000000 +RCC.TIM20Freq_Value=72000000 +RCC.TIM2Freq_Value=72000000 +RCC.TIM3Freq_Value=72000000 +RCC.TIM8Freq_Value=72000000 +RCC.UART4Freq_Value=36000000 +RCC.UART5Freq_Value=36000000 +RCC.USART1Freq_Value=72000000 +RCC.USART2Freq_Value=36000000 +RCC.USART3Freq_Value=36000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SInputFreq_Value=500000 +RCC.VCOI2SOutputFreq_Value=96000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutput2Freq_Value=8000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VCOSAIInputFreq_Value=500000 +RCC.VCOSAIOutputFreq_Value=96000000 +RCC.VCOSAIOutputFreq_ValueQ=6125000 +RCC.VCOSAIOutputFreq_ValueR=12250000 +RCC.VcooutputI2S=48000000 +RCC.VcooutputI2SQ=48000000 +RCC.WatchDogFreq_Value=32000 +SH.GPXTI13.0=GPIO_EXTI13 +SH.GPXTI13.ConfNb=1 +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +USART3.IPParameters=VirtualMode +USART3.VirtualMode=VM_ASYNC +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=NUCLEO-F446ZE +boardIOC=true +isbadioc=false