diff --git a/RT1060/MIMXRT1062xxxxx_flexspi_nor.ld b/RT1060/MIMXRT1062xxxxx_flexspi_nor.ld new file mode 100644 index 00000000..451dd1ed --- /dev/null +++ b/RT1060/MIMXRT1062xxxxx_flexspi_nor.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** +** Linker file for the GNU C Compiler +** +** Copyright (C) 2020 wolfSSL Inc. +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; */ +/* STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; */ +HEAP_SIZE = 0x10000; + +STACK_SIZE = 0x8000; +VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x007FDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_data2); + __NCACHE_REGION_SIZE = 0; + + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/RT1060/Makefile b/RT1060/Makefile new file mode 100644 index 00000000..b6247f8e --- /dev/null +++ b/RT1060/Makefile @@ -0,0 +1,83 @@ +SDK=./SDK-2.8.2_EVK-MIMXRT1060 +WOLFSSL=../../wolfssl + +CC=arm-none-eabi-gcc + +ASMFLAGS=-D__STARTUP_CLEAR_BSS -D__STARTUP_INITIALIZE_NONCACHEDATA -mcpu=cortex-m7 -Wall -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mapcs -std=gnu99 +CFLAGS=-DXIP_EXTERNAL_FLASH=1 -DXIP_BOOT_HEADER_ENABLE=1 -DCPU_MIMXRT1062DVL6A -DPRINTF_FLOAT_ENABLE=1 -DSCANF_FLOAT_ENABLE=1 -DPRINTF_ADVANCED_ENABLE=1 -DSCANF_ADVANCED_ENABLE=1 -DSERIAL_PORT_TYPE_UART=1 -Os -mcpu=cortex-m7 -Wall -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -MMD -MP -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mapcs -std=gnu99 -DXPRINTF=PRINTF +LDFLAGS= -mcpu=cortex-m7 -Wall -mfloat-abi=hard -mfpu=fpv5-d16 --specs=nosys.specs -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mthumb -mapcs -Xlinker --gc-sections -Xlinker -static -Xlinker -z -Xlinker muldefs -Xlinker -Map=output.map -T MIMXRT1062xxxxx_flexspi_nor.ld -static -lm -lc -lnosys + +CFLAGS+=-I$(SDK)/devices/MIMXRT1062/utilities/debug_console/ +CFLAGS+=-I$(SDK)/components/serial_manager -I$(SDK)/components/uart/ +CFLAGS+=-I$(SDK) -I$(SDK)/devices/MIMXRT1062/drivers/ -I$(SDK)/devices/MIMXRT1062 -I$(SDK)/CMSIS/Include +CFLAGS+=-I$(SDK)/devices/MIMXRT1062/utilities/str +CFLAGS+=-I. -I$(WOLFSSL) + +CFLAGS+=-DWOLFSSL_USER_SETTINGS + +OBJS=common.o board.o pin_mux.o dcd.o clock_config.o $(SDK)/devices/MIMXRT1062/gcc/startup_MIMXRT1062.o $(SDK)/devices/MIMXRT1062/system_MIMXRT1062.o \ + $(SDK)/devices/MIMXRT1062/drivers/fsl_clock.o \ + $(SDK)/devices/MIMXRT1062/drivers/fsl_trng.o \ + $(SDK)/devices/MIMXRT1062/drivers/fsl_common.o \ + $(SDK)/devices/MIMXRT1062/utilities/debug_console/fsl_debug_console.o \ + $(SDK)/devices/MIMXRT1062/utilities/str/fsl_str.o \ + $(SDK)/components/uart/lpuart_adapter.o \ + $(SDK)/components/serial_manager/serial_manager.o \ + $(SDK)/components/lists/generic_list.o \ + $(SDK)/components/serial_manager/serial_port_uart.o \ + $(SDK)/devices/MIMXRT1062/drivers/fsl_lpuart.o \ + $(SDK)/devices/MIMXRT1062/utilities/fsl_assert.o \ + $(SDK)/devices/MIMXRT1062/drivers/fsl_gpio.o \ + $(SDK)/devices/MIMXRT1062/xip/fsl_flexspi_nor_boot.o \ + $(SDK)/boards/evkmimxrt1060/xip/evkmimxrt1060_flexspi_nor_config.o \ + $(SDK)/devices/MIMXRT1062/utilities/fsl_sbrk.o + +OBJS+= \ + $(WOLFSSL)/wolfcrypt/src/wc_port.o \ + $(WOLFSSL)/wolfcrypt/src/wc_encrypt.o \ + $(WOLFSSL)/wolfcrypt/src/random.o \ + $(WOLFSSL)/wolfcrypt/src/logging.o \ + $(WOLFSSL)/wolfcrypt/src/sp_int.o \ + $(WOLFSSL)/wolfcrypt/src/sp_cortexm.o \ + $(WOLFSSL)/wolfcrypt/src/ecc.o \ + $(WOLFSSL)/wolfcrypt/src/rsa.o \ + $(WOLFSSL)/wolfcrypt/src/aes.o \ + $(WOLFSSL)/wolfcrypt/src/asn.o \ + $(WOLFSSL)/wolfcrypt/src/sha.o \ + $(WOLFSSL)/wolfcrypt/src/sha256.o \ + $(WOLFSSL)/wolfcrypt/src/sha512.o \ + $(WOLFSSL)/wolfcrypt/src/sha3.o \ + $(WOLFSSL)/wolfcrypt/src/chacha.o \ + $(WOLFSSL)/wolfcrypt/src/ed25519.o \ + $(WOLFSSL)/wolfcrypt/src/md5.o \ + $(WOLFSSL)/wolfcrypt/src/hmac.o \ + $(WOLFSSL)/wolfcrypt/src/coding.o \ + $(WOLFSSL)/wolfcrypt/src/ge_low_mem.o \ + $(WOLFSSL)/wolfcrypt/src/hash.o \ + $(WOLFSSL)/wolfcrypt/src/pwdbased.o \ + $(WOLFSSL)/wolfcrypt/src/wolfmath.o \ + $(WOLFSSL)/wolfcrypt/src/fe_low_mem.o + + +TEST_OBJS:=$(WOLFSSL)/wolfcrypt/test/test.o main-test.o +BENCH_OBJS:=$(WOLFSSL)/wolfcrypt/benchmark/benchmark.o main-bench.o + +all: wolfcrypt-test.bin wolfcrypt-benchmark.bin + +wolfcrypt-test.bin: wolfcrypt-test.elf + arm-none-eabi-objcopy -O binary $^ $@ + +wolfcrypt-benchmark.bin: wolfcrypt-benchmark.elf + arm-none-eabi-objcopy -O binary $^ $@ + +wolfcrypt-test.elf: $(OBJS) $(TEST_OBJS) + $(CC) -o $@ $^ $(LDFLAGS) + +wolfcrypt-benchmark.elf: $(OBJS) $(BENCH_OBJS) + $(CC) -o $@ $^ $(LDFLAGS) + +clean: + rm -f *.o *.elf *.bin *.map *.d + rm -f $(WOLFSSL)/wolfcrypt/src/*.o + rm -f $(WOLFSSL)/wolfcrypt/benchmark/*.o + rm -f $(WOLFSSL)/wolfcrypt/test/*.o diff --git a/RT1060/README.md b/RT1060/README.md new file mode 100644 index 00000000..1455401e --- /dev/null +++ b/RT1060/README.md @@ -0,0 +1,26 @@ +Building wolfCrypt benchmark on i.MX RT1060-EVK + +1. Go to https://mcuxpresso.nxp.com and download the SDK archive for RT1060 - version 2.8.2 + +2. Unpack the SDK archive into `./SDK-2.8.2_EVK-MIMXRT1060` + +3. Download latest wolfSSL (e.g. clone via `git clone git@github.com:wolfssl/wolfssl.git`) in the same directory as `wolfssl-examples` + +4. Ensure that a recent arm-gcc toolchain is installed and reachable from your path. A recent toolchain can be obtained from: + https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm + +5. Clone this repository + +6. Enter the repository directory and run `make` + +7. Connect the RT1060-EVK to the computer via the OpenSDA USB port (L23) + +8. Copy either `wolfcrypt-test.bin` or `wolfcrypt-benchmark.bin` to the storage device associated to the RT1060-EVK + +9. Open a terminal console emulator and connect it to the port associated to the RT1060-RVK (e.g. `/dev/ttyACM0`) + +10. Reset the board to start the test or benchmark and read the result on the terminal console + + +Benchmark results are also available in the file [results.md](results.md) + diff --git a/RT1060/SDK-2.8.2_EVK-MIMXRT1060/README.md b/RT1060/SDK-2.8.2_EVK-MIMXRT1060/README.md new file mode 100644 index 00000000..cd158d0d --- /dev/null +++ b/RT1060/SDK-2.8.2_EVK-MIMXRT1060/README.md @@ -0,0 +1,3 @@ +## SDK for i.MX RT1060 + +Go to https://mcuxpresso.nxp.com, download the SDK archive for RT1060 - version 2.8.2 and unpack it to this directory diff --git a/RT1060/board.c b/RT1060/board.c new file mode 100644 index 00000000..a0947daf --- /dev/null +++ b/RT1060/board.c @@ -0,0 +1,401 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get debug console frequency. */ +uint32_t BOARD_DebugConsoleSrcFreq(void) +{ + uint32_t freq; + + /* To make it simple, we assume default PLL and divider settings, and the only variable + from application is use PLL3 source or OSC source */ + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + + return freq; +} + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq(); + + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} + +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) +{ + lpi2c_master_config_t lpi2cConfig = {0}; + + /* + * lpi2cConfig.debugEnable = false; + * lpi2cConfig.ignoreAck = false; + * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; + * lpi2cConfig.baudRate_Hz = 100000U; + * lpi2cConfig.busIdleTimeout_ns = 0; + * lpi2cConfig.pinLowTimeout_ns = 0; + * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; + * lpi2cConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&lpi2cConfig); + LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); +} + +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Read; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + status_t status; + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = NULL; + xfer.dataSize = 0; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + + if (kStatus_Success == status) + { + xfer.subaddressSize = 0; + xfer.direction = kLPI2C_Read; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + } + + return status; +} + +void BOARD_Accel_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ); +} + +status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff) +{ + uint8_t data = (uint8_t)txBuff; + + return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1); +} + +status_t BOARD_Accel_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize); +} + +void BOARD_Codec_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); +} + +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); +} + +void BOARD_Camera_I2C_Init(void) +{ + CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER); + BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ); +} + +status_t BOARD_Camera_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Camera_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize); +} + +status_t BOARD_Camera_I2C_SendSCCB( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Camera_I2C_ReceiveSCCB( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize); +} +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? + 0 : + ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; +#endif + uint32_t i = 0; + + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) + { + SCB_DisableDCache(); + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + * + */ + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB); +#endif + + /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); + + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + while ((size >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + + /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB); + + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} diff --git a/RT1060/board.h b/RT1060/board.h new file mode 100644 index 00000000..c4671f9a --- /dev/null +++ b/RT1060/board.h @@ -0,0 +1,229 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMXRT1060-EVK" + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#define BOARD_DEBUG_UART_INSTANCE 1U + +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() + +#define BOARD_UART_IRQ LPUART1_IRQn +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE (115200U) +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON (0U) +#define LOGIC_LED_OFF (1U) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO GPIO1 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN (9U) +#endif + +#define USER_LED_INIT(output) \ + GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ + BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ +#define USER_LED_ON() \ + GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ +#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET1 Tx clock source. */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + /* Set ENET2 Tx clock source. */ +#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); +#else + IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); +#endif + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + diff --git a/RT1060/clock_config.h b/RT1060/clock_config.h new file mode 100644 index 00000000..18be3bee --- /dev/null +++ b/RT1060/clock_config.h @@ -0,0 +1,133 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/RT1060/common.c b/RT1060/common.c new file mode 100644 index 00000000..e1615ed4 --- /dev/null +++ b/RT1060/common.c @@ -0,0 +1,36 @@ +#include +#include +#include "user_settings.h" +#include "wolfssl/wolfcrypt/settings.h" +#include "fsl_trng.h" + +volatile uint32_t g_systickCounter; +struct timezone; + +int gettimeofday(struct timeval *tv, struct timezone *tz) +{ + (void)tz; + tv->tv_sec = g_systickCounter / 1000; + tv->tv_usec = (g_systickCounter % 1000) * 1000; + return 0; +} + +/******************************************************************************* + * Code + ******************************************************************************/ +void SysTick_Handler(void) +{ + g_systickCounter++; +} + +int32_t cust_rand_generate_block(uint8_t *rndb, uint32_t sz) +{ + status_t status; + status = TRNG_GetRandomData(TRNG, rndb,sz); + if (status != kStatus_Success) { + PRINTF("ERROR: TRNG STATUS: %d\r\n"); + return -1; + } + return 0; +} + diff --git a/RT1060/dcd.c b/RT1060/dcd.c new file mode 100644 index 00000000..2762a690 --- /dev/null +++ b/RT1060/dcd.c @@ -0,0 +1,322 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: MIMXRT1060-EVK +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 + }; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/RT1060/dcd.h b/RT1060/dcd.h new file mode 100644 index 00000000..747b1a07 --- /dev/null +++ b/RT1060/dcd.h @@ -0,0 +1,43 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/RT1060/main-bench.c b/RT1060/main-bench.c new file mode 100644 index 00000000..e4063dec --- /dev/null +++ b/RT1060/main-bench.c @@ -0,0 +1,57 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +#include "user_settings.h" +#include "wolfssl/wolfcrypt/settings.h" +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "fsl_trng.h" + +#include "board.h" +#include + +#include "pin_mux.h" +#include "clock_config.h" +#include "wolfcrypt/benchmark/benchmark.h" +#include "wolfcrypt/test/test.h" + +#include + +void main(void) +{ + char ch; + trng_config_t trngConfig; + /* Init board hardware. */ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_InitBootClocks(); + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock / 1000U); + BOARD_InitDebugConsole(); + TRNG_GetDefaultConfig(&trngConfig); + trngConfig.sampleMode = kTRNG_SampleModeVonNeumann; + benchmark_init(); + benchmark_test(NULL); + + while (1) + { + ch = GETCHAR(); + PUTCHAR(ch); + } + +} diff --git a/RT1060/main-test.c b/RT1060/main-test.c new file mode 100644 index 00000000..37b7e116 --- /dev/null +++ b/RT1060/main-test.c @@ -0,0 +1,56 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +#include "user_settings.h" +#include "wolfssl/wolfcrypt/settings.h" +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "fsl_trng.h" + +#include "board.h" +#include + +#include "pin_mux.h" +#include "clock_config.h" +#include "wolfcrypt/test/test.h" +#include + + + +void main(void) +{ + char ch; + trng_config_t trngConfig; + /* Init board hardware. */ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_InitBootClocks(); + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock / 1000U); + BOARD_InitDebugConsole(); + TRNG_GetDefaultConfig(&trngConfig); + trngConfig.sampleMode = kTRNG_SampleModeVonNeumann; + wolfcrypt_test(NULL); + + while (1) + { + ch = GETCHAR(); + PUTCHAR(ch); + } + +} diff --git a/RT1060/peripherals.c b/RT1060/peripherals.c new file mode 100644 index 00000000..cdd31993 --- /dev/null +++ b/RT1060/peripherals.c @@ -0,0 +1,59 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v8.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 0.8.2 +board: MIMXRT1060-EVK +functionalGroups: +- name: BOARD_InitPeripherals + UUID: 96c1cec6-3bd3-47a2-8301-f38e4b0dd25f + called_from_default_init: true + selectedCore: core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/RT1060/peripherals.h b/RT1060/peripherals.h new file mode 100644 index 00000000..a76a1760 --- /dev/null +++ b/RT1060/peripherals.h @@ -0,0 +1,46 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/RT1060/pin_mux.c b/RT1060/pin_mux.c new file mode 100644 index 00000000..86678360 --- /dev/null +++ b/RT1060/pin_mux.c @@ -0,0 +1,111 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v7.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 0.7.9 +board: MIMXRT1060-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: G13, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_AD_B0_10, slew_rate: Fast} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, /* GPIO_AD_B0_10 is configured as ARM_TRACE_SWO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, /* GPIO_AD_B0_10 PAD functional properties : */ + 0x90B1U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/RT1060/pin_mux.h b/RT1060/pin_mux.h new file mode 100644 index 00000000..a658b3b6 --- /dev/null +++ b/RT1060/pin_mux.h @@ -0,0 +1,949 @@ +/* wolfCrypt benchmark test application for i.MX RT1060-EVK + * + * Copyright (C) 2020 wolfSSL Inc. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +#define BOARD_INITDEBUG_UART_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITDEBUG_UART_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */ +#define BOARD_INITDEBUG_UART_UART1_TXD_PIN_NAME GPIO_AD_B0_12 /*!< Pin name */ +#define BOARD_INITDEBUG_UART_UART1_TXD_LABEL "UART1_TXD" /*!< Label */ +#define BOARD_INITDEBUG_UART_UART1_TXD_NAME "UART1_TXD" /*!< Identifier name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +#define BOARD_INITDEBUG_UART_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITDEBUG_UART_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */ +#define BOARD_INITDEBUG_UART_UART1_RXD_PIN_NAME GPIO_AD_B0_13 /*!< Pin name */ +#define BOARD_INITDEBUG_UART_UART1_RXD_LABEL "UART1_RXD" /*!< Label */ +#define BOARD_INITDEBUG_UART_UART1_RXD_NAME "UART1_RXD" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UART(void); + +/* GPIO_EMC_09 (coord C2), SEMC_A0 */ +#define BOARD_INITSDRAM_SEMC_A0_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A0_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A0_CHANNEL 0U /*!< SEMC ADDR channel: 00 */ +#define BOARD_INITSDRAM_SEMC_A0_PIN_NAME GPIO_EMC_09 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A0_LABEL "SEMC_A0" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A0_NAME "SEMC_A0" /*!< Identifier name */ + +/* GPIO_EMC_10 (coord G1), SEMC_A1 */ +#define BOARD_INITSDRAM_SEMC_A1_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A1_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A1_CHANNEL 1U /*!< SEMC ADDR channel: 01 */ +#define BOARD_INITSDRAM_SEMC_A1_PIN_NAME GPIO_EMC_10 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A1_LABEL "SEMC_A1" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A1_NAME "SEMC_A1" /*!< Identifier name */ + +/* GPIO_EMC_11 (coord G3), SEMC_A2 */ +#define BOARD_INITSDRAM_SEMC_A2_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A2_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A2_CHANNEL 2U /*!< SEMC ADDR channel: 02 */ +#define BOARD_INITSDRAM_SEMC_A2_PIN_NAME GPIO_EMC_11 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A2_LABEL "SEMC_A2" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A2_NAME "SEMC_A2" /*!< Identifier name */ + +/* GPIO_EMC_12 (coord H1), SEMC_A3 */ +#define BOARD_INITSDRAM_SEMC_A3_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A3_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A3_CHANNEL 3U /*!< SEMC ADDR channel: 03 */ +#define BOARD_INITSDRAM_SEMC_A3_PIN_NAME GPIO_EMC_12 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A3_LABEL "SEMC_A3" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A3_NAME "SEMC_A3" /*!< Identifier name */ + +/* GPIO_EMC_13 (coord A6), SEMC_A4 */ +#define BOARD_INITSDRAM_SEMC_A4_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A4_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A4_CHANNEL 4U /*!< SEMC ADDR channel: 04 */ +#define BOARD_INITSDRAM_SEMC_A4_PIN_NAME GPIO_EMC_13 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A4_LABEL "SEMC_A4" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A4_NAME "SEMC_A4" /*!< Identifier name */ + +/* GPIO_EMC_14 (coord B6), SEMC_A5 */ +#define BOARD_INITSDRAM_SEMC_A5_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A5_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A5_CHANNEL 5U /*!< SEMC ADDR channel: 05 */ +#define BOARD_INITSDRAM_SEMC_A5_PIN_NAME GPIO_EMC_14 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A5_LABEL "SEMC_A5" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A5_NAME "SEMC_A5" /*!< Identifier name */ + +/* GPIO_EMC_15 (coord B1), SEMC_A6 */ +#define BOARD_INITSDRAM_SEMC_A6_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A6_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A6_CHANNEL 6U /*!< SEMC ADDR channel: 06 */ +#define BOARD_INITSDRAM_SEMC_A6_PIN_NAME GPIO_EMC_15 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A6_LABEL "SEMC_A6" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A6_NAME "SEMC_A6" /*!< Identifier name */ + +/* GPIO_EMC_16 (coord A5), SEMC_A7 */ +#define BOARD_INITSDRAM_SEMC_A7_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A7_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A7_CHANNEL 7U /*!< SEMC ADDR channel: 07 */ +#define BOARD_INITSDRAM_SEMC_A7_PIN_NAME GPIO_EMC_16 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A7_LABEL "SEMC_A7" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A7_NAME "SEMC_A7" /*!< Identifier name */ + +/* GPIO_EMC_17 (coord A4), SEMC_A8 */ +#define BOARD_INITSDRAM_SEMC_A8_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A8_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A8_CHANNEL 8U /*!< SEMC ADDR channel: 08 */ +#define BOARD_INITSDRAM_SEMC_A8_PIN_NAME GPIO_EMC_17 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A8_LABEL "SEMC_A8" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A8_NAME "SEMC_A8" /*!< Identifier name */ + +/* GPIO_EMC_18 (coord B2), SEMC_A9 */ +#define BOARD_INITSDRAM_SEMC_A9_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A9_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A9_CHANNEL 9U /*!< SEMC ADDR channel: 09 */ +#define BOARD_INITSDRAM_SEMC_A9_PIN_NAME GPIO_EMC_18 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A9_LABEL "SEMC_A9" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A9_NAME "SEMC_A9" /*!< Identifier name */ + +/* GPIO_EMC_23 (coord G2), SEMC_A10 */ +#define BOARD_INITSDRAM_SEMC_A10_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A10_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A10_CHANNEL 10U /*!< SEMC ADDR channel: 10 */ +#define BOARD_INITSDRAM_SEMC_A10_PIN_NAME GPIO_EMC_23 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A10_LABEL "SEMC_A10" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A10_NAME "SEMC_A10" /*!< Identifier name */ + +/* GPIO_EMC_19 (coord B4), SEMC_A11 */ +#define BOARD_INITSDRAM_SEMC_A11_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A11_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A11_CHANNEL 11U /*!< SEMC ADDR channel: 11 */ +#define BOARD_INITSDRAM_SEMC_A11_PIN_NAME GPIO_EMC_19 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A11_LABEL "SEMC_A11" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A11_NAME "SEMC_A11" /*!< Identifier name */ + +/* GPIO_EMC_20 (coord A3), SEMC_A12 */ +#define BOARD_INITSDRAM_SEMC_A12_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_A12_SIGNAL ADDR /*!< SEMC signal: ADDR */ +#define BOARD_INITSDRAM_SEMC_A12_CHANNEL 12U /*!< SEMC ADDR channel: 12 */ +#define BOARD_INITSDRAM_SEMC_A12_PIN_NAME GPIO_EMC_20 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_A12_LABEL "SEMC_A12" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_A12_NAME "SEMC_A12" /*!< Identifier name */ + +/* GPIO_EMC_21 (coord C1), SEMC_BA0 */ +#define BOARD_INITSDRAM_SEMC_BA0_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_BA0_SIGNAL BA /*!< SEMC signal: BA */ +#define BOARD_INITSDRAM_SEMC_BA0_CHANNEL 0U /*!< SEMC BA channel: 0 */ +#define BOARD_INITSDRAM_SEMC_BA0_PIN_NAME GPIO_EMC_21 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_BA0_LABEL "SEMC_BA0" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_BA0_NAME "SEMC_BA0" /*!< Identifier name */ + +/* GPIO_EMC_22 (coord F1), SEMC_BA1 */ +#define BOARD_INITSDRAM_SEMC_BA1_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_BA1_SIGNAL BA /*!< SEMC signal: BA */ +#define BOARD_INITSDRAM_SEMC_BA1_CHANNEL 1U /*!< SEMC BA channel: 1 */ +#define BOARD_INITSDRAM_SEMC_BA1_PIN_NAME GPIO_EMC_22 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_BA1_LABEL "SEMC_BA1" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_BA1_NAME "SEMC_BA1" /*!< Identifier name */ + +/* GPIO_EMC_24 (coord D3), SEMC_CAS */ +#define BOARD_INITSDRAM_SEMC_CAS_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_CAS_SIGNAL semc_cas /*!< SEMC signal: semc_cas */ +#define BOARD_INITSDRAM_SEMC_CAS_PIN_NAME GPIO_EMC_24 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_CAS_LABEL "SEMC_CAS" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_CAS_NAME "SEMC_CAS" /*!< Identifier name */ + +/* GPIO_EMC_27 (coord A2), SEMC_CKE */ +#define BOARD_INITSDRAM_SEMC_CKE_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_CKE_SIGNAL semc_cke /*!< SEMC signal: semc_cke */ +#define BOARD_INITSDRAM_SEMC_CKE_PIN_NAME GPIO_EMC_27 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_CKE_LABEL "SEMC_CKE" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_CKE_NAME "SEMC_CKE" /*!< Identifier name */ + +/* GPIO_EMC_26 (coord B3), SEMC_CLK */ +#define BOARD_INITSDRAM_SEMC_CLK_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_CLK_SIGNAL semc_clk /*!< SEMC signal: semc_clk */ +#define BOARD_INITSDRAM_SEMC_CLK_PIN_NAME GPIO_EMC_26 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_CLK_LABEL "SEMC_CLK" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_CLK_NAME "SEMC_CLK" /*!< Identifier name */ + +/* GPIO_EMC_00 (coord E3), SEMC_D0 */ +#define BOARD_INITSDRAM_SEMC_D0_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D0_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D0_CHANNEL 0U /*!< SEMC DATA channel: 00 */ +#define BOARD_INITSDRAM_SEMC_D0_PIN_NAME GPIO_EMC_00 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D0_LABEL "SEMC_D0" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D0_NAME "SEMC_D0" /*!< Identifier name */ + +/* GPIO_EMC_01 (coord F3), SEMC_D1 */ +#define BOARD_INITSDRAM_SEMC_D1_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D1_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D1_CHANNEL 1U /*!< SEMC DATA channel: 01 */ +#define BOARD_INITSDRAM_SEMC_D1_PIN_NAME GPIO_EMC_01 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D1_LABEL "SEMC_D1" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D1_NAME "SEMC_D1" /*!< Identifier name */ + +/* GPIO_EMC_02 (coord F4), SEMC_D2 */ +#define BOARD_INITSDRAM_SEMC_D2_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D2_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D2_CHANNEL 2U /*!< SEMC DATA channel: 02 */ +#define BOARD_INITSDRAM_SEMC_D2_PIN_NAME GPIO_EMC_02 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D2_LABEL "SEMC_D2" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D2_NAME "SEMC_D2" /*!< Identifier name */ + +/* GPIO_EMC_03 (coord G4), SEMC_D3 */ +#define BOARD_INITSDRAM_SEMC_D3_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D3_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D3_CHANNEL 3U /*!< SEMC DATA channel: 03 */ +#define BOARD_INITSDRAM_SEMC_D3_PIN_NAME GPIO_EMC_03 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D3_LABEL "SEMC_D3" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D3_NAME "SEMC_D3" /*!< Identifier name */ + +/* GPIO_EMC_04 (coord F2), SEMC_D4 */ +#define BOARD_INITSDRAM_SEMC_D4_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D4_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D4_CHANNEL 4U /*!< SEMC DATA channel: 04 */ +#define BOARD_INITSDRAM_SEMC_D4_PIN_NAME GPIO_EMC_04 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D4_LABEL "SEMC_D4" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D4_NAME "SEMC_D4" /*!< Identifier name */ + +/* GPIO_EMC_05 (coord G5), SEMC_D5 */ +#define BOARD_INITSDRAM_SEMC_D5_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D5_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D5_CHANNEL 5U /*!< SEMC DATA channel: 05 */ +#define BOARD_INITSDRAM_SEMC_D5_PIN_NAME GPIO_EMC_05 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D5_LABEL "SEMC_D5" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D5_NAME "SEMC_D5" /*!< Identifier name */ + +/* GPIO_EMC_06 (coord H5), SEMC_D6 */ +#define BOARD_INITSDRAM_SEMC_D6_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D6_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D6_CHANNEL 6U /*!< SEMC DATA channel: 06 */ +#define BOARD_INITSDRAM_SEMC_D6_PIN_NAME GPIO_EMC_06 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D6_LABEL "SEMC_D6" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D6_NAME "SEMC_D6" /*!< Identifier name */ + +/* GPIO_EMC_07 (coord H4), SEMC_D7 */ +#define BOARD_INITSDRAM_SEMC_D7_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D7_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D7_CHANNEL 7U /*!< SEMC DATA channel: 07 */ +#define BOARD_INITSDRAM_SEMC_D7_PIN_NAME GPIO_EMC_07 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D7_LABEL "SEMC_D7" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D7_NAME "SEMC_D7" /*!< Identifier name */ + +/* GPIO_EMC_30 (coord C6), SEMC_D8 */ +#define BOARD_INITSDRAM_SEMC_D8_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D8_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D8_CHANNEL 8U /*!< SEMC DATA channel: 08 */ +#define BOARD_INITSDRAM_SEMC_D8_PIN_NAME GPIO_EMC_30 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D8_LABEL "SEMC_D8" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D8_NAME "SEMC_D8" /*!< Identifier name */ + +/* GPIO_EMC_31 (coord C5), SEMC_D9 */ +#define BOARD_INITSDRAM_SEMC_D9_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D9_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D9_CHANNEL 9U /*!< SEMC DATA channel: 09 */ +#define BOARD_INITSDRAM_SEMC_D9_PIN_NAME GPIO_EMC_31 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D9_LABEL "SEMC_D9" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D9_NAME "SEMC_D9" /*!< Identifier name */ + +/* GPIO_EMC_32 (coord D5), SEMC_D10 */ +#define BOARD_INITSDRAM_SEMC_D10_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D10_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D10_CHANNEL 10U /*!< SEMC DATA channel: 10 */ +#define BOARD_INITSDRAM_SEMC_D10_PIN_NAME GPIO_EMC_32 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D10_LABEL "SEMC_D10" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D10_NAME "SEMC_D10" /*!< Identifier name */ + +/* GPIO_EMC_33 (coord C4), SEMC_D11 */ +#define BOARD_INITSDRAM_SEMC_D11_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D11_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D11_CHANNEL 11U /*!< SEMC DATA channel: 11 */ +#define BOARD_INITSDRAM_SEMC_D11_PIN_NAME GPIO_EMC_33 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D11_LABEL "SEMC_D11" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D11_NAME "SEMC_D11" /*!< Identifier name */ + +/* GPIO_EMC_34 (coord D4), SEMC_D12 */ +#define BOARD_INITSDRAM_SEMC_D12_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D12_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D12_CHANNEL 12U /*!< SEMC DATA channel: 12 */ +#define BOARD_INITSDRAM_SEMC_D12_PIN_NAME GPIO_EMC_34 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D12_LABEL "SEMC_D12" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D12_NAME "SEMC_D12" /*!< Identifier name */ + +/* GPIO_EMC_35 (coord E5), SEMC_D13 */ +#define BOARD_INITSDRAM_SEMC_D13_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D13_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D13_CHANNEL 13U /*!< SEMC DATA channel: 13 */ +#define BOARD_INITSDRAM_SEMC_D13_PIN_NAME GPIO_EMC_35 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D13_LABEL "SEMC_D13" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D13_NAME "SEMC_D13" /*!< Identifier name */ + +/* GPIO_EMC_36 (coord C3), SEMC_D14 */ +#define BOARD_INITSDRAM_SEMC_D14_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D14_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D14_CHANNEL 14U /*!< SEMC DATA channel: 14 */ +#define BOARD_INITSDRAM_SEMC_D14_PIN_NAME GPIO_EMC_36 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D14_LABEL "SEMC_D14" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D14_NAME "SEMC_D14" /*!< Identifier name */ + +/* GPIO_EMC_37 (coord E4), SEMC_D15 */ +#define BOARD_INITSDRAM_SEMC_D15_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_D15_SIGNAL DATA /*!< SEMC signal: DATA */ +#define BOARD_INITSDRAM_SEMC_D15_CHANNEL 15U /*!< SEMC DATA channel: 15 */ +#define BOARD_INITSDRAM_SEMC_D15_PIN_NAME GPIO_EMC_37 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_D15_LABEL "SEMC_D15" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_D15_NAME "SEMC_D15" /*!< Identifier name */ + +/* GPIO_EMC_08 (coord H3), SEMC_DM0 */ +#define BOARD_INITSDRAM_SEMC_DM0_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_DM0_SIGNAL DM /*!< SEMC signal: DM */ +#define BOARD_INITSDRAM_SEMC_DM0_CHANNEL 0U /*!< SEMC DM channel: 0 */ +#define BOARD_INITSDRAM_SEMC_DM0_PIN_NAME GPIO_EMC_08 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_DM0_LABEL "SEMC_DM0" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_DM0_NAME "SEMC_DM0" /*!< Identifier name */ + +/* GPIO_EMC_38 (coord D6), SEMC_DM1 */ +#define BOARD_INITSDRAM_SEMC_DM1_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_DM1_SIGNAL DM /*!< SEMC signal: DM */ +#define BOARD_INITSDRAM_SEMC_DM1_CHANNEL 1U /*!< SEMC DM channel: 1 */ +#define BOARD_INITSDRAM_SEMC_DM1_PIN_NAME GPIO_EMC_38 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_DM1_LABEL "SEMC_DM1" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_DM1_NAME "SEMC_DM1" /*!< Identifier name */ + +/* GPIO_EMC_25 (coord D2), SEMC_RAS */ +#define BOARD_INITSDRAM_SEMC_RAS_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_RAS_SIGNAL semc_ras /*!< SEMC signal: semc_ras */ +#define BOARD_INITSDRAM_SEMC_RAS_PIN_NAME GPIO_EMC_25 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_RAS_LABEL "SEMC_RAS" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_RAS_NAME "SEMC_RAS" /*!< Identifier name */ + +/* GPIO_EMC_28 (coord D1), SEMC_WE */ +#define BOARD_INITSDRAM_SEMC_WE_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_SEMC_WE_SIGNAL semc_we /*!< SEMC signal: semc_we */ +#define BOARD_INITSDRAM_SEMC_WE_PIN_NAME GPIO_EMC_28 /*!< Pin name */ +#define BOARD_INITSDRAM_SEMC_WE_LABEL "SEMC_WE" /*!< Label */ +#define BOARD_INITSDRAM_SEMC_WE_NAME "SEMC_WE" /*!< Identifier name */ + +/* GPIO_EMC_41 (coord C7), ENET_MDIO */ +#define BOARD_INITSDRAM_ENET_MDIO_PERIPHERAL SEMC /*!< Device name: SEMC */ +#define BOARD_INITSDRAM_ENET_MDIO_SIGNAL CSX /*!< SEMC signal: CSX */ +#define BOARD_INITSDRAM_ENET_MDIO_CHANNEL 0U /*!< SEMC CSX channel: 0 */ +#define BOARD_INITSDRAM_ENET_MDIO_PIN_NAME GPIO_EMC_41 /*!< Pin name */ +#define BOARD_INITSDRAM_ENET_MDIO_LABEL "ENET_MDIO" /*!< Label */ +#define BOARD_INITSDRAM_ENET_MDIO_NAME "ENET_MDIO" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSDRAM(void); + +/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */ +#define BOARD_INITCSI_CSI_D9_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D9_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D9_CHANNEL 9U /*!< CSI csi_data channel: 09 */ +#define BOARD_INITCSI_CSI_D9_PIN_NAME GPIO_AD_B1_08 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D9_LABEL "AUD_INT/CSI_D9//J35[13]/J22[4]" /*!< Label */ +#define BOARD_INITCSI_CSI_D9_NAME "CSI_D9" /*!< Identifier name */ + +/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */ +#define BOARD_INITCSI_CSI_D8_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D8_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D8_CHANNEL 8U /*!< CSI csi_data channel: 08 */ +#define BOARD_INITCSI_CSI_D8_PIN_NAME GPIO_AD_B1_09 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D8_LABEL "SAI1_MCLK/CSI_D8/J35[11]" /*!< Label */ +#define BOARD_INITCSI_CSI_D8_NAME "CSI_D8" /*!< Identifier name */ + +/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */ +#define BOARD_INITCSI_CSI_D7_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D7_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D7_CHANNEL 7U /*!< CSI csi_data channel: 07 */ +#define BOARD_INITCSI_CSI_D7_PIN_NAME GPIO_AD_B1_10 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D7_LABEL "SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1]" /*!< Label */ +#define BOARD_INITCSI_CSI_D7_NAME "CSI_D7" /*!< Identifier name */ + +/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */ +#define BOARD_INITCSI_CSI_D6_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D6_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D6_CHANNEL 6U /*!< CSI csi_data channel: 06 */ +#define BOARD_INITCSI_CSI_D6_PIN_NAME GPIO_AD_B1_11 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D6_LABEL "SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2]" /*!< Label */ +#define BOARD_INITCSI_CSI_D6_NAME "CSI_D6" /*!< Identifier name */ + +/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */ +#define BOARD_INITCSI_CSI_D5_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D5_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D5_CHANNEL 5U /*!< CSI csi_data channel: 05 */ +#define BOARD_INITCSI_CSI_D5_PIN_NAME GPIO_AD_B1_12 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D5_LABEL "SAI1_RXD/CSI_D5/J35[5]/U13[16]" /*!< Label */ +#define BOARD_INITCSI_CSI_D5_NAME "CSI_D5" /*!< Identifier name */ + +/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */ +#define BOARD_INITCSI_CSI_D4_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D4_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D4_CHANNEL 4U /*!< CSI csi_data channel: 04 */ +#define BOARD_INITCSI_CSI_D4_PIN_NAME GPIO_AD_B1_13 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D4_LABEL "SAI1_TXD/CSI_D4/J35[3]/U13[14]" /*!< Label */ +#define BOARD_INITCSI_CSI_D4_NAME "CSI_D4" /*!< Identifier name */ + +/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */ +#define BOARD_INITCSI_CSI_D2_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D2_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D2_CHANNEL 2U /*!< CSI csi_data channel: 02 */ +#define BOARD_INITCSI_CSI_D2_PIN_NAME GPIO_AD_B1_15 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D2_LABEL "SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13]" /*!< Label */ +#define BOARD_INITCSI_CSI_D2_NAME "CSI_D2" /*!< Identifier name */ + +/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */ +#define BOARD_INITCSI_CSI_D3_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_D3_SIGNAL csi_data /*!< CSI signal: csi_data */ +#define BOARD_INITCSI_CSI_D3_CHANNEL 3U /*!< CSI csi_data channel: 03 */ +#define BOARD_INITCSI_CSI_D3_PIN_NAME GPIO_AD_B1_14 /*!< Pin name */ +#define BOARD_INITCSI_CSI_D3_LABEL "SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12]" /*!< Label */ +#define BOARD_INITCSI_CSI_D3_NAME "CSI_D3" /*!< Identifier name */ + +/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */ +#define BOARD_INITCSI_CSI_PIXCLK_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_PIXCLK_SIGNAL csi_pixclk /*!< CSI signal: csi_pixclk */ +#define BOARD_INITCSI_CSI_PIXCLK_PIN_NAME GPIO_AD_B1_04 /*!< Pin name */ +#define BOARD_INITCSI_CSI_PIXCLK_LABEL "CSI_PIXCLK/J35[8]/J23[3]" /*!< Label */ +#define BOARD_INITCSI_CSI_PIXCLK_NAME "CSI_PIXCLK" /*!< Identifier name */ + +/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */ +#define BOARD_INITCSI_CSI_MCLK_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_MCLK_SIGNAL csi_mclk /*!< CSI signal: csi_mclk */ +#define BOARD_INITCSI_CSI_MCLK_PIN_NAME GPIO_AD_B1_05 /*!< Pin name */ +#define BOARD_INITCSI_CSI_MCLK_LABEL "CSI_MCLK/J35[12]/J23[4]" /*!< Label */ +#define BOARD_INITCSI_CSI_MCLK_NAME "CSI_MCLK" /*!< Identifier name */ + +/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */ +#define BOARD_INITCSI_CSI_VSYNC_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_VSYNC_SIGNAL csi_vsync /*!< CSI signal: csi_vsync */ +#define BOARD_INITCSI_CSI_VSYNC_PIN_NAME GPIO_AD_B1_06 /*!< Pin name */ +#define BOARD_INITCSI_CSI_VSYNC_LABEL "CSI_VSYNC/J35[18]/J22[2]/UART_TX" /*!< Label */ +#define BOARD_INITCSI_CSI_VSYNC_NAME "CSI_VSYNC" /*!< Identifier name */ + +/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */ +#define BOARD_INITCSI_CSI_HSYNC_PERIPHERAL CSI /*!< Device name: CSI */ +#define BOARD_INITCSI_CSI_HSYNC_SIGNAL csi_hsync /*!< CSI signal: csi_hsync */ +#define BOARD_INITCSI_CSI_HSYNC_PIN_NAME GPIO_AD_B1_07 /*!< Pin name */ +#define BOARD_INITCSI_CSI_HSYNC_LABEL "CSI_HSYNC/J35[16]/J22[1]/UART_RX" /*!< Label */ +#define BOARD_INITCSI_CSI_HSYNC_NAME "CSI_HSYNC" /*!< Identifier name */ + +/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */ +#define BOARD_INITCSI_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Device name: LPI2C1 */ +#define BOARD_INITCSI_CSI_I2C_SCL_SIGNAL SCL /*!< LPI2C1 signal: SCL */ +#define BOARD_INITCSI_CSI_I2C_SCL_PIN_NAME GPIO_AD_B1_00 /*!< Pin name */ +#define BOARD_INITCSI_CSI_I2C_SCL_LABEL "I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4]" /*!< Label */ +#define BOARD_INITCSI_CSI_I2C_SCL_NAME "CSI_I2C_SCL" /*!< Identifier name */ + +/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */ +#define BOARD_INITCSI_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Device name: LPI2C1 */ +#define BOARD_INITCSI_CSI_I2C_SDA_SIGNAL SDA /*!< LPI2C1 signal: SDA */ +#define BOARD_INITCSI_CSI_I2C_SDA_PIN_NAME GPIO_AD_B1_01 /*!< Pin name */ +#define BOARD_INITCSI_CSI_I2C_SDA_LABEL "I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6]" /*!< Label */ +#define BOARD_INITCSI_CSI_I2C_SDA_NAME "CSI_I2C_SDA" /*!< Identifier name */ + +/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */ +#define BOARD_INITCSI_CSI_PWDN_GPIO GPIO1 /*!< GPIO device name: GPIO1 */ +#define BOARD_INITCSI_CSI_PWDN_PORT GPIO1 /*!< PORT device name: GPIO1 */ +#define BOARD_INITCSI_CSI_PWDN_GPIO_PIN 4U /*!< GPIO1 pin index: 4 */ +#define BOARD_INITCSI_CSI_PWDN_PIN_NAME GPIO_AD_B0_04 /*!< Pin name */ +#define BOARD_INITCSI_CSI_PWDN_LABEL "CSI_PWDN/J35[17]/BOOT_MODE[0]" /*!< Label */ +#define BOARD_INITCSI_CSI_PWDN_NAME "CSI_PWDN" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitCSI(void); + +/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */ +#define BOARD_INITLCD_LCDIF_D0_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D0_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D0_CHANNEL 0U /*!< LCDIF lcdif_data channel: 00 */ +#define BOARD_INITLCD_LCDIF_D0_PIN_NAME GPIO_B0_04 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D0_LABEL "LCDIF_D0/BT_CFG[0]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D0_NAME "LCDIF_D0" /*!< Identifier name */ + +/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */ +#define BOARD_INITLCD_LCDIF_D1_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D1_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D1_CHANNEL 1U /*!< LCDIF lcdif_data channel: 01 */ +#define BOARD_INITLCD_LCDIF_D1_PIN_NAME GPIO_B0_05 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D1_LABEL "LCDIF_D1/BT_CFG[1]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D1_NAME "LCDIF_D1" /*!< Identifier name */ + +/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */ +#define BOARD_INITLCD_LCDIF_D2_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D2_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D2_CHANNEL 2U /*!< LCDIF lcdif_data channel: 02 */ +#define BOARD_INITLCD_LCDIF_D2_PIN_NAME GPIO_B0_06 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D2_LABEL "LCDIF_D2/BT_CFG[2]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D2_NAME "LCDIF_D2" /*!< Identifier name */ + +/* GPIO_B0_00 (coord D7), LCDIF_CLK */ +#define BOARD_INITLCD_LCDIF_CLK_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_CLK_SIGNAL lcdif_clk /*!< LCDIF signal: lcdif_clk */ +#define BOARD_INITLCD_LCDIF_CLK_PIN_NAME GPIO_B0_00 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_CLK_LABEL "LCDIF_CLK" /*!< Label */ +#define BOARD_INITLCD_LCDIF_CLK_NAME "LCDIF_CLK" /*!< Identifier name */ + +/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */ +#define BOARD_INITLCD_LCDIF_D3_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D3_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D3_CHANNEL 3U /*!< LCDIF lcdif_data channel: 03 */ +#define BOARD_INITLCD_LCDIF_D3_PIN_NAME GPIO_B0_07 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D3_LABEL "LCDIF_D3/BT_CFG[3]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D3_NAME "LCDIF_D3" /*!< Identifier name */ + +/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */ +#define BOARD_INITLCD_LCDIF_D4_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D4_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D4_CHANNEL 4U /*!< LCDIF lcdif_data channel: 04 */ +#define BOARD_INITLCD_LCDIF_D4_PIN_NAME GPIO_B0_08 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D4_LABEL "LCDIF_D4/BT_CFG[4]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D4_NAME "LCDIF_D4" /*!< Identifier name */ + +/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */ +#define BOARD_INITLCD_LCDIF_D5_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D5_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D5_CHANNEL 5U /*!< LCDIF lcdif_data channel: 05 */ +#define BOARD_INITLCD_LCDIF_D5_PIN_NAME GPIO_B0_09 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D5_LABEL "LCDIF_D5/BT_CFG[5]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D5_NAME "LCDIF_D5" /*!< Identifier name */ + +/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */ +#define BOARD_INITLCD_LCDIF_D6_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D6_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D6_CHANNEL 6U /*!< LCDIF lcdif_data channel: 06 */ +#define BOARD_INITLCD_LCDIF_D6_PIN_NAME GPIO_B0_10 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D6_LABEL "LCDIF_D6/BT_CFG[6]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D6_NAME "LCDIF_D6" /*!< Identifier name */ + +/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */ +#define BOARD_INITLCD_LCDIF_D7_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D7_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D7_CHANNEL 7U /*!< LCDIF lcdif_data channel: 07 */ +#define BOARD_INITLCD_LCDIF_D7_PIN_NAME GPIO_B0_11 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D7_LABEL "LCDIF_D7/BT_CFG[7]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D7_NAME "LCDIF_D7" /*!< Identifier name */ + +/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */ +#define BOARD_INITLCD_LCDIF_D8_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D8_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D8_CHANNEL 8U /*!< LCDIF lcdif_data channel: 08 */ +#define BOARD_INITLCD_LCDIF_D8_PIN_NAME GPIO_B0_12 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D8_LABEL "LCDIF_D8/BT_CFG[8]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D8_NAME "LCDIF_D8" /*!< Identifier name */ + +/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */ +#define BOARD_INITLCD_LCDIF_D9_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D9_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D9_CHANNEL 9U /*!< LCDIF lcdif_data channel: 09 */ +#define BOARD_INITLCD_LCDIF_D9_PIN_NAME GPIO_B0_13 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D9_LABEL "LCDIF_D9/BT_CFG[9]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D9_NAME "LCDIF_D9" /*!< Identifier name */ + +/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */ +#define BOARD_INITLCD_LCDIF_D10_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D10_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D10_CHANNEL 10U /*!< LCDIF lcdif_data channel: 10 */ +#define BOARD_INITLCD_LCDIF_D10_PIN_NAME GPIO_B0_14 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D10_LABEL "LCDIF_D10/BT_CFG[10]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D10_NAME "LCDIF_D10" /*!< Identifier name */ + +/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */ +#define BOARD_INITLCD_LCDIF_D11_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D11_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D11_CHANNEL 11U /*!< LCDIF lcdif_data channel: 11 */ +#define BOARD_INITLCD_LCDIF_D11_PIN_NAME GPIO_B0_15 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D11_LABEL "LCDIF_D11/BT_CFG[11]" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D11_NAME "LCDIF_D11" /*!< Identifier name */ + +/* GPIO_B1_00 (coord A11), LCDIF_D12 */ +#define BOARD_INITLCD_LCDIF_D12_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D12_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D12_CHANNEL 12U /*!< LCDIF lcdif_data channel: 12 */ +#define BOARD_INITLCD_LCDIF_D12_PIN_NAME GPIO_B1_00 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D12_LABEL "LCDIF_D12" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D12_NAME "LCDIF_D12" /*!< Identifier name */ + +/* GPIO_B1_01 (coord B11), LCDIF_D13 */ +#define BOARD_INITLCD_LCDIF_D13_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D13_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D13_CHANNEL 13U /*!< LCDIF lcdif_data channel: 13 */ +#define BOARD_INITLCD_LCDIF_D13_PIN_NAME GPIO_B1_01 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D13_LABEL "LCDIF_D13" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D13_NAME "LCDIF_D13" /*!< Identifier name */ + +/* GPIO_B1_02 (coord C11), LCDIF_D14 */ +#define BOARD_INITLCD_LCDIF_D14_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D14_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D14_CHANNEL 14U /*!< LCDIF lcdif_data channel: 14 */ +#define BOARD_INITLCD_LCDIF_D14_PIN_NAME GPIO_B1_02 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D14_LABEL "LCDIF_D14" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D14_NAME "LCDIF_D14" /*!< Identifier name */ + +/* GPIO_B1_03 (coord D11), LCDIF_D15 */ +#define BOARD_INITLCD_LCDIF_D15_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_D15_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */ +#define BOARD_INITLCD_LCDIF_D15_CHANNEL 15U /*!< LCDIF lcdif_data channel: 15 */ +#define BOARD_INITLCD_LCDIF_D15_PIN_NAME GPIO_B1_03 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_D15_LABEL "LCDIF_D15" /*!< Label */ +#define BOARD_INITLCD_LCDIF_D15_NAME "LCDIF_D15" /*!< Identifier name */ + +/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ +#define BOARD_INITLCD_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< LCDIF signal: lcdif_enable */ +#define BOARD_INITLCD_LCDIF_ENABLE_PIN_NAME GPIO_B0_01 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_ENABLE_LABEL "LCDIF_ENABLE" /*!< Label */ +#define BOARD_INITLCD_LCDIF_ENABLE_NAME "LCDIF_ENABLE" /*!< Identifier name */ + +/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */ +#define BOARD_INITLCD_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< LCDIF signal: lcdif_hsync */ +#define BOARD_INITLCD_LCDIF_HSYNC_PIN_NAME GPIO_B0_02 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_HSYNC_LABEL "LCDIF_HSYNC" /*!< Label */ +#define BOARD_INITLCD_LCDIF_HSYNC_NAME "LCDIF_HSYNC" /*!< Identifier name */ + +/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ +#define BOARD_INITLCD_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Device name: LCDIF */ +#define BOARD_INITLCD_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< LCDIF signal: lcdif_vsync */ +#define BOARD_INITLCD_LCDIF_VSYNC_PIN_NAME GPIO_B0_03 /*!< Pin name */ +#define BOARD_INITLCD_LCDIF_VSYNC_LABEL "LCDIF_VSYNC" /*!< Label */ +#define BOARD_INITLCD_LCDIF_VSYNC_NAME "LCDIF_VSYNC" /*!< Identifier name */ + +/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */ +#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO device name: GPIO2 */ +#define BOARD_INITLCD_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT device name: GPIO2 */ +#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO2 pin index: 31 */ +#define BOARD_INITLCD_BACKLIGHT_CTL_PIN_NAME GPIO_B1_15 /*!< Pin name */ +#define BOARD_INITLCD_BACKLIGHT_CTL_LABEL "USB_HOST_PWR/BACKLIGHT_CTL" /*!< Label */ +#define BOARD_INITLCD_BACKLIGHT_CTL_NAME "BACKLIGHT_CTL" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLCD(void); + +/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */ +#define BOARD_INITCAN_CAN2_TX_PERIPHERAL CAN2 /*!< Device name: CAN2 */ +#define BOARD_INITCAN_CAN2_TX_SIGNAL TX /*!< CAN2 signal: TX */ +#define BOARD_INITCAN_CAN2_TX_PIN_NAME GPIO_AD_B0_14 /*!< Pin name */ +#define BOARD_INITCAN_CAN2_TX_LABEL "CAN2_TX/U12[1]" /*!< Label */ +#define BOARD_INITCAN_CAN2_TX_NAME "CAN2_TX" /*!< Identifier name */ + +/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */ +#define BOARD_INITCAN_CAN2_RX_PERIPHERAL CAN2 /*!< Device name: CAN2 */ +#define BOARD_INITCAN_CAN2_RX_SIGNAL RX /*!< CAN2 signal: RX */ +#define BOARD_INITCAN_CAN2_RX_PIN_NAME GPIO_AD_B0_15 /*!< Pin name */ +#define BOARD_INITCAN_CAN2_RX_LABEL "CAN2_RX/U12[4]" /*!< Label */ +#define BOARD_INITCAN_CAN2_RX_NAME "CAN2_RX" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitCAN(void); + +/* GPIO_EMC_40 (coord A7), ENET_MDC */ +#define BOARD_INITENET_ENET_MDC_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_MDC_SIGNAL enet_mdc /*!< ENET signal: enet_mdc */ +#define BOARD_INITENET_ENET_MDC_PIN_NAME GPIO_EMC_40 /*!< Pin name */ +#define BOARD_INITENET_ENET_MDC_LABEL "ENET_MDC" /*!< Label */ +#define BOARD_INITENET_ENET_MDC_NAME "ENET_MDC" /*!< Identifier name */ + +/* GPIO_EMC_41 (coord C7), ENET_MDIO */ +#define BOARD_INITENET_ENET_MDIO_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_MDIO_SIGNAL enet_mdio /*!< ENET signal: enet_mdio */ +#define BOARD_INITENET_ENET_MDIO_PIN_NAME GPIO_EMC_41 /*!< Pin name */ +#define BOARD_INITENET_ENET_MDIO_LABEL "ENET_MDIO" /*!< Label */ +#define BOARD_INITENET_ENET_MDIO_NAME "ENET_MDIO" /*!< Identifier name */ + +/* GPIO_B1_10 (coord B13), ENET_TX_CLK */ +#define BOARD_INITENET_ENET_TX_CLK_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< ENET signal: enet_ref_clk */ +#define BOARD_INITENET_ENET_TX_CLK_PIN_NAME GPIO_B1_10 /*!< Pin name */ +#define BOARD_INITENET_ENET_TX_CLK_LABEL "ENET_TX_CLK" /*!< Label */ +#define BOARD_INITENET_ENET_TX_CLK_NAME "ENET_TX_CLK" /*!< Identifier name */ + +/* GPIO_B1_04 (coord E12), ENET_RXD0 */ +#define BOARD_INITENET_ENET_RXD0_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_RXD0_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */ +#define BOARD_INITENET_ENET_RXD0_CHANNEL 0U /*!< ENET enet_rx_data channel: 0 */ +#define BOARD_INITENET_ENET_RXD0_PIN_NAME GPIO_B1_04 /*!< Pin name */ +#define BOARD_INITENET_ENET_RXD0_LABEL "ENET_RXD0" /*!< Label */ +#define BOARD_INITENET_ENET_RXD0_NAME "ENET_RXD0" /*!< Identifier name */ + +/* GPIO_B1_05 (coord D12), ENET_RXD1 */ +#define BOARD_INITENET_ENET_RXD1_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_RXD1_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */ +#define BOARD_INITENET_ENET_RXD1_CHANNEL 1U /*!< ENET enet_rx_data channel: 1 */ +#define BOARD_INITENET_ENET_RXD1_PIN_NAME GPIO_B1_05 /*!< Pin name */ +#define BOARD_INITENET_ENET_RXD1_LABEL "ENET_RXD1" /*!< Label */ +#define BOARD_INITENET_ENET_RXD1_NAME "ENET_RXD1" /*!< Identifier name */ + +/* GPIO_B1_06 (coord C12), ENET_CRS_DV */ +#define BOARD_INITENET_ENET_CRS_DV_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_CRS_DV_SIGNAL enet_rx_en /*!< ENET signal: enet_rx_en */ +#define BOARD_INITENET_ENET_CRS_DV_PIN_NAME GPIO_B1_06 /*!< Pin name */ +#define BOARD_INITENET_ENET_CRS_DV_LABEL "ENET_CRS_DV" /*!< Label */ +#define BOARD_INITENET_ENET_CRS_DV_NAME "ENET_CRS_DV" /*!< Identifier name */ + +/* GPIO_B1_11 (coord C13), ENET_RXER */ +#define BOARD_INITENET_ENET_RXER_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_RXER_SIGNAL enet_rx_er /*!< ENET signal: enet_rx_er */ +#define BOARD_INITENET_ENET_RXER_PIN_NAME GPIO_B1_11 /*!< Pin name */ +#define BOARD_INITENET_ENET_RXER_LABEL "ENET_RXER" /*!< Label */ +#define BOARD_INITENET_ENET_RXER_NAME "ENET_RXER" /*!< Identifier name */ + +/* GPIO_B1_07 (coord B12), ENET_TXD0 */ +#define BOARD_INITENET_ENET_TXD0_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_TXD0_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */ +#define BOARD_INITENET_ENET_TXD0_CHANNEL 0U /*!< ENET enet_tx_data channel: 0 */ +#define BOARD_INITENET_ENET_TXD0_PIN_NAME GPIO_B1_07 /*!< Pin name */ +#define BOARD_INITENET_ENET_TXD0_LABEL "ENET_TXD0" /*!< Label */ +#define BOARD_INITENET_ENET_TXD0_NAME "ENET_TXD0" /*!< Identifier name */ + +/* GPIO_B1_08 (coord A12), ENET_TXD1 */ +#define BOARD_INITENET_ENET_TXD1_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_TXD1_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */ +#define BOARD_INITENET_ENET_TXD1_CHANNEL 1U /*!< ENET enet_tx_data channel: 1 */ +#define BOARD_INITENET_ENET_TXD1_PIN_NAME GPIO_B1_08 /*!< Pin name */ +#define BOARD_INITENET_ENET_TXD1_LABEL "ENET_TXD1" /*!< Label */ +#define BOARD_INITENET_ENET_TXD1_NAME "ENET_TXD1" /*!< Identifier name */ + +/* GPIO_B1_09 (coord A13), ENET_TXEN */ +#define BOARD_INITENET_ENET_TXEN_PERIPHERAL ENET /*!< Device name: ENET */ +#define BOARD_INITENET_ENET_TXEN_SIGNAL enet_tx_en /*!< ENET signal: enet_tx_en */ +#define BOARD_INITENET_ENET_TXEN_PIN_NAME GPIO_B1_09 /*!< Pin name */ +#define BOARD_INITENET_ENET_TXEN_LABEL "ENET_TXEN" /*!< Label */ +#define BOARD_INITENET_ENET_TXEN_NAME "ENET_TXEN" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitENET(void); + +/* GPIO_SD_B0_05 (coord J2), SD1_D3 */ +#define BOARD_INITUSDHC_SD1_D3_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */ +#define BOARD_INITUSDHC_SD1_D3_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */ +#define BOARD_INITUSDHC_SD1_D3_CHANNEL 3U /*!< USDHC1 usdhc_data channel: 3 */ +#define BOARD_INITUSDHC_SD1_D3_PIN_NAME GPIO_SD_B0_05 /*!< Pin name */ +#define BOARD_INITUSDHC_SD1_D3_LABEL "SD1_D3" /*!< Label */ +#define BOARD_INITUSDHC_SD1_D3_NAME "SD1_D3" /*!< Identifier name */ + +/* GPIO_SD_B0_04 (coord H2), SD1_D2 */ +#define BOARD_INITUSDHC_SD1_D2_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */ +#define BOARD_INITUSDHC_SD1_D2_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */ +#define BOARD_INITUSDHC_SD1_D2_CHANNEL 2U /*!< USDHC1 usdhc_data channel: 2 */ +#define BOARD_INITUSDHC_SD1_D2_PIN_NAME GPIO_SD_B0_04 /*!< Pin name */ +#define BOARD_INITUSDHC_SD1_D2_LABEL "SD1_D2" /*!< Label */ +#define BOARD_INITUSDHC_SD1_D2_NAME "SD1_D2" /*!< Identifier name */ + +/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */ +#define BOARD_INITUSDHC_SD1_D1_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */ +#define BOARD_INITUSDHC_SD1_D1_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */ +#define BOARD_INITUSDHC_SD1_D1_CHANNEL 1U /*!< USDHC1 usdhc_data channel: 1 */ +#define BOARD_INITUSDHC_SD1_D1_PIN_NAME GPIO_SD_B0_03 /*!< Pin name */ +#define BOARD_INITUSDHC_SD1_D1_LABEL "SD1_D1/J24[5]/SPI_MISO" /*!< Label */ +#define BOARD_INITUSDHC_SD1_D1_NAME "SD1_D1" /*!< Identifier name */ + +/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */ +#define BOARD_INITUSDHC_SD1_D0_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */ +#define BOARD_INITUSDHC_SD1_D0_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */ +#define BOARD_INITUSDHC_SD1_D0_CHANNEL 0U /*!< USDHC1 usdhc_data channel: 0 */ +#define BOARD_INITUSDHC_SD1_D0_PIN_NAME GPIO_SD_B0_02 /*!< Pin name */ +#define BOARD_INITUSDHC_SD1_D0_LABEL "SD1_D0/J24[4]/SPI_MOSI/PWM" /*!< Label */ +#define BOARD_INITUSDHC_SD1_D0_NAME "SD1_D0" /*!< Identifier name */ + +/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */ +#define BOARD_INITUSDHC_SD1_CMD_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */ +#define BOARD_INITUSDHC_SD1_CMD_SIGNAL usdhc_cmd /*!< USDHC1 signal: usdhc_cmd */ +#define BOARD_INITUSDHC_SD1_CMD_PIN_NAME GPIO_SD_B0_00 /*!< Pin name */ +#define BOARD_INITUSDHC_SD1_CMD_LABEL "SD1_CMD/J24[6]" /*!< Label */ +#define BOARD_INITUSDHC_SD1_CMD_NAME "SD1_CMD" /*!< Identifier name */ + +/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */ +#define BOARD_INITUSDHC_SD1_CLK_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */ +#define BOARD_INITUSDHC_SD1_CLK_SIGNAL usdhc_clk /*!< USDHC1 signal: usdhc_clk */ +#define BOARD_INITUSDHC_SD1_CLK_PIN_NAME GPIO_SD_B0_01 /*!< Pin name */ +#define BOARD_INITUSDHC_SD1_CLK_LABEL "SD1_CLK/J24[3]" /*!< Label */ +#define BOARD_INITUSDHC_SD1_CLK_NAME "SD1_CLK" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSDHC(void); + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< FLEXSPI signal: FLEXSPI_A_SCLK */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_PIN_NAME GPIO_SD_B1_07 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_LABEL "FlexSPI_CLK" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_NAME "FlexSPI_CLK" /*!< Identifier name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_PIN_NAME GPIO_SD_B1_10 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_LABEL "FlexSPI_D2_A" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_NAME "FlexSPI_D2_A" /*!< Identifier name */ + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_PIN_NAME GPIO_SD_B1_08 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_LABEL "FlexSPI_D0_A" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_NAME "FlexSPI_D0_A" /*!< Identifier name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_PIN_NAME GPIO_SD_B1_09 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_LABEL "FlexSPI_D1_A" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_NAME "FlexSPI_D1_A" /*!< Identifier name */ + +/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_SIGNAL FLEXSPI_B_DATA3 /*!< FLEXSPI signal: FLEXSPI_B_DATA3 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_PIN_NAME GPIO_SD_B1_00 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_LABEL "FlexSPI_D3_B" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_NAME "FlexSPI_D3_B" /*!< Identifier name */ + +/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_SIGNAL FLEXSPI_B_DATA2 /*!< FLEXSPI signal: FLEXSPI_B_DATA2 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_PIN_NAME GPIO_SD_B1_01 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_LABEL "FlexSPI_D2_B" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_NAME "FlexSPI_D2_B" /*!< Identifier name */ + +/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_SIGNAL FLEXSPI_B_DATA1 /*!< FLEXSPI signal: FLEXSPI_B_DATA1 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_PIN_NAME GPIO_SD_B1_02 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_LABEL "FlexSPI_D1_B" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_NAME "FlexSPI_D1_B" /*!< Identifier name */ + +/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_SIGNAL FLEXSPI_B_DATA0 /*!< FLEXSPI signal: FLEXSPI_B_DATA0 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_PIN_NAME GPIO_SD_B1_03 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_LABEL "FlexSPI_D0_B" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_NAME "FlexSPI_D0_B" /*!< Identifier name */ + +/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_SIGNAL FLEXSPI_B_SCLK /*!< FLEXSPI signal: FLEXSPI_B_SCLK */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PIN_NAME GPIO_SD_B1_04 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_LABEL "FlexSPI_CLK_B" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_NAME "FlexSPI_CLK_B" /*!< Identifier name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +#define BOARD_INITHYPERFLASH_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */ +#define BOARD_INITHYPERFLASH_FlexSPI_SS0_PIN_NAME GPIO_SD_B1_06 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_SS0_LABEL "FlexSPI_SS0" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_SS0_NAME "FlexSPI_SS0" /*!< Identifier name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_PIN_NAME GPIO_SD_B1_11 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_LABEL "FlexSPI_D3_A" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_NAME "FlexSPI_D3_A" /*!< Identifier name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +#define BOARD_INITHYPERFLASH_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITHYPERFLASH_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< FLEXSPI signal: FLEXSPI_A_DQS */ +#define BOARD_INITHYPERFLASH_FlexSPI_DQS_PIN_NAME GPIO_SD_B1_05 /*!< Pin name */ +#define BOARD_INITHYPERFLASH_FlexSPI_DQS_LABEL "FlexSPI_DQS" /*!< Label */ +#define BOARD_INITHYPERFLASH_FlexSPI_DQS_NAME "FlexSPI_DQS" /*!< Identifier name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitHyperFlash(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/RT1060/results.md b/RT1060/results.md new file mode 100644 index 00000000..5c2efef3 --- /dev/null +++ b/RT1060/results.md @@ -0,0 +1,84 @@ +wolfCrypt Benchmark (block bytes 1024, min 1.0 sec each) + +------------------------------------------------------------------------------ + + wolfSSL version 4.5.0 + +------------------------------------------------------------------------------ + +wolfCrypt Benchmark (block bytes 1024, min 1.0 sec each) + +RNG 100 KB took 1.167 seconds, 85.690 KB/s + +AES-128-CBC-enc 10 MB took 1.002 seconds, 9.819 MB/s + +AES-128-CBC-dec 9 MB took 1.000 seconds, 9.497 MB/s + +AES-192-CBC-enc 9 MB took 1.000 seconds, 8.716 MB/s + +AES-192-CBC-dec 8 MB took 1.000 seconds, 8.496 MB/s + +AES-256-CBC-enc 8 MB took 1.002 seconds, 7.821 MB/s + +AES-256-CBC-dec 8 MB took 1.002 seconds, 7.626 MB/s + +AES-128-GCM-enc 2 MB took 1.003 seconds, 2.166 MB/s + +AES-128-GCM-dec 2 MB took 1.002 seconds, 2.169 MB/s + +AES-192-GCM-enc 2 MB took 1.011 seconds, 2.077 MB/s + +AES-192-GCM-dec 2 MB took 1.009 seconds, 2.081 MB/s + +AES-256-GCM-enc 2 MB took 1.001 seconds, 2.000 MB/s + +AES-256-GCM-dec 2 MB took 1.001 seconds, 2.000 MB/s + +CHACHA 26 MB took 1.000 seconds, 26.050 MB/s + +MD5 82 MB took 1.000 seconds, 82.104 MB/s + +SHA 37 MB took 1.000 seconds, 37.036 MB/s + +SHA-256 22 MB took 1.000 seconds, 22.168 MB/s + +SHA-512 8 MB took 1.001 seconds, 7.975 MB/s + +SHA3-224 9 MB took 1.001 seconds, 8.975 MB/s + +SHA3-256 8 MB took 1.001 seconds, 8.463 MB/s + +SHA3-384 7 MB took 1.000 seconds, 6.519 MB/s + +SHA3-512 5 MB took 1.004 seconds, 4.547 MB/s + +HMAC-MD5 81 MB took 1.000 seconds, 80.737 MB/s + +HMAC-SHA 36 MB took 1.000 seconds, 36.353 MB/s + +HMAC-SHA256 22 MB took 1.000 seconds, 21.924 MB/s + +HMAC-SHA512 8 MB took 1.002 seconds, 7.797 MB/s + +PBKDF2 2 KB took 1.007 seconds, 2.079 KB/s + +RSA 2048 public 222 ops took 1.007 sec, avg 4.536 ms, 220.457 ops/sec + +RSA 2048 private 4 ops took 1.327 sec, avg 331.750 ms, 3.014 ops/sec + +ECC 256 key gen 631 ops took 1.000 sec, avg 1.585 ms, 631.000 ops/sec + +ECDHE 256 agree 286 ops took 1.002 sec, avg 3.503 ms, 285.429 ops/sec + +ECDSA 256 sign 408 ops took 1.003 sec, avg 2.458 ms, 406.780 ops/sec + +ECDSA 256 verify 194 ops took 1.005 sec, avg 5.180 ms, 193.035 ops/sec + +ED 25519 key gen 20 ops took 1.004 sec, avg 50.200 ms, 19.920 ops/sec + +ED 25519 sign 20 ops took 1.024 sec, avg 51.200 ms, 19.531 ops/sec + +ED 25519 verify 10 ops took 1.055 sec, avg 105.500 ms, 9.479 ops/sec + +Benchmark complete + diff --git a/RT1060/tags b/RT1060/tags new file mode 100644 index 00000000..62ab6b10 --- /dev/null +++ b/RT1060/tags @@ -0,0 +1,868 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.9~svn20110310 // +ASMFLAGS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^ASMFLAGS=-D__STARTUP_CLEAR_BSS -D__STARTUP_INITIALIZE_NONCACHEDATA -mcpu=cortex-m7 -Wall -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mapcs -std=gnu99$/;" m +BENCH_EMBEDDED /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 108;" d +BENCH_EMBEDDED /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 38;" d +BENCH_OBJS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^BENCH_OBJS:=$(WOLFSSL)\/wolfcrypt\/benchmark\/benchmark.o main-bench.o$/;" m +BOARD_ACCEL_I2C_BASEADDR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 116;" d +BOARD_ACCEL_I2C_CLOCK_FREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 121;" d +BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 120;" d +BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 118;" d +BOARD_ARDUINO_I2C_INDEX /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 80;" d +BOARD_ARDUINO_I2C_IRQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 79;" d +BOARD_ARDUINO_INT_IRQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 78;" d +BOARD_Accel_I2C_Init /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^void BOARD_Accel_I2C_Init(void)$/;" f +BOARD_Accel_I2C_Receive /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Accel_I2C_Receive($/;" f +BOARD_Accel_I2C_Send /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)$/;" f +BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 46;" d +BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 47;" d +BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 48;" d +BOARD_BOOTCLOCKRUN_CLKO1_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 49;" d +BOARD_BOOTCLOCKRUN_CLKO2_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 50;" d +BOARD_BOOTCLOCKRUN_CLK_1M /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 51;" d +BOARD_BOOTCLOCKRUN_CLK_24M /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 52;" d +BOARD_BOOTCLOCKRUN_CORE_CLOCK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 43;" d +BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 53;" d +BOARD_BOOTCLOCKRUN_ENET1_TX_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 54;" d +BOARD_BOOTCLOCKRUN_ENET2_125M_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 55;" d +BOARD_BOOTCLOCKRUN_ENET2_TX_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 56;" d +BOARD_BOOTCLOCKRUN_ENET_125M_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 57;" d +BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 58;" d +BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 59;" d +BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 60;" d +BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 61;" d +BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 62;" d +BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 63;" d +BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 64;" d +BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 65;" d +BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 66;" d +BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 67;" d +BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 68;" d +BOARD_BOOTCLOCKRUN_LVDS1_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 69;" d +BOARD_BOOTCLOCKRUN_MQS_MCLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 70;" d +BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 71;" d +BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 72;" d +BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 73;" d +BOARD_BOOTCLOCKRUN_SAI1_MCLK1 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 74;" d +BOARD_BOOTCLOCKRUN_SAI1_MCLK2 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 75;" d +BOARD_BOOTCLOCKRUN_SAI1_MCLK3 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 76;" d +BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 77;" d +BOARD_BOOTCLOCKRUN_SAI2_MCLK1 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 78;" d +BOARD_BOOTCLOCKRUN_SAI2_MCLK2 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 79;" d +BOARD_BOOTCLOCKRUN_SAI2_MCLK3 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 80;" d +BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 81;" d +BOARD_BOOTCLOCKRUN_SAI3_MCLK1 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 82;" d +BOARD_BOOTCLOCKRUN_SAI3_MCLK2 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 83;" d +BOARD_BOOTCLOCKRUN_SAI3_MCLK3 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 84;" d +BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 85;" d +BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 86;" d +BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 87;" d +BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 88;" d +BOARD_BOOTCLOCKRUN_UART_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 89;" d +BOARD_BOOTCLOCKRUN_USBPHY1_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 90;" d +BOARD_BOOTCLOCKRUN_USBPHY2_CLK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 91;" d +BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 92;" d +BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 93;" d +BOARD_BT_UART_BASEADDR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 144;" d +BOARD_BT_UART_CLK_FREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 145;" d +BOARD_BT_UART_IRQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 146;" d +BOARD_BT_UART_IRQ_HANDLER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 147;" d +BOARD_BootClockRUN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.c /^void BOARD_BootClockRUN(void)$/;" f +BOARD_CAMERA_I2C_BASEADDR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 130;" d +BOARD_CAMERA_I2C_CLOCK_FREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 133;" d +BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 131;" d +BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 132;" d +BOARD_CAMERA_I2C_SCL_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 136;" d +BOARD_CAMERA_I2C_SCL_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 137;" d +BOARD_CAMERA_I2C_SDA_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 138;" d +BOARD_CAMERA_I2C_SDA_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 139;" d +BOARD_CAMERA_PWDN_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 140;" d +BOARD_CAMERA_PWDN_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 141;" d +BOARD_CODEC_I2C_BASEADDR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 123;" d +BOARD_CODEC_I2C_CLOCK_FREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 127;" d +BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 126;" d +BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 125;" d +BOARD_CODEC_I2C_INSTANCE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 124;" d +BOARD_Camera_I2C_Init /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^void BOARD_Camera_I2C_Init(void)$/;" f +BOARD_Camera_I2C_Receive /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Camera_I2C_Receive($/;" f +BOARD_Camera_I2C_ReceiveSCCB /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Camera_I2C_ReceiveSCCB($/;" f +BOARD_Camera_I2C_Send /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Camera_I2C_Send($/;" f +BOARD_Camera_I2C_SendSCCB /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Camera_I2C_SendSCCB($/;" f +BOARD_Codec_I2C_Init /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^void BOARD_Codec_I2C_Init(void)$/;" f +BOARD_Codec_I2C_Receive /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Codec_I2C_Receive($/;" f +BOARD_Codec_I2C_Send /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_Codec_I2C_Send($/;" f +BOARD_ConfigMPU /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^void BOARD_ConfigMPU(void)$/;" f +BOARD_DEBUG_UART_BASEADDR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 24;" d +BOARD_DEBUG_UART_BAUDRATE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 33;" d +BOARD_DEBUG_UART_CLK_FREQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 27;" d +BOARD_DEBUG_UART_INSTANCE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 25;" d +BOARD_DEBUG_UART_TYPE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 23;" d +BOARD_DebugConsoleSrcFreq /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^uint32_t BOARD_DebugConsoleSrcFreq(void)$/;" f +BOARD_ENET0_PHY_ADDRESS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 71;" d +BOARD_FLASH_SIZE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 68;" d +BOARD_HAS_SDCARD /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 150;" d +BOARD_INITCAN_CAN2_RX_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 692;" d +BOARD_INITCAN_CAN2_RX_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 693;" d +BOARD_INITCAN_CAN2_RX_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 689;" d +BOARD_INITCAN_CAN2_RX_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 691;" d +BOARD_INITCAN_CAN2_RX_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 690;" d +BOARD_INITCAN_CAN2_TX_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 685;" d +BOARD_INITCAN_CAN2_TX_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 686;" d +BOARD_INITCAN_CAN2_TX_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 682;" d +BOARD_INITCAN_CAN2_TX_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 684;" d +BOARD_INITCAN_CAN2_TX_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 683;" d +BOARD_INITCSI_CSI_D2_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 440;" d +BOARD_INITCSI_CSI_D2_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 442;" d +BOARD_INITCSI_CSI_D2_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 443;" d +BOARD_INITCSI_CSI_D2_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 438;" d +BOARD_INITCSI_CSI_D2_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 441;" d +BOARD_INITCSI_CSI_D2_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 439;" d +BOARD_INITCSI_CSI_D3_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 448;" d +BOARD_INITCSI_CSI_D3_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 450;" d +BOARD_INITCSI_CSI_D3_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 451;" d +BOARD_INITCSI_CSI_D3_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 446;" d +BOARD_INITCSI_CSI_D3_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 449;" d +BOARD_INITCSI_CSI_D3_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 447;" d +BOARD_INITCSI_CSI_D4_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 432;" d +BOARD_INITCSI_CSI_D4_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 434;" d +BOARD_INITCSI_CSI_D4_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 435;" d +BOARD_INITCSI_CSI_D4_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 430;" d +BOARD_INITCSI_CSI_D4_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 433;" d +BOARD_INITCSI_CSI_D4_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 431;" d +BOARD_INITCSI_CSI_D5_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 424;" d +BOARD_INITCSI_CSI_D5_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 426;" d +BOARD_INITCSI_CSI_D5_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 427;" d +BOARD_INITCSI_CSI_D5_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 422;" d +BOARD_INITCSI_CSI_D5_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 425;" d +BOARD_INITCSI_CSI_D5_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 423;" d +BOARD_INITCSI_CSI_D6_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 416;" d +BOARD_INITCSI_CSI_D6_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 418;" d +BOARD_INITCSI_CSI_D6_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 419;" d +BOARD_INITCSI_CSI_D6_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 414;" d +BOARD_INITCSI_CSI_D6_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 417;" d +BOARD_INITCSI_CSI_D6_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 415;" d +BOARD_INITCSI_CSI_D7_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 408;" d +BOARD_INITCSI_CSI_D7_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 410;" d +BOARD_INITCSI_CSI_D7_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 411;" d +BOARD_INITCSI_CSI_D7_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 406;" d +BOARD_INITCSI_CSI_D7_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 409;" d +BOARD_INITCSI_CSI_D7_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 407;" d +BOARD_INITCSI_CSI_D8_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 400;" d +BOARD_INITCSI_CSI_D8_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 402;" d +BOARD_INITCSI_CSI_D8_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 403;" d +BOARD_INITCSI_CSI_D8_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 398;" d +BOARD_INITCSI_CSI_D8_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 401;" d +BOARD_INITCSI_CSI_D8_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 399;" d +BOARD_INITCSI_CSI_D9_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 392;" d +BOARD_INITCSI_CSI_D9_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 394;" d +BOARD_INITCSI_CSI_D9_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 395;" d +BOARD_INITCSI_CSI_D9_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 390;" d +BOARD_INITCSI_CSI_D9_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 393;" d +BOARD_INITCSI_CSI_D9_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 391;" d +BOARD_INITCSI_CSI_HSYNC_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 478;" d +BOARD_INITCSI_CSI_HSYNC_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 479;" d +BOARD_INITCSI_CSI_HSYNC_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 475;" d +BOARD_INITCSI_CSI_HSYNC_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 477;" d +BOARD_INITCSI_CSI_HSYNC_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 476;" d +BOARD_INITCSI_CSI_I2C_SCL_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 485;" d +BOARD_INITCSI_CSI_I2C_SCL_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 486;" d +BOARD_INITCSI_CSI_I2C_SCL_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 482;" d +BOARD_INITCSI_CSI_I2C_SCL_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 484;" d +BOARD_INITCSI_CSI_I2C_SCL_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 483;" d +BOARD_INITCSI_CSI_I2C_SDA_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 492;" d +BOARD_INITCSI_CSI_I2C_SDA_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 493;" d +BOARD_INITCSI_CSI_I2C_SDA_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 489;" d +BOARD_INITCSI_CSI_I2C_SDA_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 491;" d +BOARD_INITCSI_CSI_I2C_SDA_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 490;" d +BOARD_INITCSI_CSI_MCLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 464;" d +BOARD_INITCSI_CSI_MCLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 465;" d +BOARD_INITCSI_CSI_MCLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 461;" d +BOARD_INITCSI_CSI_MCLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 463;" d +BOARD_INITCSI_CSI_MCLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 462;" d +BOARD_INITCSI_CSI_PIXCLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 457;" d +BOARD_INITCSI_CSI_PIXCLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 458;" d +BOARD_INITCSI_CSI_PIXCLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 454;" d +BOARD_INITCSI_CSI_PIXCLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 456;" d +BOARD_INITCSI_CSI_PIXCLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 455;" d +BOARD_INITCSI_CSI_PWDN_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 496;" d +BOARD_INITCSI_CSI_PWDN_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 498;" d +BOARD_INITCSI_CSI_PWDN_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 500;" d +BOARD_INITCSI_CSI_PWDN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 501;" d +BOARD_INITCSI_CSI_PWDN_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 499;" d +BOARD_INITCSI_CSI_PWDN_PORT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 497;" d +BOARD_INITCSI_CSI_VSYNC_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 471;" d +BOARD_INITCSI_CSI_VSYNC_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 472;" d +BOARD_INITCSI_CSI_VSYNC_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 468;" d +BOARD_INITCSI_CSI_VSYNC_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 470;" d +BOARD_INITCSI_CSI_VSYNC_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 469;" d +BOARD_INITDEBUG_UART_UART1_RXD_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 65;" d +BOARD_INITDEBUG_UART_UART1_RXD_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 66;" d +BOARD_INITDEBUG_UART_UART1_RXD_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 62;" d +BOARD_INITDEBUG_UART_UART1_RXD_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 64;" d +BOARD_INITDEBUG_UART_UART1_RXD_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 63;" d +BOARD_INITDEBUG_UART_UART1_TXD_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 58;" d +BOARD_INITDEBUG_UART_UART1_TXD_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 59;" d +BOARD_INITDEBUG_UART_UART1_TXD_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 55;" d +BOARD_INITDEBUG_UART_UART1_TXD_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 57;" d +BOARD_INITDEBUG_UART_UART1_TXD_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 56;" d +BOARD_INITENET_ENET_CRS_DV_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 743;" d +BOARD_INITENET_ENET_CRS_DV_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 744;" d +BOARD_INITENET_ENET_CRS_DV_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 740;" d +BOARD_INITENET_ENET_CRS_DV_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 742;" d +BOARD_INITENET_ENET_CRS_DV_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 741;" d +BOARD_INITENET_ENET_MDC_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 706;" d +BOARD_INITENET_ENET_MDC_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 707;" d +BOARD_INITENET_ENET_MDC_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 703;" d +BOARD_INITENET_ENET_MDC_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 705;" d +BOARD_INITENET_ENET_MDC_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 704;" d +BOARD_INITENET_ENET_MDIO_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 713;" d +BOARD_INITENET_ENET_MDIO_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 714;" d +BOARD_INITENET_ENET_MDIO_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 710;" d +BOARD_INITENET_ENET_MDIO_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 712;" d +BOARD_INITENET_ENET_MDIO_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 711;" d +BOARD_INITENET_ENET_RXD0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 726;" d +BOARD_INITENET_ENET_RXD0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 728;" d +BOARD_INITENET_ENET_RXD0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 729;" d +BOARD_INITENET_ENET_RXD0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 724;" d +BOARD_INITENET_ENET_RXD0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 727;" d +BOARD_INITENET_ENET_RXD0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 725;" d +BOARD_INITENET_ENET_RXD1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 734;" d +BOARD_INITENET_ENET_RXD1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 736;" d +BOARD_INITENET_ENET_RXD1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 737;" d +BOARD_INITENET_ENET_RXD1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 732;" d +BOARD_INITENET_ENET_RXD1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 735;" d +BOARD_INITENET_ENET_RXD1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 733;" d +BOARD_INITENET_ENET_RXER_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 750;" d +BOARD_INITENET_ENET_RXER_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 751;" d +BOARD_INITENET_ENET_RXER_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 747;" d +BOARD_INITENET_ENET_RXER_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 749;" d +BOARD_INITENET_ENET_RXER_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 748;" d +BOARD_INITENET_ENET_TXD0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 756;" d +BOARD_INITENET_ENET_TXD0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 758;" d +BOARD_INITENET_ENET_TXD0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 759;" d +BOARD_INITENET_ENET_TXD0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 754;" d +BOARD_INITENET_ENET_TXD0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 757;" d +BOARD_INITENET_ENET_TXD0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 755;" d +BOARD_INITENET_ENET_TXD1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 764;" d +BOARD_INITENET_ENET_TXD1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 766;" d +BOARD_INITENET_ENET_TXD1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 767;" d +BOARD_INITENET_ENET_TXD1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 762;" d +BOARD_INITENET_ENET_TXD1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 765;" d +BOARD_INITENET_ENET_TXD1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 763;" d +BOARD_INITENET_ENET_TXEN_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 773;" d +BOARD_INITENET_ENET_TXEN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 774;" d +BOARD_INITENET_ENET_TXEN_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 770;" d +BOARD_INITENET_ENET_TXEN_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 772;" d +BOARD_INITENET_ENET_TXEN_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 771;" d +BOARD_INITENET_ENET_TX_CLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 720;" d +BOARD_INITENET_ENET_TX_CLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 721;" d +BOARD_INITENET_ENET_TX_CLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 717;" d +BOARD_INITENET_ENET_TX_CLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 719;" d +BOARD_INITENET_ENET_TX_CLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 718;" d +BOARD_INITGT202SHIELD_IRQ_DIRECTION /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 97;" d +BOARD_INITGT202SHIELD_IRQ_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 91;" d +BOARD_INITGT202SHIELD_IRQ_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 93;" d +BOARD_INITGT202SHIELD_IRQ_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 95;" d +BOARD_INITGT202SHIELD_IRQ_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 96;" d +BOARD_INITGT202SHIELD_IRQ_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 94;" d +BOARD_INITGT202SHIELD_IRQ_PORT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 92;" d +BOARD_INITGT202SHIELD_PWRON_DIRECTION /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 89;" d +BOARD_INITGT202SHIELD_PWRON_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 83;" d +BOARD_INITGT202SHIELD_PWRON_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 85;" d +BOARD_INITGT202SHIELD_PWRON_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 87;" d +BOARD_INITGT202SHIELD_PWRON_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 88;" d +BOARD_INITGT202SHIELD_PWRON_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 86;" d +BOARD_INITGT202SHIELD_PWRON_PORT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 84;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_B_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 896;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_B_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 897;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 893;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 895;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_B_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 894;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 840;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 841;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 837;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 839;" d +BOARD_INITHYPERFLASH_FlexSPI_CLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 838;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_A_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 854;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_A_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 855;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_A_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 851;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_A_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 853;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_A_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 852;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_B_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 889;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_B_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 890;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_B_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 886;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_B_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 888;" d +BOARD_INITHYPERFLASH_FlexSPI_D0_B_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 887;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_A_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 861;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_A_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 862;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_A_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 858;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_A_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 860;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_A_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 859;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_B_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 882;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_B_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 883;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_B_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 879;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_B_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 881;" d +BOARD_INITHYPERFLASH_FlexSPI_D1_B_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 880;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_A_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 847;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_A_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 848;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_A_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 844;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_A_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 846;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_A_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 845;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_B_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 875;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_B_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 876;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_B_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 872;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_B_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 874;" d +BOARD_INITHYPERFLASH_FlexSPI_D2_B_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 873;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_A_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 910;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_A_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 911;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_A_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 907;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_A_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 909;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_A_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 908;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_B_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 868;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_B_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 869;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_B_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 865;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_B_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 867;" d +BOARD_INITHYPERFLASH_FlexSPI_D3_B_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 866;" d +BOARD_INITHYPERFLASH_FlexSPI_DQS_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 917;" d +BOARD_INITHYPERFLASH_FlexSPI_DQS_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 918;" d +BOARD_INITHYPERFLASH_FlexSPI_DQS_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 914;" d +BOARD_INITHYPERFLASH_FlexSPI_DQS_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 916;" d +BOARD_INITHYPERFLASH_FlexSPI_DQS_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 915;" d +BOARD_INITHYPERFLASH_FlexSPI_SS0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 903;" d +BOARD_INITHYPERFLASH_FlexSPI_SS0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 904;" d +BOARD_INITHYPERFLASH_FlexSPI_SS0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 900;" d +BOARD_INITHYPERFLASH_FlexSPI_SS0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 902;" d +BOARD_INITHYPERFLASH_FlexSPI_SS0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 901;" d +BOARD_INITLCD_BACKLIGHT_CTL_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 667;" d +BOARD_INITLCD_BACKLIGHT_CTL_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 669;" d +BOARD_INITLCD_BACKLIGHT_CTL_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 671;" d +BOARD_INITLCD_BACKLIGHT_CTL_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 672;" d +BOARD_INITLCD_BACKLIGHT_CTL_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 670;" d +BOARD_INITLCD_BACKLIGHT_CTL_PORT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 668;" d +BOARD_INITLCD_LCDIF_CLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 538;" d +BOARD_INITLCD_LCDIF_CLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 539;" d +BOARD_INITLCD_LCDIF_CLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 535;" d +BOARD_INITLCD_LCDIF_CLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 537;" d +BOARD_INITLCD_LCDIF_CLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 536;" d +BOARD_INITLCD_LCDIF_D0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 513;" d +BOARD_INITLCD_LCDIF_D0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 515;" d +BOARD_INITLCD_LCDIF_D0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 516;" d +BOARD_INITLCD_LCDIF_D0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 511;" d +BOARD_INITLCD_LCDIF_D0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 514;" d +BOARD_INITLCD_LCDIF_D0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 512;" d +BOARD_INITLCD_LCDIF_D10_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 600;" d +BOARD_INITLCD_LCDIF_D10_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 602;" d +BOARD_INITLCD_LCDIF_D10_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 603;" d +BOARD_INITLCD_LCDIF_D10_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 598;" d +BOARD_INITLCD_LCDIF_D10_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 601;" d +BOARD_INITLCD_LCDIF_D10_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 599;" d +BOARD_INITLCD_LCDIF_D11_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 608;" d +BOARD_INITLCD_LCDIF_D11_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 610;" d +BOARD_INITLCD_LCDIF_D11_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 611;" d +BOARD_INITLCD_LCDIF_D11_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 606;" d +BOARD_INITLCD_LCDIF_D11_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 609;" d +BOARD_INITLCD_LCDIF_D11_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 607;" d +BOARD_INITLCD_LCDIF_D12_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 616;" d +BOARD_INITLCD_LCDIF_D12_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 618;" d +BOARD_INITLCD_LCDIF_D12_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 619;" d +BOARD_INITLCD_LCDIF_D12_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 614;" d +BOARD_INITLCD_LCDIF_D12_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 617;" d +BOARD_INITLCD_LCDIF_D12_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 615;" d +BOARD_INITLCD_LCDIF_D13_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 624;" d +BOARD_INITLCD_LCDIF_D13_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 626;" d +BOARD_INITLCD_LCDIF_D13_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 627;" d +BOARD_INITLCD_LCDIF_D13_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 622;" d +BOARD_INITLCD_LCDIF_D13_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 625;" d +BOARD_INITLCD_LCDIF_D13_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 623;" d +BOARD_INITLCD_LCDIF_D14_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 632;" d +BOARD_INITLCD_LCDIF_D14_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 634;" d +BOARD_INITLCD_LCDIF_D14_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 635;" d +BOARD_INITLCD_LCDIF_D14_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 630;" d +BOARD_INITLCD_LCDIF_D14_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 633;" d +BOARD_INITLCD_LCDIF_D14_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 631;" d +BOARD_INITLCD_LCDIF_D15_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 640;" d +BOARD_INITLCD_LCDIF_D15_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 642;" d +BOARD_INITLCD_LCDIF_D15_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 643;" d +BOARD_INITLCD_LCDIF_D15_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 638;" d +BOARD_INITLCD_LCDIF_D15_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 641;" d +BOARD_INITLCD_LCDIF_D15_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 639;" d +BOARD_INITLCD_LCDIF_D1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 521;" d +BOARD_INITLCD_LCDIF_D1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 523;" d +BOARD_INITLCD_LCDIF_D1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 524;" d +BOARD_INITLCD_LCDIF_D1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 519;" d +BOARD_INITLCD_LCDIF_D1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 522;" d +BOARD_INITLCD_LCDIF_D1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 520;" d +BOARD_INITLCD_LCDIF_D2_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 529;" d +BOARD_INITLCD_LCDIF_D2_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 531;" d +BOARD_INITLCD_LCDIF_D2_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 532;" d +BOARD_INITLCD_LCDIF_D2_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 527;" d +BOARD_INITLCD_LCDIF_D2_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 530;" d +BOARD_INITLCD_LCDIF_D2_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 528;" d +BOARD_INITLCD_LCDIF_D3_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 544;" d +BOARD_INITLCD_LCDIF_D3_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 546;" d +BOARD_INITLCD_LCDIF_D3_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 547;" d +BOARD_INITLCD_LCDIF_D3_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 542;" d +BOARD_INITLCD_LCDIF_D3_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 545;" d +BOARD_INITLCD_LCDIF_D3_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 543;" d +BOARD_INITLCD_LCDIF_D4_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 552;" d +BOARD_INITLCD_LCDIF_D4_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 554;" d +BOARD_INITLCD_LCDIF_D4_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 555;" d +BOARD_INITLCD_LCDIF_D4_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 550;" d +BOARD_INITLCD_LCDIF_D4_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 553;" d +BOARD_INITLCD_LCDIF_D4_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 551;" d +BOARD_INITLCD_LCDIF_D5_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 560;" d +BOARD_INITLCD_LCDIF_D5_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 562;" d +BOARD_INITLCD_LCDIF_D5_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 563;" d +BOARD_INITLCD_LCDIF_D5_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 558;" d +BOARD_INITLCD_LCDIF_D5_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 561;" d +BOARD_INITLCD_LCDIF_D5_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 559;" d +BOARD_INITLCD_LCDIF_D6_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 568;" d +BOARD_INITLCD_LCDIF_D6_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 570;" d +BOARD_INITLCD_LCDIF_D6_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 571;" d +BOARD_INITLCD_LCDIF_D6_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 566;" d +BOARD_INITLCD_LCDIF_D6_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 569;" d +BOARD_INITLCD_LCDIF_D6_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 567;" d +BOARD_INITLCD_LCDIF_D7_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 576;" d +BOARD_INITLCD_LCDIF_D7_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 578;" d +BOARD_INITLCD_LCDIF_D7_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 579;" d +BOARD_INITLCD_LCDIF_D7_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 574;" d +BOARD_INITLCD_LCDIF_D7_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 577;" d +BOARD_INITLCD_LCDIF_D7_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 575;" d +BOARD_INITLCD_LCDIF_D8_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 584;" d +BOARD_INITLCD_LCDIF_D8_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 586;" d +BOARD_INITLCD_LCDIF_D8_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 587;" d +BOARD_INITLCD_LCDIF_D8_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 582;" d +BOARD_INITLCD_LCDIF_D8_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 585;" d +BOARD_INITLCD_LCDIF_D8_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 583;" d +BOARD_INITLCD_LCDIF_D9_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 592;" d +BOARD_INITLCD_LCDIF_D9_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 594;" d +BOARD_INITLCD_LCDIF_D9_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 595;" d +BOARD_INITLCD_LCDIF_D9_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 590;" d +BOARD_INITLCD_LCDIF_D9_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 593;" d +BOARD_INITLCD_LCDIF_D9_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 591;" d +BOARD_INITLCD_LCDIF_ENABLE_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 649;" d +BOARD_INITLCD_LCDIF_ENABLE_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 650;" d +BOARD_INITLCD_LCDIF_ENABLE_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 646;" d +BOARD_INITLCD_LCDIF_ENABLE_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 648;" d +BOARD_INITLCD_LCDIF_ENABLE_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 647;" d +BOARD_INITLCD_LCDIF_HSYNC_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 656;" d +BOARD_INITLCD_LCDIF_HSYNC_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 657;" d +BOARD_INITLCD_LCDIF_HSYNC_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 653;" d +BOARD_INITLCD_LCDIF_HSYNC_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 655;" d +BOARD_INITLCD_LCDIF_HSYNC_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 654;" d +BOARD_INITLCD_LCDIF_VSYNC_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 663;" d +BOARD_INITLCD_LCDIF_VSYNC_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 664;" d +BOARD_INITLCD_LCDIF_VSYNC_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 660;" d +BOARD_INITLCD_LCDIF_VSYNC_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 662;" d +BOARD_INITLCD_LCDIF_VSYNC_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 661;" d +BOARD_INITSDRAM_ENET_MDIO_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 377;" d +BOARD_INITSDRAM_ENET_MDIO_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 379;" d +BOARD_INITSDRAM_ENET_MDIO_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 380;" d +BOARD_INITSDRAM_ENET_MDIO_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 375;" d +BOARD_INITSDRAM_ENET_MDIO_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 378;" d +BOARD_INITSDRAM_ENET_MDIO_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 376;" d +BOARD_INITSDRAM_SEMC_A0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 78;" d +BOARD_INITSDRAM_SEMC_A0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 80;" d +BOARD_INITSDRAM_SEMC_A0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 81;" d +BOARD_INITSDRAM_SEMC_A0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 76;" d +BOARD_INITSDRAM_SEMC_A0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 79;" d +BOARD_INITSDRAM_SEMC_A0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 77;" d +BOARD_INITSDRAM_SEMC_A10_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 158;" d +BOARD_INITSDRAM_SEMC_A10_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 160;" d +BOARD_INITSDRAM_SEMC_A10_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 161;" d +BOARD_INITSDRAM_SEMC_A10_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 156;" d +BOARD_INITSDRAM_SEMC_A10_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 159;" d +BOARD_INITSDRAM_SEMC_A10_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 157;" d +BOARD_INITSDRAM_SEMC_A11_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 166;" d +BOARD_INITSDRAM_SEMC_A11_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 168;" d +BOARD_INITSDRAM_SEMC_A11_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 169;" d +BOARD_INITSDRAM_SEMC_A11_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 164;" d +BOARD_INITSDRAM_SEMC_A11_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 167;" d +BOARD_INITSDRAM_SEMC_A11_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 165;" d +BOARD_INITSDRAM_SEMC_A12_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 174;" d +BOARD_INITSDRAM_SEMC_A12_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 176;" d +BOARD_INITSDRAM_SEMC_A12_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 177;" d +BOARD_INITSDRAM_SEMC_A12_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 172;" d +BOARD_INITSDRAM_SEMC_A12_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 175;" d +BOARD_INITSDRAM_SEMC_A12_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 173;" d +BOARD_INITSDRAM_SEMC_A1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 86;" d +BOARD_INITSDRAM_SEMC_A1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 88;" d +BOARD_INITSDRAM_SEMC_A1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 89;" d +BOARD_INITSDRAM_SEMC_A1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 84;" d +BOARD_INITSDRAM_SEMC_A1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 87;" d +BOARD_INITSDRAM_SEMC_A1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 85;" d +BOARD_INITSDRAM_SEMC_A2_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 94;" d +BOARD_INITSDRAM_SEMC_A2_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 96;" d +BOARD_INITSDRAM_SEMC_A2_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 97;" d +BOARD_INITSDRAM_SEMC_A2_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 92;" d +BOARD_INITSDRAM_SEMC_A2_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 95;" d +BOARD_INITSDRAM_SEMC_A2_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 93;" d +BOARD_INITSDRAM_SEMC_A3_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 102;" d +BOARD_INITSDRAM_SEMC_A3_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 104;" d +BOARD_INITSDRAM_SEMC_A3_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 105;" d +BOARD_INITSDRAM_SEMC_A3_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 100;" d +BOARD_INITSDRAM_SEMC_A3_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 103;" d +BOARD_INITSDRAM_SEMC_A3_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 101;" d +BOARD_INITSDRAM_SEMC_A4_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 110;" d +BOARD_INITSDRAM_SEMC_A4_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 112;" d +BOARD_INITSDRAM_SEMC_A4_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 113;" d +BOARD_INITSDRAM_SEMC_A4_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 108;" d +BOARD_INITSDRAM_SEMC_A4_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 111;" d +BOARD_INITSDRAM_SEMC_A4_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 109;" d +BOARD_INITSDRAM_SEMC_A5_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 118;" d +BOARD_INITSDRAM_SEMC_A5_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 120;" d +BOARD_INITSDRAM_SEMC_A5_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 121;" d +BOARD_INITSDRAM_SEMC_A5_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 116;" d +BOARD_INITSDRAM_SEMC_A5_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 119;" d +BOARD_INITSDRAM_SEMC_A5_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 117;" d +BOARD_INITSDRAM_SEMC_A6_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 126;" d +BOARD_INITSDRAM_SEMC_A6_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 128;" d +BOARD_INITSDRAM_SEMC_A6_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 129;" d +BOARD_INITSDRAM_SEMC_A6_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 124;" d +BOARD_INITSDRAM_SEMC_A6_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 127;" d +BOARD_INITSDRAM_SEMC_A6_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 125;" d +BOARD_INITSDRAM_SEMC_A7_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 134;" d +BOARD_INITSDRAM_SEMC_A7_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 136;" d +BOARD_INITSDRAM_SEMC_A7_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 137;" d +BOARD_INITSDRAM_SEMC_A7_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 132;" d +BOARD_INITSDRAM_SEMC_A7_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 135;" d +BOARD_INITSDRAM_SEMC_A7_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 133;" d +BOARD_INITSDRAM_SEMC_A8_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 142;" d +BOARD_INITSDRAM_SEMC_A8_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 144;" d +BOARD_INITSDRAM_SEMC_A8_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 145;" d +BOARD_INITSDRAM_SEMC_A8_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 140;" d +BOARD_INITSDRAM_SEMC_A8_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 143;" d +BOARD_INITSDRAM_SEMC_A8_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 141;" d +BOARD_INITSDRAM_SEMC_A9_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 150;" d +BOARD_INITSDRAM_SEMC_A9_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 152;" d +BOARD_INITSDRAM_SEMC_A9_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 153;" d +BOARD_INITSDRAM_SEMC_A9_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 148;" d +BOARD_INITSDRAM_SEMC_A9_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 151;" d +BOARD_INITSDRAM_SEMC_A9_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 149;" d +BOARD_INITSDRAM_SEMC_BA0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 182;" d +BOARD_INITSDRAM_SEMC_BA0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 184;" d +BOARD_INITSDRAM_SEMC_BA0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 185;" d +BOARD_INITSDRAM_SEMC_BA0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 180;" d +BOARD_INITSDRAM_SEMC_BA0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 183;" d +BOARD_INITSDRAM_SEMC_BA0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 181;" d +BOARD_INITSDRAM_SEMC_BA1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 190;" d +BOARD_INITSDRAM_SEMC_BA1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 192;" d +BOARD_INITSDRAM_SEMC_BA1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 193;" d +BOARD_INITSDRAM_SEMC_BA1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 188;" d +BOARD_INITSDRAM_SEMC_BA1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 191;" d +BOARD_INITSDRAM_SEMC_BA1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 189;" d +BOARD_INITSDRAM_SEMC_CAS_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 199;" d +BOARD_INITSDRAM_SEMC_CAS_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 200;" d +BOARD_INITSDRAM_SEMC_CAS_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 196;" d +BOARD_INITSDRAM_SEMC_CAS_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 198;" d +BOARD_INITSDRAM_SEMC_CAS_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 197;" d +BOARD_INITSDRAM_SEMC_CKE_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 206;" d +BOARD_INITSDRAM_SEMC_CKE_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 207;" d +BOARD_INITSDRAM_SEMC_CKE_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 203;" d +BOARD_INITSDRAM_SEMC_CKE_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 205;" d +BOARD_INITSDRAM_SEMC_CKE_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 204;" d +BOARD_INITSDRAM_SEMC_CLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 213;" d +BOARD_INITSDRAM_SEMC_CLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 214;" d +BOARD_INITSDRAM_SEMC_CLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 210;" d +BOARD_INITSDRAM_SEMC_CLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 212;" d +BOARD_INITSDRAM_SEMC_CLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 211;" d +BOARD_INITSDRAM_SEMC_D0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 219;" d +BOARD_INITSDRAM_SEMC_D0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 221;" d +BOARD_INITSDRAM_SEMC_D0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 222;" d +BOARD_INITSDRAM_SEMC_D0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 217;" d +BOARD_INITSDRAM_SEMC_D0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 220;" d +BOARD_INITSDRAM_SEMC_D0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 218;" d +BOARD_INITSDRAM_SEMC_D10_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 299;" d +BOARD_INITSDRAM_SEMC_D10_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 301;" d +BOARD_INITSDRAM_SEMC_D10_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 302;" d +BOARD_INITSDRAM_SEMC_D10_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 297;" d +BOARD_INITSDRAM_SEMC_D10_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 300;" d +BOARD_INITSDRAM_SEMC_D10_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 298;" d +BOARD_INITSDRAM_SEMC_D11_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 307;" d +BOARD_INITSDRAM_SEMC_D11_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 309;" d +BOARD_INITSDRAM_SEMC_D11_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 310;" d +BOARD_INITSDRAM_SEMC_D11_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 305;" d +BOARD_INITSDRAM_SEMC_D11_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 308;" d +BOARD_INITSDRAM_SEMC_D11_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 306;" d +BOARD_INITSDRAM_SEMC_D12_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 315;" d +BOARD_INITSDRAM_SEMC_D12_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 317;" d +BOARD_INITSDRAM_SEMC_D12_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 318;" d +BOARD_INITSDRAM_SEMC_D12_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 313;" d +BOARD_INITSDRAM_SEMC_D12_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 316;" d +BOARD_INITSDRAM_SEMC_D12_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 314;" d +BOARD_INITSDRAM_SEMC_D13_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 323;" d +BOARD_INITSDRAM_SEMC_D13_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 325;" d +BOARD_INITSDRAM_SEMC_D13_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 326;" d +BOARD_INITSDRAM_SEMC_D13_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 321;" d +BOARD_INITSDRAM_SEMC_D13_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 324;" d +BOARD_INITSDRAM_SEMC_D13_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 322;" d +BOARD_INITSDRAM_SEMC_D14_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 331;" d +BOARD_INITSDRAM_SEMC_D14_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 333;" d +BOARD_INITSDRAM_SEMC_D14_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 334;" d +BOARD_INITSDRAM_SEMC_D14_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 329;" d +BOARD_INITSDRAM_SEMC_D14_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 332;" d +BOARD_INITSDRAM_SEMC_D14_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 330;" d +BOARD_INITSDRAM_SEMC_D15_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 339;" d +BOARD_INITSDRAM_SEMC_D15_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 341;" d +BOARD_INITSDRAM_SEMC_D15_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 342;" d +BOARD_INITSDRAM_SEMC_D15_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 337;" d +BOARD_INITSDRAM_SEMC_D15_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 340;" d +BOARD_INITSDRAM_SEMC_D15_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 338;" d +BOARD_INITSDRAM_SEMC_D1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 227;" d +BOARD_INITSDRAM_SEMC_D1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 229;" d +BOARD_INITSDRAM_SEMC_D1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 230;" d +BOARD_INITSDRAM_SEMC_D1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 225;" d +BOARD_INITSDRAM_SEMC_D1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 228;" d +BOARD_INITSDRAM_SEMC_D1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 226;" d +BOARD_INITSDRAM_SEMC_D2_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 235;" d +BOARD_INITSDRAM_SEMC_D2_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 237;" d +BOARD_INITSDRAM_SEMC_D2_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 238;" d +BOARD_INITSDRAM_SEMC_D2_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 233;" d +BOARD_INITSDRAM_SEMC_D2_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 236;" d +BOARD_INITSDRAM_SEMC_D2_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 234;" d +BOARD_INITSDRAM_SEMC_D3_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 243;" d +BOARD_INITSDRAM_SEMC_D3_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 245;" d +BOARD_INITSDRAM_SEMC_D3_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 246;" d +BOARD_INITSDRAM_SEMC_D3_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 241;" d +BOARD_INITSDRAM_SEMC_D3_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 244;" d +BOARD_INITSDRAM_SEMC_D3_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 242;" d +BOARD_INITSDRAM_SEMC_D4_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 251;" d +BOARD_INITSDRAM_SEMC_D4_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 253;" d +BOARD_INITSDRAM_SEMC_D4_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 254;" d +BOARD_INITSDRAM_SEMC_D4_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 249;" d +BOARD_INITSDRAM_SEMC_D4_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 252;" d +BOARD_INITSDRAM_SEMC_D4_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 250;" d +BOARD_INITSDRAM_SEMC_D5_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 259;" d +BOARD_INITSDRAM_SEMC_D5_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 261;" d +BOARD_INITSDRAM_SEMC_D5_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 262;" d +BOARD_INITSDRAM_SEMC_D5_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 257;" d +BOARD_INITSDRAM_SEMC_D5_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 260;" d +BOARD_INITSDRAM_SEMC_D5_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 258;" d +BOARD_INITSDRAM_SEMC_D6_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 267;" d +BOARD_INITSDRAM_SEMC_D6_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 269;" d +BOARD_INITSDRAM_SEMC_D6_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 270;" d +BOARD_INITSDRAM_SEMC_D6_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 265;" d +BOARD_INITSDRAM_SEMC_D6_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 268;" d +BOARD_INITSDRAM_SEMC_D6_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 266;" d +BOARD_INITSDRAM_SEMC_D7_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 275;" d +BOARD_INITSDRAM_SEMC_D7_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 277;" d +BOARD_INITSDRAM_SEMC_D7_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 278;" d +BOARD_INITSDRAM_SEMC_D7_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 273;" d +BOARD_INITSDRAM_SEMC_D7_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 276;" d +BOARD_INITSDRAM_SEMC_D7_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 274;" d +BOARD_INITSDRAM_SEMC_D8_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 283;" d +BOARD_INITSDRAM_SEMC_D8_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 285;" d +BOARD_INITSDRAM_SEMC_D8_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 286;" d +BOARD_INITSDRAM_SEMC_D8_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 281;" d +BOARD_INITSDRAM_SEMC_D8_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 284;" d +BOARD_INITSDRAM_SEMC_D8_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 282;" d +BOARD_INITSDRAM_SEMC_D9_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 291;" d +BOARD_INITSDRAM_SEMC_D9_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 293;" d +BOARD_INITSDRAM_SEMC_D9_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 294;" d +BOARD_INITSDRAM_SEMC_D9_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 289;" d +BOARD_INITSDRAM_SEMC_D9_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 292;" d +BOARD_INITSDRAM_SEMC_D9_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 290;" d +BOARD_INITSDRAM_SEMC_DM0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 347;" d +BOARD_INITSDRAM_SEMC_DM0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 349;" d +BOARD_INITSDRAM_SEMC_DM0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 350;" d +BOARD_INITSDRAM_SEMC_DM0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 345;" d +BOARD_INITSDRAM_SEMC_DM0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 348;" d +BOARD_INITSDRAM_SEMC_DM0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 346;" d +BOARD_INITSDRAM_SEMC_DM1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 355;" d +BOARD_INITSDRAM_SEMC_DM1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 357;" d +BOARD_INITSDRAM_SEMC_DM1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 358;" d +BOARD_INITSDRAM_SEMC_DM1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 353;" d +BOARD_INITSDRAM_SEMC_DM1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 356;" d +BOARD_INITSDRAM_SEMC_DM1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 354;" d +BOARD_INITSDRAM_SEMC_RAS_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 364;" d +BOARD_INITSDRAM_SEMC_RAS_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 365;" d +BOARD_INITSDRAM_SEMC_RAS_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 361;" d +BOARD_INITSDRAM_SEMC_RAS_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 363;" d +BOARD_INITSDRAM_SEMC_RAS_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 362;" d +BOARD_INITSDRAM_SEMC_WE_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 371;" d +BOARD_INITSDRAM_SEMC_WE_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 372;" d +BOARD_INITSDRAM_SEMC_WE_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 368;" d +BOARD_INITSDRAM_SEMC_WE_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 370;" d +BOARD_INITSDRAM_SEMC_WE_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 369;" d +BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 113;" d +BOARD_INITSILEX2401SHIELD_IRQ_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 107;" d +BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 109;" d +BOARD_INITSILEX2401SHIELD_IRQ_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 111;" d +BOARD_INITSILEX2401SHIELD_IRQ_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 112;" d +BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 110;" d +BOARD_INITSILEX2401SHIELD_IRQ_PORT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 108;" d +BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 105;" d +BOARD_INITSILEX2401SHIELD_PWRON_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 99;" d +BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 101;" d +BOARD_INITSILEX2401SHIELD_PWRON_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 103;" d +BOARD_INITSILEX2401SHIELD_PWRON_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 104;" d +BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 102;" d +BOARD_INITSILEX2401SHIELD_PWRON_PORT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 100;" d +BOARD_INITUSDHC_SD1_CLK_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 826;" d +BOARD_INITUSDHC_SD1_CLK_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 827;" d +BOARD_INITUSDHC_SD1_CLK_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 823;" d +BOARD_INITUSDHC_SD1_CLK_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 825;" d +BOARD_INITUSDHC_SD1_CLK_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 824;" d +BOARD_INITUSDHC_SD1_CMD_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 819;" d +BOARD_INITUSDHC_SD1_CMD_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 820;" d +BOARD_INITUSDHC_SD1_CMD_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 816;" d +BOARD_INITUSDHC_SD1_CMD_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 818;" d +BOARD_INITUSDHC_SD1_CMD_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 817;" d +BOARD_INITUSDHC_SD1_D0_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 810;" d +BOARD_INITUSDHC_SD1_D0_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 812;" d +BOARD_INITUSDHC_SD1_D0_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 813;" d +BOARD_INITUSDHC_SD1_D0_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 808;" d +BOARD_INITUSDHC_SD1_D0_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 811;" d +BOARD_INITUSDHC_SD1_D0_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 809;" d +BOARD_INITUSDHC_SD1_D1_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 802;" d +BOARD_INITUSDHC_SD1_D1_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 804;" d +BOARD_INITUSDHC_SD1_D1_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 805;" d +BOARD_INITUSDHC_SD1_D1_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 800;" d +BOARD_INITUSDHC_SD1_D1_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 803;" d +BOARD_INITUSDHC_SD1_D1_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 801;" d +BOARD_INITUSDHC_SD1_D2_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 794;" d +BOARD_INITUSDHC_SD1_D2_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 796;" d +BOARD_INITUSDHC_SD1_D2_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 797;" d +BOARD_INITUSDHC_SD1_D2_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 792;" d +BOARD_INITUSDHC_SD1_D2_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 795;" d +BOARD_INITUSDHC_SD1_D2_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 793;" d +BOARD_INITUSDHC_SD1_D3_CHANNEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 786;" d +BOARD_INITUSDHC_SD1_D3_LABEL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 788;" d +BOARD_INITUSDHC_SD1_D3_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 789;" d +BOARD_INITUSDHC_SD1_D3_PERIPHERAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 784;" d +BOARD_INITUSDHC_SD1_D3_PIN_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 787;" d +BOARD_INITUSDHC_SD1_D3_SIGNAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 785;" d +BOARD_InitBootClocks /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.c /^void BOARD_InitBootClocks(void)$/;" f +BOARD_InitBootPeripherals /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/peripherals.c /^void BOARD_InitBootPeripherals(void)$/;" f +BOARD_InitBootPins /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.c /^void BOARD_InitBootPins(void) {$/;" f +BOARD_InitDebugConsole /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^void BOARD_InitDebugConsole(void)$/;" f +BOARD_InitPeripherals /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/peripherals.c /^void BOARD_InitPeripherals(void)$/;" f +BOARD_InitPins /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.c /^void BOARD_InitPins(void) {$/;" f +BOARD_LPI2C_Init /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)$/;" f +BOARD_LPI2C_Receive /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_LPI2C_Receive(LPI2C_Type *base,$/;" f +BOARD_LPI2C_ReceiveSCCB /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,$/;" f +BOARD_LPI2C_Send /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_LPI2C_Send(LPI2C_Type *base,$/;" f +BOARD_LPI2C_SendSCCB /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.c /^status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,$/;" f +BOARD_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 20;" d +BOARD_UART_IRQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 29;" d +BOARD_UART_IRQ_HANDLER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 30;" d +BOARD_USB_PHY_D_CAL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 74;" d +BOARD_USB_PHY_TXCAL45DM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 76;" d +BOARD_USB_PHY_TXCAL45DP /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 75;" d +BOARD_USER_BUTTON_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 58;" d +BOARD_USER_BUTTON_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 61;" d +BOARD_USER_BUTTON_IRQ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 63;" d +BOARD_USER_BUTTON_IRQ_HANDLER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 64;" d +BOARD_USER_BUTTON_NAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 65;" d +BOARD_USER_LED_GPIO /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 40;" d +BOARD_USER_LED_GPIO_PIN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 43;" d +BOARD_XTAL0_CLK_HZ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 16;" d +BOARD_XTAL32K_CLK_HZ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 18;" d +CC /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^CC=arm-none-eabi-gcc$/;" m +CFLAGS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^CFLAGS=-DXIP_EXTERNAL_FLASH=1 -DXIP_BOOT_HEADER_ENABLE=1 -DCPU_MIMXRT1062DVL6A -DPRINTF_FLOAT_ENABLE=1 -DSCANF_FLOAT_ENABLE=1 -DPRINTF_ADVANCED_ENABLE=1 -DSCANF_ADVANCED_ENABLE=1 -DSERIAL_PORT_TYPE_UART=1 -Os -mcpu=cortex-m7 -Wall -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -MMD -MP -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mapcs -std=gnu99 -DXPRINTF=PRINTF$/;" m +CUSTOM_RAND_GENERATE_BLOCK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 42;" d +DCD_ARRAY_SIZE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.h 30;" d +DCD_TAG_HEADER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.h 27;" d +DCD_TAG_HEADER_SHIFT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.h 29;" d +DCD_VERSION /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.h 28;" d +ECC_TIMING_RESISTANT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 52;" d +ED25519_SMALL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 48;" d +FSL_COMPONENT_ID /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.c 24;" d file: +FSL_XIP_BOARD_DRIVER_VERSION /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.h 21;" d +HAVE_AESGCM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 82;" d +HAVE_CHACHA /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 80;" d +HAVE_ECC /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 51;" d +HAVE_ECC256 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 67;" d +HAVE_ED25519 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 47;" d +HAVE_POLY1035 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 83;" d +HAVE_PWDBASED /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 81;" d +HAVE_RSA /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 69;" d +H_USER_SETTINGS_ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 27;" d +LDFLAGS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^LDFLAGS= -mcpu=cortex-m7 -Wall -mfloat-abi=hard -mfpu=fpv5-d16 --specs=nosys.specs -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mthumb -mapcs -Xlinker --gc-sections -Xlinker -static -Xlinker -z -Xlinker muldefs -Xlinker -Map=output.map -T MIMXRT1062xxxxx_flexspi_nor.ld -static -lm -lc -lnosys$/;" m +LOGIC_LED_OFF /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 38;" d +LOGIC_LED_ON /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 37;" d +NO_CERT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 93;" d +NO_DES3 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 96;" d +NO_DEV_RANDOM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 99;" d +NO_DH /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 90;" d +NO_DSA /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 88;" d +NO_ERROR_STRINGS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 106;" d +NO_FILESYSTEM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 100;" d +NO_HC128 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 95;" d +NO_MAIN_DRIVER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 101;" d +NO_MD4 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 89;" d +NO_OLD_RNGNAME /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 102;" d +NO_RABBIT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 91;" d +NO_RC4 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 87;" d +NO_SESSION_CACHE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 94;" d +NO_SIG_WRAPPER /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 92;" d +NO_WOLFSSL_DIR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 103;" d +NO_WOLFSSL_DIR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 44;" d +NO_WOLFSSL_MEMORY /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 39;" d +NO_WRITEV /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 98;" d +OBJS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^OBJS=common.o board.o pin_mux.o dcd.o clock_config.o $(SDK)\/devices\/MIMXRT1062\/gcc\/startup_MIMXRT1062.o $(SDK)\/devices\/MIMXRT1062\/system_MIMXRT1062.o \\$/;" m +RSA_LOW_MEM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 70;" d +SDK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^SDK=..\/SDK-2.8.2_EVK-MIMXRT1060$/;" m +SINGLE_THREADED /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 35;" d +SIZEOF_LONG_LONG /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 37;" d +SP_WORD_SIZE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 64;" d +SP_WORD_SIZE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 75;" d +SysTick_Handler /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/common.c /^void SysTick_Handler(void)$/;" f +SysTick_Handler /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main.c /^void SysTick_Handler(void)$/;" f +TEST_OBJS /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^TEST_OBJS:=$(WOLFSSL)\/wolfcrypt\/test\/test.o main-test.o$/;" m +USER_LED_INIT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 46;" d +USER_LED_OFF /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 51;" d +USER_LED_ON /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 49;" d +USER_LED_TOGGLE /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 52;" d +USE_FAST_MATH /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 53;" d +WC_NO_HASHDRBG /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 97;" d +WC_RSA_BLINDING /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 76;" d +WOLFCRYPT_ONLY /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 36;" d +WOLFSSL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/Makefile /^WOLFSSL=..\/wolfssl$/;" m +WOLFSSL_GENERAL_ALIGNMENT /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 34;" d +WOLFSSL_HAVE_SP_ECC /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 54;" d +WOLFSSL_HAVE_SP_RSA /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 71;" d +WOLFSSL_IGNORE_FILE_WARN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 105;" d +WOLFSSL_NO_CURRDIR /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 45;" d +WOLFSSL_NO_PEM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 86;" d +WOLFSSL_NO_SOCK /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 104;" d +WOLFSSL_SHA3 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 78;" d +WOLFSSL_SHA512 /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 49;" d +WOLFSSL_SP /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 61;" d +WOLFSSL_SP /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 72;" d +WOLFSSL_SP_ARM_CORTEX_M_ASM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 60;" d +WOLFSSL_SP_ASM /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 59;" d +WOLFSSL_SP_MATH /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 62;" d +WOLFSSL_SP_MATH /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 74;" d +WOLFSSL_SP_SMALL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 63;" d +WOLFSSL_SP_SMALL /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 73;" d +XPRINTF /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/user_settings.h 109;" d +_BOARD_H_ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/board.h 9;" d +_CLOCK_CONFIG_H_ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.h 9;" d +_PERIPHERALS_H_ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/peripherals.h 14;" d +_PIN_MUX_H_ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h 14;" d +__DCD__ /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.h 14;" d +_pin_mux_direction /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h /^typedef enum _pin_mux_direction$/;" g +armPllConfig_BOARD_BootClockRUN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.c /^const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =$/;" v +cust_rand_generate_block /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/common.c /^int32_t cust_rand_generate_block(uint8_t *rndb, uint32_t sz)$/;" f +cust_rand_generate_block /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main.c /^int32_t cust_rand_generate_block(uint8_t *rndb, uint32_t sz)$/;" f +dcd_data /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.c /^const uint8_t dcd_data[] = {$/;" v +dcd_data /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/dcd.c /^const uint8_t dcd_data[] = {0x00};$/;" v +g_systickCounter /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/common.c /^volatile uint32_t g_systickCounter;$/;" v +g_systickCounter /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main.c /^volatile uint32_t g_systickCounter;$/;" v +gettimeofday /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/common.c /^int gettimeofday(struct timeval *tv, struct timezone *tz)$/;" f +gettimeofday /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main.c /^int gettimeofday(struct timeval *tv, struct timezone *tz)$/;" f +kPIN_MUX_DirectionInput /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h /^ kPIN_MUX_DirectionInput = 0U, \/* Input direction *\/$/;" e enum:_pin_mux_direction +kPIN_MUX_DirectionInputOrOutput /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h /^ kPIN_MUX_DirectionInputOrOutput = 2U \/* Input or output direction *\/$/;" e enum:_pin_mux_direction +kPIN_MUX_DirectionOutput /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h /^ kPIN_MUX_DirectionOutput = 1U, \/* Output direction *\/$/;" e enum:_pin_mux_direction +main /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main-bench.c /^void main(void)$/;" f +main /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main-test.c /^void main(void)$/;" f +main /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/main.c /^void main(void)$/;" f +pin_mux_direction_t /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/pin_mux.h /^} pin_mux_direction_t;$/;" t typeref:enum:_pin_mux_direction +sysPllConfig_BOARD_BootClockRUN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.c /^const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =$/;" v +usb1PllConfig_BOARD_BootClockRUN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.c /^const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =$/;" v +videoPllConfig_BOARD_BootClockRUN /home/dan/src/NXP/i.MX_RT1060/wolfcrypt-test-app/clock_config.c /^const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =$/;" v diff --git a/RT1060/user_settings.h b/RT1060/user_settings.h new file mode 100644 index 00000000..780793f4 --- /dev/null +++ b/RT1060/user_settings.h @@ -0,0 +1,111 @@ +/* user_settings.h + * + * Custom configuration for wolfCrypt/wolfSSL. + * Enabled via WOLFSSL_USER_SETTINGS. + * + * + * Copyright (C) 2020 wolfSSL Inc. + * + * This file is part of wolfSSL. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef H_USER_SETTINGS_ +#define H_USER_SETTINGS_ +#include +#include "fsl_debug_console.h" + + + +/* System */ +#define WOLFSSL_GENERAL_ALIGNMENT 4 +#define SINGLE_THREADED +#define WOLFCRYPT_ONLY +#define SIZEOF_LONG_LONG 8 +#define BENCH_EMBEDDED +#define NO_WOLFSSL_MEMORY + +int32_t cust_rand_generate_block(uint8_t *rndb, uint32_t sz); +#define CUSTOM_RAND_GENERATE_BLOCK cust_rand_generate_block + +#define NO_WOLFSSL_DIR +#define WOLFSSL_NO_CURRDIR + +#define HAVE_ED25519 +#define ED25519_SMALL +#define WOLFSSL_SHA512 + +#define HAVE_ECC +#define ECC_TIMING_RESISTANT +#undef USE_FAST_MATH +#define WOLFSSL_HAVE_SP_ECC + + + +/* SP MATH */ +#define WOLFSSL_SP_ASM +#define WOLFSSL_SP_ARM_CORTEX_M_ASM +#define WOLFSSL_SP +#define WOLFSSL_SP_MATH +#define WOLFSSL_SP_SMALL +#define SP_WORD_SIZE 32 + +/* Curve */ +# define HAVE_ECC256 + +#define HAVE_RSA +#define RSA_LOW_MEM +#define WOLFSSL_HAVE_SP_RSA +#define WOLFSSL_SP +#define WOLFSSL_SP_SMALL +#define WOLFSSL_SP_MATH +#define SP_WORD_SIZE 32 +#define WC_RSA_BLINDING + +#define WOLFSSL_SHA3 + +#define HAVE_CHACHA +#define HAVE_PWDBASED +#define HAVE_AESGCM +#define HAVE_POLY1035 + +/* Disables - For minimum wolfCrypt build */ +#define WOLFSSL_NO_PEM +#define NO_RC4 +#define NO_DSA +#define NO_MD4 +#define NO_DH +#define NO_RABBIT +#define NO_SIG_WRAPPER +#define NO_CERT +#define NO_SESSION_CACHE +#define NO_HC128 +#define NO_DES3 +#define WC_NO_HASHDRBG +#define NO_WRITEV +#define NO_DEV_RANDOM +#define NO_FILESYSTEM +#define NO_MAIN_DRIVER +#define NO_OLD_RNGNAME +#define NO_WOLFSSL_DIR +#define WOLFSSL_NO_SOCK +#define WOLFSSL_IGNORE_FILE_WARN +#define NO_ERROR_STRINGS + +#define BENCH_EMBEDDED +#define XPRINTF PRINTF + +#endif /* !H_USER_SETTINGS_ */