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Merge pull request #7931 from barracuda156/powerpc-darwin 

Fixes for PowerPC
pull/7972/head
Sean Parkinson 2024-09-10 10:34:09 +10:00 committed by GitHub
parent 500a3b41e4 94478cb208
commit 10c1fa2088
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
4 changed files with 358 additions and 6 deletions
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50
wolfcrypt/src/asm.c
View File

@ -529,6 +529,27 @@ __asm__( \
#define LOOP_START \ #define LOOP_START \
mu = c[x] * mp mu = c[x] * mp
#ifdef __APPLE__
#define INNERMUL \
__asm__( \
" mullw r16,%3,%4 \n\t" \
" mulhwu r17,%3,%4 \n\t" \
" addc r16,r16,%2 \n\t" \
" addze r17,r17 \n\t" \
" addc %1,r16,%5 \n\t" \
" addze %0,r17 \n\t" \
:"=r"(cy),"=r"(_c[0]):"0"(cy),"r"(mu),"r"(tmpm[0]),"1"(_c[0]):"r16", "r17", "cc"); ++tmpm;
#define PROPCARRY \
__asm__( \
" addc %1,%3,%2 \n\t" \
" xor %0,%2,%2 \n\t" \
" addze %0,%2 \n\t" \
:"=r"(cy),"=r"(_c[0]):"0"(cy),"1"(_c[0]):"cc");
#else
#define INNERMUL \ #define INNERMUL \
__asm__( \ __asm__( \
" mullw 16,%3,%4 \n\t" \ " mullw 16,%3,%4 \n\t" \
@ -546,6 +567,8 @@ __asm__( \
" addze %0,%2 \n\t" \ " addze %0,%2 \n\t" \
:"=r"(cy),"=r"(_c[0]):"0"(cy),"1"(_c[0]):"cc"); :"=r"(cy),"=r"(_c[0]):"0"(cy),"1"(_c[0]):"cc");
#endif
#elif defined(TFM_PPC64) #elif defined(TFM_PPC64)
/* PPC64 */ /* PPC64 */
@ -555,6 +578,8 @@ __asm__( \
#define LOOP_START \ #define LOOP_START \
mu = c[x] * mp mu = c[x] * mp
#ifdef __APPLE__
#define INNERMUL \ #define INNERMUL \
__asm__( \ __asm__( \
" mulld r16,%3,%4 \n\t" \ " mulld r16,%3,%4 \n\t" \
@ -576,6 +601,31 @@ __asm__( \
" addze %0,%0 \n\t" \ " addze %0,%0 \n\t" \
:"=r"(cy),"=m"(_c[0]):"0"(cy),"1"(_c[0]):"r16","cc"); :"=r"(cy),"=m"(_c[0]):"0"(cy),"1"(_c[0]):"r16","cc");
#else
#define INNERMUL \
__asm__( \
" mulld 16,%3,%4 \n\t" \
" mulhdu 17,%3,%4 \n\t" \
" addc 16,16,%0 \n\t" \
" addze 17,17 \n\t" \
" ldx 18,0,%1 \n\t" \
" addc 16,16,18 \n\t" \
" addze %0,17 \n\t" \
" sdx 16,0,%1 \n\t" \
:"=r"(cy),"=m"(_c[0]):"0"(cy),"r"(mu),"r"(tmpm[0]),"1"(_c[0]):"16", "17", "18","cc"); ++tmpm;
#define PROPCARRY \
__asm__( \
" ldx 16,0,%1 \n\t" \
" addc 16,16,%0 \n\t" \
" sdx 16,0,%1 \n\t" \
" xor %0,%0,%0 \n\t" \
" addze %0,%0 \n\t" \
:"=r"(cy),"=m"(_c[0]):"0"(cy),"1"(_c[0]):"16","cc");
#endif
/******************************************************************/ /******************************************************************/
#elif defined(TFM_AVR32) #elif defined(TFM_AVR32)

302
wolfcrypt/src/sp_int.c
View File

@ -3473,6 +3473,156 @@ static WC_INLINE sp_int_digit sp_div_word(sp_int_digit hi, sp_int_digit lo,
* CPU: PPC64 * CPU: PPC64
*/ */
#ifdef __APPLE__
/* Multiply va by vb and store double size result in: vh | vl */
#define SP_ASM_MUL(vl, vh, va, vb) \
__asm__ __volatile__ ( \
"mulld %[l], %[a], %[b] \n\t" \
"mulhdu %[h], %[a], %[b] \n\t" \
: [h] "+r" (vh), [l] "+r" (vl) \
: [a] "r" (va), [b] "r" (vb) \
: "memory" \
)
/* Multiply va by vb and store double size result in: vo | vh | vl */
#define SP_ASM_MUL_SET(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mulhdu %[h], %[a], %[b] \n\t" \
"mulld %[l], %[a], %[b] \n\t" \
"li %[o], 0 \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "=r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: \
)
/* Multiply va by vb and add double size result into: vo | vh | vl */
#define SP_ASM_MUL_ADD(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mulld r16, %[a], %[b] \n\t" \
"mulhdu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Multiply va by vb and add double size result into: vh | vl */
#define SP_ASM_MUL_ADD_NO(vl, vh, va, vb) \
__asm__ __volatile__ ( \
"mulld r16, %[a], %[b] \n\t" \
"mulhdu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Multiply va by vb and add double size result twice into: vo | vh | vl */
#define SP_ASM_MUL_ADD2(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mulld r16, %[a], %[b] \n\t" \
"mulhdu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Multiply va by vb and add double size result twice into: vo | vh | vl
* Assumes first add will not overflow vh | vl
*/
#define SP_ASM_MUL_ADD2_NO(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mulld r16, %[a], %[b] \n\t" \
"mulhdu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Square va and store double size result in: vh | vl */
#define SP_ASM_SQR(vl, vh, va) \
__asm__ __volatile__ ( \
"mulld %[l], %[a], %[a] \n\t" \
"mulhdu %[h], %[a], %[a] \n\t" \
: [h] "+r" (vh), [l] "+r" (vl) \
: [a] "r" (va) \
: "memory" \
)
/* Square va and add double size result into: vo | vh | vl */
#define SP_ASM_SQR_ADD(vl, vh, vo, va) \
__asm__ __volatile__ ( \
"mulld r16, %[a], %[a] \n\t" \
"mulhdu r17, %[a], %[a] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va) \
: "r16", "r17", "cc" \
)
/* Square va and add double size result into: vh | vl */
#define SP_ASM_SQR_ADD_NO(vl, vh, va) \
__asm__ __volatile__ ( \
"mulld r16, %[a], %[a] \n\t" \
"mulhdu r17, %[a], %[a] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va) \
: "r16", "r17", "cc" \
)
/* Add va into: vh | vl */
#define SP_ASM_ADDC(vl, vh, va) \
__asm__ __volatile__ ( \
"addc %[l], %[l], %[a] \n\t" \
"addze %[h], %[h] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va) \
: "cc" \
)
/* Sub va from: vh | vl */
#define SP_ASM_SUBB(vl, vh, va) \
__asm__ __volatile__ ( \
"subfc %[l], %[a], %[l] \n\t" \
"li r16, 0 \n\t" \
"subfe %[h], r16, %[h] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va) \
: "r16", "cc" \
)
/* Add two times vc | vb | va into vo | vh | vl */
#define SP_ASM_ADD_DBL_3(vl, vh, vo, va, vb, vc) \
__asm__ __volatile__ ( \
"addc %[l], %[l], %[a] \n\t" \
"adde %[h], %[h], %[b] \n\t" \
"adde %[o], %[o], %[c] \n\t" \
"addc %[l], %[l], %[a] \n\t" \
"adde %[h], %[h], %[b] \n\t" \
"adde %[o], %[o], %[c] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb), [c] "r" (vc) \
: "cc" \
)
/* Count leading zeros. */
#define SP_ASM_LZCNT(va, vn) \
__asm__ __volatile__ ( \
"cntlzd %[n], %[a] \n\t" \
: [n] "=r" (vn) \
: [a] "r" (va) \
: \
)
#else /* !defined(__APPLE__) */
/* Multiply va by vb and store double size result in: vh | vl */ /* Multiply va by vb and store double size result in: vh | vl */
#define SP_ASM_MUL(vl, vh, va, vb) \ #define SP_ASM_MUL(vl, vh, va, vb) \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
@ -3619,6 +3769,8 @@ static WC_INLINE sp_int_digit sp_div_word(sp_int_digit hi, sp_int_digit lo,
: \ : \
) )
#endif /* !defined(__APPLE__) */
#define SP_INT_ASM_AVAILABLE #define SP_INT_ASM_AVAILABLE
#endif /* WOLFSSL_SP_PPC64 && SP_WORD_SIZE == 64 */ #endif /* WOLFSSL_SP_PPC64 && SP_WORD_SIZE == 64 */
@ -3628,6 +3780,154 @@ static WC_INLINE sp_int_digit sp_div_word(sp_int_digit hi, sp_int_digit lo,
* CPU: PPC 32-bit * CPU: PPC 32-bit
*/ */
#ifdef __APPLE__
/* Multiply va by vb and store double size result in: vh | vl */
#define SP_ASM_MUL(vl, vh, va, vb) \
__asm__ __volatile__ ( \
"mullw %[l], %[a], %[b] \n\t" \
"mulhwu %[h], %[a], %[b] \n\t" \
: [h] "+r" (vh), [l] "+r" (vl) \
: [a] "r" (va), [b] "r" (vb) \
: "memory" \
)
/* Multiply va by vb and store double size result in: vo | vh | vl */
#define SP_ASM_MUL_SET(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mulhwu %[h], %[a], %[b] \n\t" \
"mullw %[l], %[a], %[b] \n\t" \
"li %[o], 0 \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "=r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
)
/* Multiply va by vb and add double size result into: vo | vh | vl */
#define SP_ASM_MUL_ADD(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mullw r16, %[a], %[b] \n\t" \
"mulhwu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Multiply va by vb and add double size result into: vh | vl */
#define SP_ASM_MUL_ADD_NO(vl, vh, va, vb) \
__asm__ __volatile__ ( \
"mullw r16, %[a], %[b] \n\t" \
"mulhwu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Multiply va by vb and add double size result twice into: vo | vh | vl */
#define SP_ASM_MUL_ADD2(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mullw r16, %[a], %[b] \n\t" \
"mulhwu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Multiply va by vb and add double size result twice into: vo | vh | vl
* Assumes first add will not overflow vh | vl
*/
#define SP_ASM_MUL_ADD2_NO(vl, vh, vo, va, vb) \
__asm__ __volatile__ ( \
"mullw r16, %[a], %[b] \n\t" \
"mulhwu r17, %[a], %[b] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb) \
: "r16", "r17", "cc" \
)
/* Square va and store double size result in: vh | vl */
#define SP_ASM_SQR(vl, vh, va) \
__asm__ __volatile__ ( \
"mullw %[l], %[a], %[a] \n\t" \
"mulhwu %[h], %[a], %[a] \n\t" \
: [h] "+r" (vh), [l] "+r" (vl) \
: [a] "r" (va) \
: "memory" \
)
/* Square va and add double size result into: vo | vh | vl */
#define SP_ASM_SQR_ADD(vl, vh, vo, va) \
__asm__ __volatile__ ( \
"mullw r16, %[a], %[a] \n\t" \
"mulhwu r17, %[a], %[a] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
"addze %[o], %[o] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va) \
: "r16", "r17", "cc" \
)
/* Square va and add double size result into: vh | vl */
#define SP_ASM_SQR_ADD_NO(vl, vh, va) \
__asm__ __volatile__ ( \
"mullw r16, %[a], %[a] \n\t" \
"mulhwu r17, %[a], %[a] \n\t" \
"addc %[l], %[l], r16 \n\t" \
"adde %[h], %[h], r17 \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va) \
: "r16", "r17", "cc" \
)
/* Add va into: vh | vl */
#define SP_ASM_ADDC(vl, vh, va) \
__asm__ __volatile__ ( \
"addc %[l], %[l], %[a] \n\t" \
"addze %[h], %[h] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va) \
: "cc" \
)
/* Sub va from: vh | vl */
#define SP_ASM_SUBB(vl, vh, va) \
__asm__ __volatile__ ( \
"subfc %[l], %[a], %[l] \n\t" \
"li r16, 0 \n\t" \
"subfe %[h], r16, %[h] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh) \
: [a] "r" (va) \
: "r16", "cc" \
)
/* Add two times vc | vb | va into vo | vh | vl */
#define SP_ASM_ADD_DBL_3(vl, vh, vo, va, vb, vc) \
__asm__ __volatile__ ( \
"addc %[l], %[l], %[a] \n\t" \
"adde %[h], %[h], %[b] \n\t" \
"adde %[o], %[o], %[c] \n\t" \
"addc %[l], %[l], %[a] \n\t" \
"adde %[h], %[h], %[b] \n\t" \
"adde %[o], %[o], %[c] \n\t" \
: [l] "+r" (vl), [h] "+r" (vh), [o] "+r" (vo) \
: [a] "r" (va), [b] "r" (vb), [c] "r" (vc) \
: "cc" \
)
/* Count leading zeros. */
#define SP_ASM_LZCNT(va, vn) \
__asm__ __volatile__ ( \
"cntlzw %[n], %[a] \n\t" \
: [n] "=r" (vn) \
: [a] "r" (va) \
)
#else /* !defined(__APPLE__) */
/* Multiply va by vb and store double size result in: vh | vl */ /* Multiply va by vb and store double size result in: vh | vl */
#define SP_ASM_MUL(vl, vh, va, vb) \ #define SP_ASM_MUL(vl, vh, va, vb) \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
@ -3772,6 +4072,8 @@ static WC_INLINE sp_int_digit sp_div_word(sp_int_digit hi, sp_int_digit lo,
: [a] "r" (va) \ : [a] "r" (va) \
) )
#endif /* !defined(__APPLE__) */
#define SP_INT_ASM_AVAILABLE #define SP_INT_ASM_AVAILABLE
#endif /* WOLFSSL_SP_PPC && SP_WORD_SIZE == 64 */ #endif /* WOLFSSL_SP_PPC && SP_WORD_SIZE == 64 */

8
wolfssl/wolfcrypt/types.h
View File

@ -162,16 +162,16 @@ decouple library dependencies with standard string, memory and so on.
#elif !defined(__BCPLUSPLUS__) && !defined(__EMSCRIPTEN__) #elif !defined(__BCPLUSPLUS__) && !defined(__EMSCRIPTEN__)
#if !defined(SIZEOF_LONG_LONG) && !defined(SIZEOF_LONG) #if !defined(SIZEOF_LONG_LONG) && !defined(SIZEOF_LONG)
#if (defined(__alpha__) || defined(__ia64__) || \ #if (defined(__alpha__) || defined(__ia64__) || \
defined(_ARCH_PPC64) || defined(__mips64) || \ defined(_ARCH_PPC64) || defined(__ppc64__) || \
defined(__x86_64__) || defined(__s390x__ ) || \ defined(__x86_64__) || defined(__s390x__ ) || \
((defined(sun) || defined(__sun)) && \ ((defined(sun) || defined(__sun)) && \
(defined(LP64) || defined(_LP64))) || \ (defined(LP64) || defined(_LP64))) || \
(defined(__riscv_xlen) && (__riscv_xlen == 64)) || \ (defined(__riscv_xlen) && (__riscv_xlen == 64)) || \
defined(__aarch64__) || \ defined(__aarch64__) || defined(__mips64) || \
(defined(__DCC__) && (defined(__LP64) || defined(__LP64__)))) (defined(__DCC__) && (defined(__LP64) || defined(__LP64__))))
/* long should be 64bit */ /* long should be 64bit */
#define SIZEOF_LONG 8 #define SIZEOF_LONG 8
#elif defined(__i386__) || defined(__CORTEX_M3__) #elif defined(__i386__) || defined(__CORTEX_M3__) || defined(__ppc__)
/* long long should be 64bit */ /* long long should be 64bit */
#define SIZEOF_LONG_LONG 8 #define SIZEOF_LONG_LONG 8
#endif #endif
@ -234,7 +234,7 @@ decouple library dependencies with standard string, memory and so on.
defined(__x86_64__) || defined(_M_X64)) || \ defined(__x86_64__) || defined(_M_X64)) || \
defined(__aarch64__) || defined(__sparc64__) || defined(__s390x__ ) || \ defined(__aarch64__) || defined(__sparc64__) || defined(__s390x__ ) || \
(defined(__riscv_xlen) && (__riscv_xlen == 64)) || defined(_M_ARM64) || \ (defined(__riscv_xlen) && (__riscv_xlen == 64)) || defined(_M_ARM64) || \
defined(__aarch64__) || \ defined(__aarch64__) || defined(__ppc64__) || \
(defined(__DCC__) && (defined(__LP64) || defined(__LP64__))) (defined(__DCC__) && (defined(__LP64) || defined(__LP64__)))
#define WC_64BIT_CPU #define WC_64BIT_CPU
#elif (defined(sun) || defined(__sun)) && \ #elif (defined(sun) || defined(__sun)) && \

4
wolfssl/wolfcrypt/wc_port.h
View File

@ -1106,7 +1106,7 @@ WOLFSSL_ABI WOLFSSL_API int wolfCrypt_Cleanup(void);
#endif #endif
/* PowerPC time_t is int */ /* PowerPC time_t is int */
#ifdef __PPC__ #if defined(__PPC__) || defined(__ppc__)
#define TIME_T_NOT_64BIT #define TIME_T_NOT_64BIT
#endif #endif
@ -1279,7 +1279,7 @@ WOLFSSL_ABI WOLFSSL_API int wolfCrypt_Cleanup(void);
#define XFENCE() XASM_VOLATILE("isb") #define XFENCE() XASM_VOLATILE("isb")
#elif defined(__riscv) #elif defined(__riscv)
#define XFENCE() XASM_VOLATILE("fence") #define XFENCE() XASM_VOLATILE("fence")
#elif defined(__PPC__) #elif defined(__PPC__) || defined(__POWERPC__)
#define XFENCE() XASM_VOLATILE("isync; sync") #define XFENCE() XASM_VOLATILE("isync; sync")
#else #else
#define XFENCE() WC_DO_NOTHING #define XFENCE() WC_DO_NOTHING