mirror of https://github.com/wolfSSL/wolfssl.git
Espressif benchmark update
gojimmypi
parent
2c9208b0c6
commit
4bd78e5e31
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@ -49,6 +49,10 @@
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*
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* set the default devId for cryptocb to the value instead of INVALID_DEVID
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* WC_USE_DEVID=0x1234
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*
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* Turn on benchmark timing debugging (CPU Cycles, RTOS ticks, etc)
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* DEBUG_WOLFSSL_BENCHMARK_TIMING
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*
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*/
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@ -226,6 +230,7 @@
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/* default units per second. See WOLFSSL_BENCHMARK_FIXED_UNITS_* to change */
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#define WOLFSSL_FIXED_UNIT "MB" /* may be re-set by fixed units */
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#define MILLION_VALUE 1000000.0
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#ifdef BENCH_MICROSECOND
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#define WOLFSSL_FIXED_TIME_UNIT "μs"
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@ -296,20 +301,46 @@
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#endif /* WOLFSSL_NO_FLOAT_FMT */
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#ifdef WOLFSSL_ESPIDF
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#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6)
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#ifdef configTICK_RATE_HZ
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/* Define CPU clock cycles per tick of FreeRTOS clock
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* CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ is typically a value like 240
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* configTICK_RATE_HZ is typically 100 or 1000.
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**/
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#define CPU_TICK_CYCLES ( \
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(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * MILLION_VALUE) \
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/ configTICK_RATE_HZ \
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)
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#endif
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#if defined(CONFIG_IDF_TARGET_ESP32C2)
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#include "driver/gptimer.h"
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static gptimer_handle_t esp_gptimer = NULL;
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static gptimer_config_t esp_timer_config = {
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.clk_src = GPTIMER_CLK_SRC_DEFAULT,
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.direction = GPTIMER_COUNT_UP,
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.resolution_hz = CONFIG_XTAL_FREQ * 1000000,
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.resolution_hz = CONFIG_XTAL_FREQ * 100000,
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};
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#elif defined(CONFIG_IDF_TARGET_ESP32C3) || \
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defined(CONFIG_IDF_TARGET_ESP32C6)
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#include <esp_cpu.h>
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#include "driver/gptimer.h"
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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#define RESOLUTION_SCALE 100
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static gptimer_handle_t esp_gptimer = NULL;
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static gptimer_config_t esp_timer_config = {
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.clk_src = GPTIMER_CLK_SRC_DEFAULT,
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.direction = GPTIMER_COUNT_UP,
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.resolution_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * (MILLION_VALUE / RESOLUTION_SCALE), /* CONFIG_XTAL_FREQ = 40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ = 160 */
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};
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#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
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#elif defined(CONFIG_IDF_TARGET_ESP32) || \
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defined(CONFIG_IDF_TARGET_ESP32S2) || \
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defined(CONFIG_IDF_TARGET_ESP32S3)
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#include <xtensa/hal.h>
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#elif defined(CONFIG_IDF_TARGET_ESP32H2)
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#else
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#error "CONFIG_IDF_TARGET not implemented"
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#endif
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#include <esp_log.h>
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#endif /* WOLFSSL_ESPIDF */
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@ -1212,67 +1243,149 @@ static const char* bench_result_words3[][5] = {
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(void)XSNPRINTF(b + XSTRLEN(b), n - XSTRLEN(b), FLT_FMT_PREC ",\n", \
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FLT_FMT_PREC_ARGS(6, (double)total_cycles / (count*s)))
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#elif defined(WOLFSSL_ESPIDF)
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static THREAD_LS_T word64 begin_cycles;
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static THREAD_LS_T word64 total_cycles;
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/* the return value */
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static THREAD_LS_T word64 _xthal_get_ccount_ex = 0;
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/* the last value seen, adjusted for an overflow */
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static THREAD_LS_T word64 _xthal_get_ccount_last = 0;
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/* TAG for ESP_LOGx() */
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static const char* TAG = "wolfssl_benchmark";
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#define HAVE_GET_CYCLES
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#define INIT_CYCLE_COUNTER
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static WC_INLINE word64 get_xtensa_cycles(void);
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static THREAD_LS_T word64 begin_cycles;
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static THREAD_LS_T word64 begin_cycles_ticks;
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static THREAD_LS_T word64 end_cycles;
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static THREAD_LS_T word64 total_cycles;
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/* WARNING the hal UINT xthal_get_ccount() quietly rolls over. */
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#define BEGIN_ESP_CYCLES begin_cycles = (get_xtensa_cycles());
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/* the return value, as a global var */
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static THREAD_LS_T word64 _esp_get_cycle_count_ex = 0;
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/* the last value seen, adjusted for an overflow, as a global var */
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static THREAD_LS_T word64 _esp_cpu_count_last = 0;
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static THREAD_LS_T TickType_t last_tickCount = 0; /* last FreeRTOS value */
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/* esp_get_cpu_benchmark_cycles(void):
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*
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* Architecture-independant CPU clock counter.
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* WARNING: the hal UINT xthal_get_ccount() quietly rolls over. */
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static WC_INLINE word64 esp_get_cpu_benchmark_cycles(void);
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/* Some vars for debugging, compare ticks to cycles */
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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static THREAD_LS_T word64 _esp_cpu_timer_last = 0;
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static THREAD_LS_T word64 _esp_cpu_timer_diff = 0;
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static THREAD_LS_T word64 _xthal_get_ccount_exAlt = 0;
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static THREAD_LS_T word64 _xthal_get_ccount_exDiff = 0;
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#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
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/* The ESP32 (both Xtensa and RISC-V have raw CPU counters). */
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#define HAVE_GET_CYCLES
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#define INIT_CYCLE_COUNTER do { \
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ESP_LOGV(TAG, "INIT_CYCLE_COUNTER"); \
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esp_cpu_set_cycle_count(0); \
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} while (0);
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#define BEGIN_ESP_CYCLES do { \
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ESP_LOGV(TAG, "BEGIN_ESP_CYCLES"); \
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begin_cycles = esp_get_cpu_benchmark_cycles(); \
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begin_cycles_ticks = xTaskGetTickCount(); \
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} while (0);
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/* since it rolls over, we have something that will tolerate one */
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#define END_ESP_CYCLES \
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ESP_LOGV(TAG,"%llu - %llu", \
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get_xtensa_cycles(), \
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begin_cycles \
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); \
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total_cycles = (get_xtensa_cycles() - begin_cycles);
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#define END_ESP_CYCLES \
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end_cycles = esp_get_cpu_benchmark_cycles(); \
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ESP_LOGV(TAG,"END_ESP_CYCLES %llu - %llu", \
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end_cycles, \
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begin_cycles \
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); \
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total_cycles = (end_cycles - begin_cycles);
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#define SHOW_ESP_CYCLES(b, n, s) \
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(void)XSNPRINTF(b + XSTRLEN(b), n - XSTRLEN(b), \
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" %s = " FLT_FMT_PREC2 "\n", \
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bench_result_words1[lng_index][2], \
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FLT_FMT_PREC2_ARGS(6, 2, (double)total_cycles / (count*s)) \
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)
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(void)XSNPRINTF(b + XSTRLEN(b), n - XSTRLEN(b), \
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" %s = " FLT_FMT_PREC2 "\n", \
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bench_result_words1[lng_index][2], \
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FLT_FMT_PREC2_ARGS(6, 2, (double)total_cycles / (count*s)) \
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)
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#define SHOW_ESP_CYCLES_CSV(b, n, s) \
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(void)XSNPRINTF(b + XSTRLEN(b), n - XSTRLEN(b), FLT_FMT_PREC ",\n", \
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FLT_FMT_PREC_ARGS(6, (double)total_cycles / (count*s)))
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(void)XSNPRINTF(b + XSTRLEN(b), n - XSTRLEN(b), FLT_FMT_PREC ",\n", \
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FLT_FMT_PREC_ARGS(6, (double)total_cycles / (count*s)))
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/* xthal_get_ccount_ex() is a single-overflow-tolerant extension to
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** the Espressif `unsigned xthal_get_ccount()` which is known to overflow
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** at least once during full benchmark tests.
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*/
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uint64_t xthal_get_ccount_ex()
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{
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/* reminder: unsigned long long max = 18,446,744,073,709,551,615 */
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/* the currently observed clock counter value */
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#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6)
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uint64_t thisVal = 0;
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ESP_ERROR_CHECK(gptimer_get_raw_count(esp_gptimer, &thisVal));
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#else
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/* reminder unsupported CONFIG_IDF_TARGET captured above */
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uint64_t thisVal = xthal_get_ccount();
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#endif
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/* if the current value is less than the previous value,
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** we likely overflowed at least once.
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*/
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if (thisVal < _xthal_get_ccount_last)
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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/* 64 bit, unisgned, absolute difference
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* used in CPU cycle counter debug calcs. */
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static uint64_t esp_cycle_abs_diff(uint64_t x, uint64_t y)
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{
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/* Warning: we assume the return type of xthal_get_ccount()
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** will always be unsigned int to add UINT_MAX.
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uint64_t ret;
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ret = (x > y) ? (x - y) : (y - x);
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return ret;
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}
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#endif
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/* esp_get_cycle_count_ex() is a single-overflow-tolerant extension to
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** the Espressif `unsigned xthal_get_ccount()` (Xtensa) or
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** `esp_cpu_get_cycle_count` (RISC-V) which are known to overflow
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** at least once during full benchmark tests.
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**
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** To test timing overflow, add a delay longer than max cycles:
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** vTaskDelay( (const TickType_t)(configTICK_RATE_HZ * 17 * 5) );
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*/
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uint64_t esp_get_cycle_count_ex()
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{
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/* reminder: unsigned long long max = 18,446,744,073,709,551,615 */
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/* unsigned int max = 4,294,967,295 */
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uint64_t thisVal = 0; /* CPU counter, "this current value" as read. */
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uint64_t thisIncrement = 0; /* The adjusted increment amount. */
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uint64_t expected_diff = 0; /* FreeRTOS esimated expected CPU diff. */
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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uint32_t tickCount = 0; /* Currrent rtos tick counter. */
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uint32_t tickDiff = 0; /* Tick difference from last check. */
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uint32_t tickBeginDiff = 0; /* Tick difference from beginning. */
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#endif
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#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
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defined(CONFIG_IDF_TARGET_ESP32C3) || \
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defined(CONFIG_IDF_TARGET_ESP32C6)
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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uint64_t thisTimerVal = 0; /* Timer Value as alternate to compare */
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uint64_t diffDiff = 0; /* Difference between CPU & Timer differences:
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* (current - last) */
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ESP_ERROR_CHECK(gptimer_get_raw_count(esp_gptimer, &thisTimerVal));
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thisTimerVal = thisTimerVal * RESOLUTION_SCALE;
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#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
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thisVal = esp_cpu_get_cycle_count();
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#elif defined(CONFIG_IDF_TARGET_ESP32H2)
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thisVal = esp_cpu_get_cycle_count();
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#else
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/* TODO: Why doesn't esp_cpu_get_cycle_count work for Xtensa?
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* Calling current_time(1) to reset time causes thisVal overflow,
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* on Xtensa, but not on RISC-V architecture. See also, below */
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#ifndef __XTENSA__
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thisVal = esp_cpu_get_cycle_count();
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#else
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thisVal = xthal_get_ccount(); /* or esp_cpu_get_cycle_count(); */
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#endif
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#endif
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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{
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tickCount = xTaskGetTickCount(); /* Our local FreeRTOS tick count */
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tickDiff = tickCount - last_tickCount; /* ticks since bench start */
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expected_diff = CPU_TICK_CYCLES * tickDiff; /* CPU expected count */
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ESP_LOGV(TAG, "CPU_TICK_CYCLES = %d", (int)CPU_TICK_CYCLES);
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ESP_LOGV(TAG, "tickCount = %lu", tickCount);
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ESP_LOGV(TAG, "last_tickCount = %lu", last_tickCount);
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ESP_LOGV(TAG, "tickDiff = %lu", tickDiff);
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ESP_LOGV(TAG, "expected_diff1 = %llu", expected_diff);
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}
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#endif
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/* If either thisVal is smaller than last (overflow), and/or the
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* expected value calculated from FreeRTOS tick difference that would
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* have never fit into an unsigned 32 bit integer anyhow... then we
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* need to adjust thisVal to save. */
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if ( (thisVal < _esp_cpu_count_last) || (expected_diff > UINT_MAX) )
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{
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/* Warning: we assume the return type of esp_cpu_get_cycle_count()
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** will always be unsigned int (or uint32_t) to add UINT_MAX.
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**
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** NOTE for long duration between calls with multiple overflows:
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**
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@ -1283,22 +1396,109 @@ static const char* bench_result_words3[][5] = {
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** as well call xthal_get_ccount_ex() with no more than one
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** overflow CPU tick count, all will be well.
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*/
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ESP_LOGV(TAG, "Alert: Detected xthal_get_ccount overflow, "
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"adding %ull", UINT_MAX);
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thisVal += (word64)UINT_MAX;
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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ESP_LOGW(TAG,
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"Alert: Detected xthal_get_ccount overflow at %llu, "
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"adding UINT_MAX.",
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thisVal);
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#endif
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/* double check expected diff calc */
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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expected_diff = (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * MILLION_VALUE)
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* tickDiff / configTICK_RATE_HZ;
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ESP_LOGI(TAG, "expected_diff2 = %llu", expected_diff);
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#endif
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if (expected_diff > UINT_MAX) {
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/* The number of cycles expected from FreeRTOS ticks is
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* greater than the maximum size of an unsigned 32-bit
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* integer, meaning multiple overflows occured. */
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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ESP_LOGW(TAG, "expected_diff > UINT_MAX (%u)", UINT_MAX);
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#endif
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thisVal += expected_diff; /* FreeRTOS calc to our 64 bit val */
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}
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else {
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thisVal += (word64)UINT_MAX; /* add 32 bit max to our 64 bit */
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}
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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{
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tickBeginDiff = tickCount - begin_cycles_ticks;
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ESP_LOGI(TAG, "begin_cycles_ticks = %llu", begin_cycles_ticks);
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ESP_LOGI(TAG, "tickDiff = %lu", tickDiff);
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ESP_LOGI(TAG, "expected_diff = %llu", expected_diff);
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ESP_LOGI(TAG, "tickBeginDiff = %lu", tickBeginDiff);
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ESP_LOGW(TAG, "");
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}
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#endif
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}
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else {
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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ESP_LOGI(TAG, "thisVal, read CPU = %llu", thisVal);
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#endif
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} /* if thisVal adjustment check */
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/* adjust our actual returned value that takes into account overflow */
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_xthal_get_ccount_ex += (thisVal - _xthal_get_ccount_last);
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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if (thisTimerVal < _esp_cpu_timer_last)
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{
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ESP_LOGW(TAG, "Alert: Detected xthal_get_ccountAlt overflow, "
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"adding %ull", UINT_MAX);
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thisTimerVal += (word64)UINT_MAX;
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}
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/* Check an alternate counter using a timer */
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/* all of this took some time, so reset the "last seen" value */
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#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6)
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ESP_ERROR_CHECK(gptimer_get_raw_count(esp_gptimer,
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&_xthal_get_ccount_last));
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#else
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_xthal_get_ccount_last = xthal_get_ccount();
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#endif
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return _xthal_get_ccount_ex;
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_esp_cpu_timer_diff = esp_cycle_abs_diff(_esp_cpu_count_last, _esp_cpu_timer_last);
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#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
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/* Adjust our actual returned value that takes into account overflow,
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* increment 64 bit extended total by this 32 bit differential: */
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thisIncrement = (thisVal - _esp_cpu_count_last);
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#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
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ESP_LOGI(TAG, "thisIncrement = %llu", thisIncrement);
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#endif
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/* Add our adjustment, taking into account overflows (see above) */
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_esp_get_cycle_count_ex += thisIncrement;
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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_xthal_get_ccount_exDiff = esp_cycle_abs_diff(_esp_get_cycle_count_ex, _xthal_get_ccount_exAlt);
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_xthal_get_ccount_exAlt += (thisTimerVal - _esp_cpu_timer_last);
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diffDiff = esp_cycle_abs_diff(_xthal_get_ccount_exDiff, _esp_cpu_timer_diff);
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#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
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/* all of this took some time, so reset the "last seen" value
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* for the next measurement. */
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#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
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defined(CONFIG_IDF_TARGET_ESP32C3) || \
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defined(CONFIG_IDF_TARGET_ESP32C6)
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{
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#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
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ESP_ERROR_CHECK(gptimer_get_raw_count(esp_gptimer,
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&_esp_cpu_timer_last));
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ESP_LOGI(TAG, "thisVal = %llu", thisVal);
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ESP_LOGI(TAG, "thisTimerVal = %llu", thisTimerVal);
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ESP_LOGI(TAG, "diffDiff = %llu", diffDiff);
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ESP_LOGI(TAG, "_xthal_get_ccount_exDiff = %llu", _xthal_get_ccount_exDiff);
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#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
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_esp_cpu_count_last = esp_cpu_get_cycle_count();
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ESP_LOGV(TAG, "_xthal_get_ccount_last = %llu", _esp_cpu_count_last);
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}
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#elif defined(CONFIG_IDF_TARGET_ESP32H2)
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_esp_cpu_count_last = esp_cpu_get_cycle_count();
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#else
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/* TODO: Why doesn't esp_cpu_get_cycle_count work for Xtensa
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* when resetting CPU cycle counter? FreeRTOS tick collison?
|
||||
* thisVal = esp_cpu_get_cycle_count(); See also, above
|
||||
* or thisVal = xthal_get_ccount(); */
|
||||
_esp_cpu_count_last = esp_cpu_get_cycle_count();
|
||||
#endif
|
||||
|
||||
/* Return the 64 bit extended total from 32 bit counter. */
|
||||
return _esp_get_cycle_count_ex;
|
||||
}
|
||||
|
||||
/* implement other architecture cycle counters here */
|
||||
|
|
@ -1911,9 +2111,10 @@ static WC_INLINE void bench_stats_start(int* count, double* start)
|
|||
*start = current_time(1);
|
||||
|
||||
#ifdef WOLFSSL_ESPIDF
|
||||
ESP_LOGV(TAG, "finish total_cycles = %llu, start=" FLT_FMT,
|
||||
total_cycles, FLT_FMT_ARGS(*start) );
|
||||
|
||||
#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
|
||||
ESP_LOGI(TAG, "bench_stats_start total_cycles = %llu, start=" FLT_FMT,
|
||||
total_cycles, FLT_FMT_ARGS(*start) );
|
||||
#endif
|
||||
BEGIN_ESP_CYCLES
|
||||
#else
|
||||
BEGIN_INTEL_CYCLES
|
||||
|
|
@ -1931,11 +2132,23 @@ static WC_INLINE void bench_stats_start(int* count, double* start)
|
|||
|
||||
static WC_INLINE int bench_stats_check(double start)
|
||||
{
|
||||
return ((current_time(0) - start) < BENCH_MIN_RUNTIME_SEC
|
||||
int ret = 0;
|
||||
double this_current_time;
|
||||
this_current_time = current_time(0); /* get the timestamp, no reset */
|
||||
#if defined(DEBUG_WOLFSSL_BENCHMARK_TIMING)
|
||||
#if (WOLFSSL_ESPIDF)
|
||||
ESP_LOGI(TAG, "bench_stats_check Current time %f, start %f",
|
||||
this_current_time, start );
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ret = ((this_current_time - start) < BENCH_MIN_RUNTIME_SEC
|
||||
#ifdef BENCH_MICROSECOND
|
||||
* 1000000
|
||||
#endif
|
||||
);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* return text for units and scale the value of blocks as needed */
|
||||
|
|
@ -2106,8 +2319,8 @@ static void bench_stats_sym_finish(const char* desc, int useDeviceID,
|
|||
|
||||
total = current_time(0) - start;
|
||||
|
||||
#ifdef WOLFSSL_ESPIDF
|
||||
ESP_LOGV(TAG, "%s total_cycles = %llu", desc, total_cycles);
|
||||
#if defined(WOLFSSL_ESPIDF) && defined(DEBUG_WOLFSSL_BENCHMARK_TIMING)
|
||||
ESP_LOGI(TAG, "%s total_cycles = %llu", desc, total_cycles);
|
||||
#endif
|
||||
|
||||
#ifdef LINUX_RUSAGE_UTIME
|
||||
|
|
@ -2229,9 +2442,15 @@ static void bench_stats_sym_finish(const char* desc, int useDeviceID,
|
|||
|
||||
#ifdef WOLFSSL_ESPIDF
|
||||
SHOW_ESP_CYCLES_CSV(msg, sizeof(msg), countSz);
|
||||
ESP_LOGV(TAG, "finish total_cycles = %llu", total_cycles);
|
||||
/* implement other cycle counters here */
|
||||
#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
|
||||
ESP_LOGI(TAG, "bench_stats_sym_finish total_cycles = %llu",
|
||||
total_cycles);
|
||||
#endif
|
||||
|
||||
/* implement other cycle counters here */
|
||||
|
||||
#else
|
||||
/* the default cycle counter is Intel */
|
||||
SHOW_INTEL_CYCLES_CSV(msg, sizeof(msg), (unsigned)countSz);
|
||||
#endif
|
||||
} /* if (csv_format == 1) */
|
||||
|
|
@ -11950,20 +12169,93 @@ void bench_sphincsKeySign(byte level, byte optim)
|
|||
int construct_argv();
|
||||
extern char* __argv[22];
|
||||
#endif
|
||||
|
||||
/* current_time(reset)
|
||||
*
|
||||
* Benchmark passage of time, in fractional seconds.
|
||||
* [reset] is non zero to adjust timer or counter to zero
|
||||
*
|
||||
* Use care when repeatedly calling calling. See implementation. */
|
||||
double current_time(int reset)
|
||||
{
|
||||
double ret;
|
||||
#if ESP_IDF_VERSION_MAJOR >= 4
|
||||
TickType_t tickCount;
|
||||
TickType_t tickCount; /* typically 32 bit, local FreeRTOS ticks */
|
||||
#else
|
||||
portTickType tickCount;
|
||||
#endif
|
||||
|
||||
(void) reset;
|
||||
#if defined(__XTENSA__)
|
||||
(void)reset;
|
||||
|
||||
/* tick count == ms, if configTICK_RATE_HZ is set to 1000 */
|
||||
tickCount = xTaskGetTickCount();
|
||||
return (double)tickCount / 1000;
|
||||
if (reset) {
|
||||
/* TODO: Determine a mechanism for reset that does not interfere
|
||||
* with freeRTOS tick. Using this code for Xtensa appears to cause
|
||||
* RTOS tick timer to stick. See "last_tickCount unchanged".
|
||||
ESP_LOGW(TAG, "Current_time() reset!");
|
||||
portTICK_TYPE_ENTER_CRITICAL();
|
||||
{
|
||||
esp_cpu_set_cycle_count((esp_cpu_cycle_count_t)0);
|
||||
_esp_cpu_count_last = xthal_get_ccount();
|
||||
_esp_cpu_count_last = esp_cpu_get_cycle_count();
|
||||
}
|
||||
portTICK_TYPE_EXIT_CRITICAL();
|
||||
*/
|
||||
}
|
||||
#else
|
||||
/* Only reset the CPU counter for RISC-V */
|
||||
if (reset) {
|
||||
ESP_LOGV(TAG, "current_time() reset!");
|
||||
/* TODO: why does Espressif esp_cpu_get_cycle_count() cause
|
||||
* unexpected rollovers in return values for Xtensa but not RISC-V?
|
||||
* See also esp_get_cycle_count_ex() */
|
||||
#ifdef __XTENSA__
|
||||
_esp_cpu_count_last = xthal_get_ccount();
|
||||
#else
|
||||
esp_cpu_set_cycle_count((esp_cpu_cycle_count_t)0);
|
||||
_esp_cpu_count_last = esp_cpu_get_cycle_count();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* tick count == ms, if configTICK_RATE_HZ is set to 1000 */
|
||||
tickCount = xTaskGetTickCount(); /* RTOS ticks, not CPU cycles!
|
||||
The count of ticks since vTaskStartScheduler was called,
|
||||
typiclly in app_startup.c */
|
||||
|
||||
#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
|
||||
ESP_LOGV(TAG, "tickCount = %lu", tickCount);
|
||||
if (tickCount == last_tickCount) {
|
||||
ESP_LOGW(TAG, "last_tickCount unchanged? %lu", tickCount);
|
||||
|
||||
}
|
||||
if (tickCount < last_tickCount) {
|
||||
ESP_LOGW(TAG, "last_tickCount overflow?");
|
||||
}
|
||||
#endif
|
||||
|
||||
if (reset) {
|
||||
#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
|
||||
ESP_LOGW(TAG, "Assign last_tickCount = %lu", tickCount);
|
||||
#endif
|
||||
last_tickCount = tickCount;
|
||||
}
|
||||
else {
|
||||
#ifdef DEBUG_WOLFSSL_BENCHMARK_TIMING
|
||||
ESP_LOGW(TAG, "No Reset last_tickCount = %lu", tickCount);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(configTICK_RATE_HZ) && defined(CONFIG_FREERTOS_HZ)
|
||||
ret = (double)tickCount / configTICK_RATE_HZ;
|
||||
#else
|
||||
ESP_LOGW(TAG, "Warning: configTICK_RATE_HZ not defined,"
|
||||
"assuming 1000 Hz.");
|
||||
ret = (double)(tickCount / 1000.0);
|
||||
#endif /* configTICK_RATE_HZ */
|
||||
|
||||
return ret;
|
||||
} /* current_time */
|
||||
|
||||
#elif defined (WOLFSSL_TIRTOS)
|
||||
|
||||
|
|
@ -12002,7 +12294,7 @@ void bench_sphincsKeySign(byte level, byte optim)
|
|||
{
|
||||
double time_now;
|
||||
double current_s = OS_GetTime() / 1000.0;
|
||||
double current_us = OS_GetTime_us() / 1000000.0;
|
||||
double current_us = OS_GetTime_us() / MILLION_VALUE;
|
||||
time_now = (double)( current_s + current_us);
|
||||
|
||||
(void) reset;
|
||||
|
|
@ -12129,20 +12421,20 @@ void bench_sphincsKeySign(byte level, byte optim)
|
|||
* outside wolfcrypt.
|
||||
*/
|
||||
return (double)rusage.ru_utime.tv_sec +
|
||||
(double)rusage.ru_utime.tv_usec / 1000000.0;
|
||||
(double)rusage.ru_utime.tv_usec / MILLION_VALUE;
|
||||
}
|
||||
|
||||
static void check_for_excessive_stime(const char *desc,
|
||||
const char *desc_extra)
|
||||
{
|
||||
double start_utime = (double)base_rusage.ru_utime.tv_sec +
|
||||
(double)base_rusage.ru_utime.tv_usec / 1000000.0;
|
||||
(double)base_rusage.ru_utime.tv_usec / MILLION_VALUE;
|
||||
double start_stime = (double)base_rusage.ru_stime.tv_sec +
|
||||
(double)base_rusage.ru_stime.tv_usec / 1000000.0;
|
||||
(double)base_rusage.ru_stime.tv_usec / MILLION_VALUE;
|
||||
double cur_utime = (double)cur_rusage.ru_utime.tv_sec +
|
||||
(double)cur_rusage.ru_utime.tv_usec / 1000000.0;
|
||||
(double)cur_rusage.ru_utime.tv_usec / MILLION_VALUE;
|
||||
double cur_stime = (double)cur_rusage.ru_stime.tv_sec +
|
||||
(double)cur_rusage.ru_stime.tv_usec / 1000000.0;
|
||||
(double)cur_rusage.ru_stime.tv_usec / MILLION_VALUE;
|
||||
double stime_utime_ratio =
|
||||
(cur_stime - start_stime) / (cur_utime - start_utime);
|
||||
if (stime_utime_ratio > .1)
|
||||
|
|
@ -12185,9 +12477,12 @@ void bench_sphincsKeySign(byte level, byte optim)
|
|||
#if defined(HAVE_GET_CYCLES)
|
||||
|
||||
#if defined(WOLFSSL_ESPIDF)
|
||||
static WC_INLINE word64 get_xtensa_cycles(void)
|
||||
/* Generic CPU cycle counter for either Xtensa or RISC-V */
|
||||
static WC_INLINE word64 esp_get_cpu_benchmark_cycles(void)
|
||||
{
|
||||
return xthal_get_ccount_ex();
|
||||
/* Reminder for long duration between calls with
|
||||
* multiple overflows will not be detected. */
|
||||
return esp_get_cycle_count_ex();
|
||||
}
|
||||
|
||||
/* implement other architectures here */
|
||||
|
|
@ -12390,25 +12685,18 @@ static int string_matches(const char* arg, const char* str)
|
|||
|
||||
#endif
|
||||
{
|
||||
/* Code for main() or wolf_benchmark_task() */
|
||||
#ifdef WOLFSSL_ESPIDF
|
||||
int argc = construct_argv();
|
||||
char** argv = (char**)__argv;
|
||||
|
||||
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6)
|
||||
ESP_ERROR_CHECK(gptimer_new_timer(&esp_timer_config, &esp_gptimer));
|
||||
ESP_LOGI(TAG, "Enable ESP32-C3 timer ");
|
||||
ESP_ERROR_CHECK(gptimer_enable(esp_gptimer));
|
||||
ESP_ERROR_CHECK(gptimer_start(esp_gptimer));
|
||||
#endif
|
||||
#elif defined(MAIN_NO_ARGS)
|
||||
int argc = 0;
|
||||
char** argv = NULL;
|
||||
|
||||
#endif
|
||||
|
||||
return wolfcrypt_benchmark_main(argc, argv);
|
||||
}
|
||||
#endif /* NO_MAIN_DRIVER && NO_MAIN_FUNCTION */
|
||||
#endif /* !NO_MAIN_DRIVER && !NO_MAIN_FUNCTION */
|
||||
|
||||
int wolfcrypt_benchmark_main(int argc, char** argv)
|
||||
{
|
||||
|
|
@ -12671,6 +12959,22 @@ int wolfcrypt_benchmark_main(int argc, char** argv)
|
|||
else
|
||||
#endif
|
||||
{
|
||||
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
|
||||
defined(CONFIG_IDF_TARGET_ESP32C3) || \
|
||||
defined(CONFIG_IDF_TARGET_ESP32C6)
|
||||
{
|
||||
#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
|
||||
if (esp_gptimer == NULL) {
|
||||
ESP_ERROR_CHECK(gptimer_new_timer(&esp_timer_config,
|
||||
&esp_gptimer) );
|
||||
}
|
||||
ESP_ERROR_CHECK(gptimer_enable(esp_gptimer));
|
||||
ESP_ERROR_CHECK(gptimer_start(esp_gptimer));
|
||||
ESP_LOGI(TAG, "Enable %s timer", CONFIG_IDF_TARGET);
|
||||
#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_STACK_SIZE
|
||||
ret = StackSizeCheck(NULL, benchmark_test);
|
||||
#else
|
||||
|
|
@ -12678,6 +12982,17 @@ int wolfcrypt_benchmark_main(int argc, char** argv)
|
|||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
|
||||
defined(CONFIG_IDF_TARGET_ESP32C3) || \
|
||||
defined(CONFIG_IDF_TARGET_ESP32C6)
|
||||
{
|
||||
#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
|
||||
ESP_ERROR_CHECK(gptimer_stop(esp_gptimer));
|
||||
ESP_ERROR_CHECK(gptimer_disable(esp_gptimer));
|
||||
#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* !NO_MAIN_DRIVER */
|
||||
|
|
|
|||
Loading…
Reference in New Issue