mirror of https://github.com/wolfSSL/wolfssl.git
Merge pull request #5358 from SparkiDev/sp_int_armv6
SP int ARM32: replace clz instruction when not supportedpull/5364/head
commit
6cc2665a81
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@ -1022,10 +1022,31 @@ static WC_INLINE sp_int_digit sp_div_word(sp_int_digit hi, sp_int_digit lo,
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sp_int_digit d)
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{
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sp_int_digit r = 0;
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#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
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static const char debruijn32[32] = {
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0, 31, 9, 30, 3, 8, 13, 29, 2, 5, 7, 21, 12, 24, 28, 19,
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1, 10, 4, 14, 6, 22, 25, 20, 11, 15, 23, 26, 16, 27, 17, 18
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};
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static const sp_uint32 debruijn32_mul = 0x076be629;
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#endif
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__asm__ __volatile__ (
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/* Shift d so that top bit is set. */
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#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
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"ldr r4, %[m]\n\t"
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"mov r5, %[d]\n\t"
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"orr r5, r5, r5, lsr #1\n\t"
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"orr r5, r5, r5, lsr #2\n\t"
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"orr r5, r5, r5, lsr #4\n\t"
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"orr r5, r5, r5, lsr #8\n\t"
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"orr r5, r5, r5, lsr #16\n\t"
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"add r5, r5, #1\n\t"
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"mul r5, r5, r4\n\t"
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"lsr r5, r5, #27\n\t"
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"ldrb r5, [%[t], r5]\n\t"
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#else
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"clz r5, %[d]\n\t"
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#endif
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"rsb r6, r5, #31\n\t"
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"lsl %[d], %[d], r5\n\t"
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"lsl %[hi], %[hi], r5\n\t"
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@ -1081,7 +1102,11 @@ static WC_INLINE sp_int_digit sp_div_word(sp_int_digit hi, sp_int_digit lo,
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"sbc r8, r8, r8\n\t"
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"sub %[r], %[r], r8\n\t"
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: [r] "+r" (r), [hi] "+r" (hi), [lo] "+r" (lo), [d] "+r" (d)
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#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
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: [t] "r" (debruijn32), [m] "m" (debruijn32_mul)
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#else
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:
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#endif
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: "r4", "r5", "r6", "r8", "r9"
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);
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