diff --git a/.gitignore b/.gitignore index 3f73f167e..cfd7970a5 100644 --- a/.gitignore +++ b/.gitignore @@ -81,3 +81,4 @@ cov-int cyassl.tgz *.log *.trs +IDE\MDK-ARM\Projects diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h index 680bdaf38..a88e1bca4 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h @@ -78,7 +78,7 @@ // STM32 Hardware Crypt // STM32F2 Hardware RNG -#define MDK_CONF_STM32F2_RNG 1 +#define MDK_CONF_STM32F2_RNG 0 #if MDK_CONF_STM32F2_RNG == 1 #define STM32F2_RNG #else diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h index a1eb9ea7d..ed2e6d642 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h @@ -76,7 +76,7 @@ // STM32 Hardware Crypt // STM32F2 Hardware RNG -#define MDK_CONF_STM32F2_RNG 1 +#define MDK_CONF_STM32F2_RNG 0 #if MDK_CONF_STM32F2_RNG == 1 #define STM32F2_RNG #else diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h index cd0ff5717..17b644d79 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h @@ -99,7 +99,7 @@ // // STM32 Hardware Crypt // STM32F2 Hardware RNG -#define MDK_CONF_STM32F2_RNG 1 +#define MDK_CONF_STM32F2_RNG 0 #if MDK_CONF_STM32F2_RNG == 1 #define STM32F2_RNG #else @@ -127,19 +127,19 @@ // // CertGen -#define MDK_CONF_CERT_GEN 0 +#define MDK_CONF_CERT_GEN 1 #if MDK_CONF_CERT_GEN == 1 #define CYASSL_CERT_GEN #endif // // KeyGen -#define MDK_CONF_KEY_GEN 0 +#define MDK_CONF_KEY_GEN 1 #if MDK_CONF_KEY_GEN == 1 #define CYASSL_KEY_GEN #endif // // CRL -#define MDK_CONF_DER_LOAD 0 +#define MDK_CONF_DER_LOAD 1 #if MDK_CONF_DER_LOAD == 1 #define CYASSL_DER_LOAD #endif @@ -160,7 +160,7 @@ // MD5, SHA, SHA-256, AES, RC4, ASN, RSA // // MD2 -#define MDK_CONF_MD2 0 +#define MDK_CONF_MD2 1 #if MDK_CONF_MD2 == 1 #define CYASSL_MD2 #endif @@ -173,13 +173,13 @@ // // SHA-384 // This has to be with SHA512 -#define MDK_CONF_SHA384 0 +#define MDK_CONF_SHA384 1 #if MDK_CONF_SHA384 == 1 #define CYASSL_SHA384 #endif // // SHA-512 -#define MDK_CONF_SHA512 0 +#define MDK_CONF_SHA512 1 #if MDK_CONF_SHA512 == 1 #define CYASSL_SHA512 #endif @@ -197,7 +197,7 @@ #endif // // HC128 -#define MDK_CONF_HC128 0 +#define MDK_CONF_HC128 1 #if MDK_CONF_HC128 == 1 #define HAVE_HC128 #endif @@ -210,7 +210,7 @@ // // AEAD -#define MDK_CONF_AEAD 0 +#define MDK_CONF_AEAD 1 #if MDK_CONF_AEAD == 1 #define HAVE_AEAD #endif @@ -222,7 +222,7 @@ #endif // // CAMELLIA -#define MDK_CONF_CAMELLIA 0 +#define MDK_CONF_CAMELLIA 1 #if MDK_CONF_CAMELLIA == 1 #define HAVE_CAMELLIA #endif @@ -261,13 +261,13 @@ #endif // // AESCCM (Turn off Hardware Crypt) -#define MDK_CONF_AESCCM 0 +#define MDK_CONF_AESCCM 1 #if MDK_CONF_AESCCM == 1 #define HAVE_AESCCM #endif // // AESGCM (Turn off Hardware Crypt) -#define MDK_CONF_AESGCM 0 +#define MDK_CONF_AESGCM 1 #if MDK_CONF_AESGCM == 1 #define HAVE_AESGCM #define BUILD_AESGCM diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c index 718919b63..f0959de12 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c @@ -59,7 +59,7 @@ unsigned long inet_addr(const char *cp) /*** tcp_connect is actually associated with following syassl_tcp_connect. ***/ int Cyassl_connect(int sd, const struct sockaddr* sa, int sz) { - int ret ; + int ret = 0 ; #if defined(CYASSL_KEIL_TCP_NET) SOCKADDR_IN addr ; @@ -86,7 +86,7 @@ int Cyassl_connect(int sd, const struct sockaddr* sa, int sz) int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen) { - int ret ; + int ret = 0 ; #if defined(CYASSL_KEIL_TCP_NET) while(1) { @@ -110,7 +110,7 @@ int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen) int Cyassl_recv(int sd, void *buf, size_t len, int flags) { - int ret ; + int ret = 0; #if defined(CYASSL_KEIL_TCP_NET) while(1) { #undef recv /* Go to KEIL TCPnet recv */ @@ -132,7 +132,7 @@ int Cyassl_recv(int sd, void *buf, size_t len, int flags) int Cyassl_send(int sd, const void *buf, size_t len, int flags) { - int ret ; + int ret = 0 ; #if defined(CYASSL_KEIL_TCP_NET) while(1) { @@ -170,40 +170,6 @@ int Cyassl_tcp_select(int sd, int timeout) } #endif -struct tm *Cyassl_MDK_gmtime(const time_t *c) -{ - - RTC_TimeTypeDef RTC_Time ; - RTC_DateTypeDef RTC_Date ; - static struct tm date ; - - RTC_GetTime(RTC_Format_BIN, &RTC_Time) ; - RTC_GetDate(RTC_Format_BIN, &RTC_Date) ; - - date.tm_year = RTC_Date.RTC_Year + 100 ; - date.tm_mon = RTC_Date.RTC_Month - 1 ; - date.tm_mday = RTC_Date.RTC_Date ; - date.tm_hour = RTC_Time.RTC_Hours ; - date.tm_min = RTC_Time.RTC_Minutes ; - date.tm_sec = RTC_Time.RTC_Seconds ; - - #if defined(DEBUG_CYASSL) - { - char msg[100] ; - sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n", - RTC_Date.RTC_Year+2000, RTC_Date.RTC_Month, RTC_Date.RTC_Date, - RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ; - CYASSL_MSG(msg) ; - } - #endif - - return(&date) ; -} - -double current_time() -{ - return ((double)TIM2->CNT/1000000.0) ; -} extern int getkey(void) ; extern int sendchar(int c) ; diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h index c565b6e15..052fe2991 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h @@ -95,13 +95,9 @@ extern int setsockopt(int sockfd, int level, int optname, extern int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, const struct timeval *timeout); - -/** KEIL-RL gmtime ****/ - +/* CyaSSL MDK-ARM time functions */ #include -#include "stm32f2xx_rtc.h" -extern struct tm *gmtime(const time_t *timer); -extern struct tm *Cyassl_MDK_gmtime(const time_t *timer); +struct tm *Cyassl_MDK_gmtime(const time_t *c) ; extern double current_time(void) ; #endif /* CYASSL_KEIL_RL_H */ diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c index f858f71cd..7a39b51f4 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c @@ -30,10 +30,6 @@ #include #include "cyassl_MDK_ARM.h" -#include "stm32f2xx_tim.h" -#include "stm32f2xx_rcc.h" - - /*----------------------------------------------------------------------------- * Initialize a Flash Memory Card *----------------------------------------------------------------------------*/ @@ -87,77 +83,6 @@ __task void tcp_poll (void) } #endif -/*----------------------------------------------------------------------------- - * initialize RTC - *----------------------------------------------------------------------------*/ -#include "stm32f2xx_rtc.h" -#include "stm32f2xx_rcc.h" -#include "stm32f2xx_pwr.h" - -static init_RTC() -{ - RTC_InitTypeDef RTC_InitStruct ; - - RTC_TimeTypeDef RTC_Time ; - RTC_DateTypeDef RTC_Date ; - - - /* Enable the PWR clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - - /* Allow access to RTC */ - PWR_BackupAccessCmd(ENABLE); - -/***Configures the External Low Speed oscillator (LSE)****/ - - RCC_LSEConfig(RCC_LSE_ON); - - /* Wait till LSE is ready */ - while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) - { - } - - /* Select the RTC Clock Source */ - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - - /* Enable the RTC Clock */ - RCC_RTCCLKCmd(ENABLE); - - /* Wait for RTC APB registers synchronisation */ - RTC_WaitForSynchro(); - - /* Calendar Configuration with LSI supposed at 32KHz */ - RTC_InitStruct.RTC_AsynchPrediv = 0x7F; - RTC_InitStruct.RTC_SynchPrediv = 0xFF; - RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24; - RTC_Init(&RTC_InitStruct); - - RTC_GetTime(RTC_Format_BIN, &RTC_Time) ; - RTC_GetDate(RTC_Format_BIN, &RTC_Date) ; -} - -/*----------------------------------------------------------------------------- - * initialize TIM - *----------------------------------------------------------------------------*/ -void init_timer() -{ - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure ; - - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) ; - - TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.TIM_Prescaler = 60; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseStructure.TIM_Period = 0xffffffff; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; - - TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); - - TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure) ; - TIM_Cmd(TIM2, ENABLE) ; -} - #if defined(HAVE_KEIL_RTX) && defined(CYASSL_MDK_SHELL) #define SHELL_STACKSIZE 1000 static unsigned char Shell_stack[SHELL_STACKSIZE] ; @@ -193,11 +118,12 @@ void main_task (void) shell_main() ; #endif #else - + /************************************/ /*** USER APPLICATION HERE ***/ /************************************/ - + printf("USER LOGIC STARTED\n") ; + #endif #ifdef HAVE_KEIL_RTX @@ -217,16 +143,19 @@ void main_task (void) /*** main entry ***/ +extern void init_time(void) ; +extern void SystemInit(void); + int main() { - /* stm32_Init (); STM32 setup */ - + + SystemInit(); + SER_Init() ; #if !defined(NO_FILESYSTEM) init_card () ; /* initializing SD card */ #endif - - init_RTC() ; - init_timer() ; - SER_Init() ; + + init_time() ; + #if defined(DEBUG_CYASSL) printf("Turning ON Debug message\n") ; diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c index d6268fa80..1a0b6ad73 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c @@ -384,39 +384,6 @@ static void ipaddr_comm(void *args) #endif -static void time_main(void *args) -{ - char * datetime ; - RTC_TimeTypeDef RTC_Time ; - RTC_DateTypeDef RTC_Date ; - int year ; - if( args == NULL || ((func_args *)args)->argc == 1) { - RTC_GetTime(RTC_Format_BIN, &RTC_Time) ; - RTC_GetDate(RTC_Format_BIN, &RTC_Date) ; - printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", - RTC_Date.RTC_Month, RTC_Date.RTC_Date, RTC_Date.RTC_Year+2000, - RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 'd' ) { - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d/%d/%d", - (int *)&RTC_Date.RTC_Month, (int *)&RTC_Date.RTC_Date, &year) ; - RTC_Date.RTC_Year = year - 2000 ; - RTC_Date.RTC_WeekDay = 0 ; - RTC_SetDate(RTC_Format_BIN, &RTC_Date) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 't' ) { - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d:%d:%d", - (int *)&RTC_Time.RTC_Hours, - (int *)&RTC_Time.RTC_Minutes, - (int *)&RTC_Time.RTC_Seconds - ) ; - RTC_SetTime(RTC_Format_BIN, &RTC_Time) ; - } else printf("Invalid argument\n") ; -} #if defined(HAVE_KEIL_RTX) diff --git a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c index 9c121dac5..96b6dada2 100644 --- a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c +++ b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c @@ -1,387 +1,401 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - FlashFS - *---------------------------------------------------------------------------- - * Name: FILE_CONFIG.C - * Purpose: Configuration of RL FlashFS by user - * Rev.: V4.50 - *---------------------------------------------------------------------------- - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// File System -// ============== -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define N_FILES 6 - -// CPU Clock Frequency [Hz]<0-1000000000> -// Define the CPU Clock frequency used for -// flash programming and erasing. -#define CPU_CLK 120000000 - -// -// Flash Drive -// ============== -// Enable Embedded Flash Drive [F:] -#define FL0_EN 0 - -// Base address <0x0-0xFFFFF000:0x1000> -// Define the target device Base address -// Default: 0x80000000 -#define FL0_BADR 0x80000000 - -// Device Size <0x4000-0xFFFFF000:0x4000> -// Define the size of Flash device in bytes -// Default: 0x100000 (1MB) -#define FL0_SIZE 0x0200000 - -// Content of Erased Memory <0=>0x00 <0xFF=>0xFF -// Define the initial value for erased Flash data -// Default: 0xFF -#define FL0_INITV 0xFF - -// Device Description file -// Specify a file name with a relative path -// Default: FS_FlashDev.h -#define FL0_HFILE "FS_FlashDev.h" - -// Default Drive [F:] -// Used when Drive letter not specified -#define FL0_DEF 1 - -// -// SPI Flash Drive -// ================== -// Enable SPI Flash Drive [S:] -#define SF0_EN 0 - -// Device Size <0x10000-0xFFFFF000:0x8000> -// Define the size of SPI Flash device in bytes -// Default: 0x100000 (1MB) -#define SF0_SIZE 0x0200000 - -// Content of Erased Memory <0=>0x00 <0xFF=>0xFF -// Define the initial value for erased Flash data -// Default: 0xFF -#define SF0_INITV 0xFF - -// Device Description file -// Specify a file name with a relative path -// Default: FS_SPI_FlashDev.h -#define SF0_HFILE "FS_SPI_FlashDev.h" - -// Default Drive [S:] -// Used when Drive letter not specified -#define SF0_DEF 0 - -// -// RAM Drive -// ============ -// Enable Embedded RAM Drive [R:] -#define RAM0_EN 0 - -// Device Size <0x4000-0xFFFFF000:0x4000> -// Define the size of RAM device in bytes -// Default: 0x40000 -#define RAM0_SIZE 0x004000 - -// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 -// Define number of virtual sectors for RAM device -// Default: 32 -#define RAM0_NSECT 64 - -// Relocate Device Buffer -// Locate RAM Device Buffer at a specific address. -// If not enabled, the linker selects base address. -#define RAM0_RELOC 1 - -// Base address <0x0-0xFFFFF000:0x1000> -// Define the target device Base address. -// Default: 0x81000000 -#define RAM0_BADR 0x81010000 - -// -// Default Drive [R:] -// Used when Drive letter not specified -#define RAM0_DEF 0 - -// -// Memory Card Drive 0 -// ====================== -// Enable Memory Card Drive [M0:] -#define MC0_EN 1 - -// Bus Mode <0=>SD-Native <1=>SPI -// Define Memory Card bus interface mode. -// SD-Native mode needs MCI peripheral. -// SPI mode uses SD Card in SPI mode. -#define MC0_SPI 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define MC0_CASZ 16 - -// Relocate Cache Buffer -// Locate Cache Buffer at a specific address. -// Some devices like NXP LPC23xx require a Cache buffer -// for DMA transfer located at specific address. -#define MC0_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -// For LPC23xx/24xx devices this is USB RAM -// starting at 0x7FD00000. -#define MC0_CADR 0x7FD00000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define MC0_FSJ 0 - -// Default Drive [M0:] -// Used when Drive letter not specified -#define MC0_DEF 1 - -// -// Memory Card Drive 1 -// ====================== -// Enable Memory Card Drive [M1:] -#define MC1_EN 0 - -// Bus Mode <0=>SD-Native <1=>SPI -// Define Memory Card bus interface mode. -// SD-Native mode needs MCI peripheral. -// SPI mode uses SD Card in SPI mode. -#define MC1_SPI 1 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define MC1_CASZ 0 - -// Relocate Cache Buffer -// Locate Cache Buffer at a specific address. -// Some devices like NXP LPC23xx require a Cache buffer -// for DMA transfer located at specific address. -#define MC1_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -// For LPC23xx/24xx devices this is USB RAM -// starting at 0x7FD00000. -#define MC1_CADR 0x7FD00000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define MC1_FSJ 0 - -// Default Drive [M1:] -// Used when Drive letter not specified -#define MC1_DEF 0 - -// -// USB Flash Drive 0 -// ==================== -// Enable USB Flash Drive [U0:] -#define USB0_EN 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define USB0_CASZ 8 - -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define USB0_FSJ 0 - -// Default Drive [U0:] -// Used when Drive letter not specified -#define USB0_DEF 1 - -// -// USB Flash Drive 1 -// ==================== -// Enable USB Flash Drive [U1:] -#define USB1_EN 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define USB1_CASZ 8 - -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define USB1_FSJ 0 - -// Default Drive [U1:] -// Used when Drive letter not specified -#define USB1_DEF 1 - -// -// NAND Flash Drive 0 -// =================== -// Enable NAND Flash Drive [N0:] -#define NAND0_EN 0 - -// Page size <528=> 512 + 16 bytes -// <2112=>2048 + 64 bytes -// <4224=>4096 + 128 bytes -// <8448=>8192 + 256 bytes -// Define program Page size in bytes (User + Spare area). -#define NAND0_PGSZ 2112 - -// Block Size <8=>8 pages <16=>16 pages <32=>32 pages -// <64=>64 pages <128=>128 pages <256=>256 pages -// Define number of pages in a block. -#define NAND0_PGCNT 64 - -// Device Size [blocks] <512-32768> -// Define number of blocks in NAND Flash device. -#define NAND0_BLCNT 4096 - -// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages -// <8=>8 pages <16=>16 pages <32=>32 pages -// Define number of cached Pages. -// Default: 4 pages -#define NAND0_CAPG 2 - -// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks -// <8=>8 blocks <16=>16 blocks <32=>32 blocks -// <64=>64 blocks <128=>128 blocks <256=>256 blocks -// Define number of indexed Flash Blocks. -// Increase this number for better performance. -// Default: 16 blocks -#define NAND0_CABL 16 - -// Software ECC <0=>None <1=>Hamming (SLC) -// Enable software ECC calculation only, -// if not supported by hardware. -#define NAND0_SWECC 1 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define NAND0_CASZ 4 - -// Relocate Cache Buffers -// Use this option to locate Cache buffers -// at specific address in RAM or SDRAM. -#define NAND0_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define base address for Cache Buffers. -#define NAND0_CADR 0x80000000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define NAND0_FSJ 0 - -// Default Drive [N0:] -// Used when Drive letter not specified -#define NAND0_DEF 0 - -// -// NAND Flash Drive 1 -// =================== -// Enable NAND Flash Drive [N1:] -#define NAND1_EN 0 - -// Page size <528=> 512 + 16 bytes -// <2112=>2048 + 64 bytes -// <4224=>4096 + 128 bytes -// <8448=>8192 + 256 bytes -// Define program Page size in bytes (User + Spare area). -#define NAND1_PGSZ 2112 - -// Block Size <8=>8 pages <16=>16 pages <32=>32 pages -// <64=>64 pages <128=>128 pages <256=>256 pages -// Define number of pages in a block. -#define NAND1_PGCNT 32 - -// Device Size [blocks] <512-32768> -// Define number of blocks in NAND Flash device. -#define NAND1_BLCNT 512 - -// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages -// <8=>8 pages <16=>16 pages <32=>32 pages -// Define number of cached Pages. -// Default: 4 pages -#define NAND1_CAPG 4 - -// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks -// <8=>8 blocks <16=>16 blocks <32=>32 blocks -// <64=>64 blocks <128=>128 blocks <256=>256 blocks -// Define number of indexed Flash Blocks. -// Increase this number for better performance. -// Default: 16 blocks -#define NAND1_CABL 16 - -// Software ECC <0=>None <1=>Hamming (SLC) -// Enable software ECC calculation only, -// if not supported by hardware. -#define NAND1_SWECC 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define NAND1_CASZ 4 - -// Relocate Cache Buffers -// Use this option to locate Cache buffers -// at specific address in RAM or SDRAM. -#define NAND1_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define base address for Cache Buffers. -#define NAND1_CADR 0x80000000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define NAND1_FSJ 0 - -// Default Drive [N1:] -// Used when Drive letter not specified -#define NAND1_DEF 0 - -// - -//------------- <<< end of configuration section >>> ----------------------- - -#ifndef __NO_FILE_LIB_C -#include -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * RL-ARM - FlashFS + *---------------------------------------------------------------------------- + * Name: FILE_CONFIG.C + * Purpose: Configuration of RL FlashFS by user + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// File System +// ============== +// Define File System global parameters + +// Number of open files <4-16> +// Define number of files that can be +// opened at the same time. +// Default: 8 +#define N_FILES 6 + +// FAT Name Cache Size <0-1000000> +// Define number of cached FAT file or directory names. +// 48 bytes of RAM is required for each cached name. +#define FAT_NAME_CACNT 0 + +// Relocate FAT Name Cache Buffer +// Locate Cache Buffer at a specific address. +#define FAT_NAME_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +#define FAT_NAME_CADR 0x60000000 + +// +// CPU Clock Frequency [Hz]<0-1000000000> +// Define the CPU Clock frequency used for +// flash programming and erasing. +#define CPU_CLK 180000000 + +// +// Flash Drive +// ============== +// Enable Embedded Flash Drive [F:] +#define FL0_EN 0 + +// Base address <0x0-0xFFFFF000:0x1000> +// Define the target device Base address +// Default: 0x80000000 +#define FL0_BADR 0x80000000 + +// Device Size <0x4000-0xFFFFF000:0x4000> +// Define the size of Flash device in bytes +// Default: 0x100000 (1MB) +#define FL0_SIZE 0x0200000 + +// Content of Erased Memory <0=>0x00 <0xFF=>0xFF +// Define the initial value for erased Flash data +// Default: 0xFF +#define FL0_INITV 0xFF + +// Device Description file +// Specify a file name with a relative path +// Default: FS_FlashDev.h +#define FL0_HFILE "FS_FlashDev.h" + +// Default Drive [F:] +// Used when Drive letter not specified +#define FL0_DEF 1 + +// +// SPI Flash Drive +// ================== +// Enable SPI Flash Drive [S:] +#define SF0_EN 0 + +// Device Size <0x10000-0xFFFFF000:0x8000> +// Define the size of SPI Flash device in bytes +// Default: 0x100000 (1MB) +#define SF0_SIZE 0x0200000 + +// Content of Erased Memory <0=>0x00 <0xFF=>0xFF +// Define the initial value for erased Flash data +// Default: 0xFF +#define SF0_INITV 0xFF + +// Device Description file +// Specify a file name with a relative path +// Default: FS_SPI_FlashDev.h +#define SF0_HFILE "FS_SPI_FlashDev.h" + +// Default Drive [S:] +// Used when Drive letter not specified +#define SF0_DEF 0 + +// +// RAM Drive +// ============ +// Enable Embedded RAM Drive [R:] +#define RAM0_EN 0 + +// Device Size <0x4000-0xFFFFF000:0x4000> +// Define the size of RAM device in bytes +// Default: 0x40000 +#define RAM0_SIZE 0x004000 + +// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 +// Define number of virtual sectors for RAM device +// Default: 32 +#define RAM0_NSECT 64 + +// Relocate Device Buffer +// Locate RAM Device Buffer at a specific address. +// If not enabled, the linker selects base address. +#define RAM0_RELOC 1 + +// Base address <0x0-0xFFFFF000:0x1000> +// Define the target device Base address. +// Default: 0x81000000 +#define RAM0_BADR 0x81010000 + +// +// Default Drive [R:] +// Used when Drive letter not specified +#define RAM0_DEF 0 + +// +// Memory Card Drive 0 +// ====================== +// Enable Memory Card Drive [M0:] +#define MC0_EN 1 + +// Bus Mode <0=>SD-Native <1=>SPI +// Define Memory Card bus interface mode. +// SD-Native mode needs MCI peripheral. +// SPI mode uses SD Card in SPI mode. +#define MC0_SPI 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define MC0_CASZ 4 + +// Relocate Cache Buffer +// Locate Cache Buffer at a specific address. +// Some devices like NXP LPC23xx require a Cache buffer +// for DMA transfer located at specific address. +#define MC0_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +// For LPC23xx/24xx devices this is USB RAM +// starting at 0x7FD00000. +#define MC0_CADR 0x7FD00000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define MC0_FSJ 0 + +// Default Drive [M0:] +// Used when Drive letter not specified +#define MC0_DEF 1 + +// +// Memory Card Drive 1 +// ====================== +// Enable Memory Card Drive [M1:] +#define MC1_EN 0 + +// Bus Mode <0=>SD-Native <1=>SPI +// Define Memory Card bus interface mode. +// SD-Native mode needs MCI peripheral. +// SPI mode uses SD Card in SPI mode. +#define MC1_SPI 1 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define MC1_CASZ 0 + +// Relocate Cache Buffer +// Locate Cache Buffer at a specific address. +// Some devices like NXP LPC23xx require a Cache buffer +// for DMA transfer located at specific address. +#define MC1_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +// For LPC23xx/24xx devices this is USB RAM +// starting at 0x7FD00000. +#define MC1_CADR 0x7FD00000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define MC1_FSJ 0 + +// Default Drive [M1:] +// Used when Drive letter not specified +#define MC1_DEF 0 + +// +// USB Flash Drive 0 +// ==================== +// Enable USB Flash Drive [U0:] +#define USB0_EN 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define USB0_CASZ 8 + +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define USB0_FSJ 0 + +// Default Drive [U0:] +// Used when Drive letter not specified +#define USB0_DEF 0 + +// +// USB Flash Drive 1 +// ==================== +// Enable USB Flash Drive [U1:] +#define USB1_EN 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define USB1_CASZ 8 + +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define USB1_FSJ 0 + +// Default Drive [U1:] +// Used when Drive letter not specified +#define USB1_DEF 0 + +// +// NAND Flash Drive 0 +// =================== +// Enable NAND Flash Drive [N0:] +#define NAND0_EN 0 + +// Page size <528=> 512 + 16 bytes +// <2112=>2048 + 64 bytes +// <4224=>4096 + 128 bytes +// <8448=>8192 + 256 bytes +// Define program Page size in bytes (User + Spare area). +#define NAND0_PGSZ 2112 + +// Block Size <8=>8 pages <16=>16 pages <32=>32 pages +// <64=>64 pages <128=>128 pages <256=>256 pages +// Define number of pages in a block. +#define NAND0_PGCNT 64 + +// Device Size [blocks] <512-32768> +// Define number of blocks in NAND Flash device. +#define NAND0_BLCNT 4096 + +// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages +// <8=>8 pages <16=>16 pages <32=>32 pages +// Define number of cached Pages. +// Default: 4 pages +#define NAND0_CAPG 2 + +// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks +// <8=>8 blocks <16=>16 blocks <32=>32 blocks +// <64=>64 blocks <128=>128 blocks <256=>256 blocks +// Define number of indexed Flash Blocks. +// Increase this number for better performance. +// Default: 16 blocks +#define NAND0_CABL 16 + +// Software ECC <0=>None <1=>Hamming (SLC) +// Enable software ECC calculation only, +// if not supported by hardware. +#define NAND0_SWECC 1 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define NAND0_CASZ 4 + +// Relocate Cache Buffers +// Use this option to locate Cache buffers +// at specific address in RAM or SDRAM. +#define NAND0_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define base address for Cache Buffers. +#define NAND0_CADR 0x80000000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define NAND0_FSJ 0 + +// Default Drive [N0:] +// Used when Drive letter not specified +#define NAND0_DEF 0 + +// +// NAND Flash Drive 1 +// =================== +// Enable NAND Flash Drive [N1:] +#define NAND1_EN 0 + +// Page size <528=> 512 + 16 bytes +// <2112=>2048 + 64 bytes +// <4224=>4096 + 128 bytes +// <8448=>8192 + 256 bytes +// Define program Page size in bytes (User + Spare area). +#define NAND1_PGSZ 2112 + +// Block Size <8=>8 pages <16=>16 pages <32=>32 pages +// <64=>64 pages <128=>128 pages <256=>256 pages +// Define number of pages in a block. +#define NAND1_PGCNT 32 + +// Device Size [blocks] <512-32768> +// Define number of blocks in NAND Flash device. +#define NAND1_BLCNT 512 + +// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages +// <8=>8 pages <16=>16 pages <32=>32 pages +// Define number of cached Pages. +// Default: 4 pages +#define NAND1_CAPG 4 + +// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks +// <8=>8 blocks <16=>16 blocks <32=>32 blocks +// <64=>64 blocks <128=>128 blocks <256=>256 blocks +// Define number of indexed Flash Blocks. +// Increase this number for better performance. +// Default: 16 blocks +#define NAND1_CABL 16 + +// Software ECC <0=>None <1=>Hamming (SLC) +// Enable software ECC calculation only, +// if not supported by hardware. +#define NAND1_SWECC 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define NAND1_CASZ 4 + +// Relocate Cache Buffers +// Use this option to locate Cache buffers +// at specific address in RAM or SDRAM. +#define NAND1_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define base address for Cache Buffers. +#define NAND1_CADR 0x80000000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define NAND1_FSJ 0 + +// Default Drive [N1:] +// Used when Drive letter not specified +#define NAND1_DEF 0 + +// + +//------------- <<< end of configuration section >>> ----------------------- + +#ifndef __NO_FILE_LIB_C +#include +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c b/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c index 2d932a2d1..a03892045 100644 --- a/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c +++ b/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c @@ -39,7 +39,7 @@ // Set the stack size for tasks which is assigned by the system. // Default: 512 #ifndef OS_STKSIZE - #define OS_STKSIZE 250 + #define OS_STKSIZE 499 #endif // Check for the stack overflow diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvopt b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvopt new file mode 100644 index 000000000..14992a665 --- /dev/null +++ b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvopt @@ -0,0 +1,1720 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + MDK-RTX-TCP-FS + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 9 + + + + + + + + + + ..\MDK-ARM\config\Dbg_Flash.ini + BIN\ULP2CM3.DLL + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + ULP2CM3 + -UP1135060 -O974 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 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000000000..e25ffe7de --- /dev/null +++ b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvproj @@ -0,0 +1,3455 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
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__RTX USE_STDPERIPH_DRIVER MDK_CONF_RTX_TCP_FS + + ..\MDK-ARM\CyaSSL;../../..;..\LPC43xx\Drivers\include;..\LPC43xx\LPC43xx\Include + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + CyaSSL Apps + + + echoclient.c + 1 + ..\..\..\examples\echoclient\echoclient.c + + + echoserver.c + 1 + ..\..\..\examples\echoserver\echoserver.c + + + test.c + 1 + ..\..\..\ctaocrypt\test\test.c + + + benchmark.c + 1 + ..\..\..\ctaocrypt\benchmark\benchmark.c + + + client.c + 1 + ..\..\..\examples\client\client.c + + + server.c + 1 + ..\..\..\examples\server\server.c + + + shell.c + 1 + ..\MDK-ARM\CyaSSL\shell.c + + + main.c + 1 + ..\MDK-ARM\CyaSSL\main.c + + + cert_data.c + 1 + ..\MDK-ARM\CyaSSL\cert_data.c + + + + + LPC43xx + + + lpc43xx_rtc.c + 1 + ..\LPC43xx\Drivers\source\lpc43xx_rtc.c + + + lpc43xx_timer.c + 1 + ..\LPC43xx\Drivers\source\lpc43xx_timer.c + + + lpc43xx_cgu.c + 1 + ..\LPC43xx\Drivers\source\lpc43xx_cgu.c + + + lpc43xx_scu.c + 1 + ..\LPC43xx\Drivers\source\lpc43xx_scu.c + + + + + MDK-ARM + + + FS_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\FS_CM3.lib + + + RTX_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\\RTX_CM3.lib + + + TCPD_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\TCPD_CM3.lib + + + TCP_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\TCP_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + Serial.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\Serial.c + + + ETH_LPC43xx.c + 1 + C:\Keil\ARM\RL\TCPnet\Drivers\ETH_LPC43xx.c + + + SDIO_LPC43xx.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\SDIO_LPC43xx.c + + + system_LPC43xx.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\system_LPC43xx.c + + + + + CyaSSL Library + + + crl.c + 1 + ..\..\..\src\crl.c + + + internal.c + 1 + ..\..\..\src\internal.c + + + io.c + 1 + ..\..\..\src\io.c + + + keys.c + 1 + ..\..\..\src\keys.c + + + ocsp.c + 1 + ..\..\..\src\ocsp.c + + + sniffer.c + 1 + ..\..\..\src\sniffer.c + + + ssl.c + 1 + ..\..\..\src\ssl.c + + + tls.c + 1 + ..\..\..\src\tls.c + + + ssl-dummy.c + 1 + ..\MDK-ARM\CyaSSL\ssl-dummy.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Crypt/Cipher Library + + + aes.c + 1 + ..\..\..\ctaocrypt\src\aes.c + + + arc4.c + 1 + ..\..\..\ctaocrypt\src\arc4.c + + + asm.c + 1 + ..\..\..\ctaocrypt\src\asm.c + + + asn.c + 1 + ..\..\..\ctaocrypt\src\asn.c + + + camellia.c + 1 + ..\..\..\ctaocrypt\src\camellia.c + + + coding.c + 1 + ..\..\..\ctaocrypt\src\coding.c + + + des3.c + 1 + ..\..\..\ctaocrypt\src\des3.c + + + dh.c + 1 + ..\..\..\ctaocrypt\src\dh.c + + + dsa.c + 1 + ..\..\..\ctaocrypt\src\dsa.c + + + ecc.c + 1 + ..\..\..\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + ..\..\..\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + ..\..\..\ctaocrypt\src\error.c + + + hc128.c + 1 + ..\..\..\ctaocrypt\src\hc128.c + + + hmac.c + 1 + ..\..\..\ctaocrypt\src\hmac.c + + + integer.c + 1 + ..\..\..\ctaocrypt\src\integer.c + + + logging.c + 1 + ..\..\..\ctaocrypt\src\logging.c + + + md2.c + 1 + ..\..\..\ctaocrypt\src\md2.c + + + md4.c + 1 + ..\..\..\ctaocrypt\src\md4.c + + + md5.c + 1 + ..\..\..\ctaocrypt\src\md5.c + + + memory.c + 1 + ..\..\..\ctaocrypt\src\memory.c + + + misc.c + 1 + ..\..\..\ctaocrypt\src\misc.c + + + pwdbased.c + 1 + ..\..\..\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + ..\..\..\ctaocrypt\src\rabbit.c + + + random.c + 1 + ..\..\..\ctaocrypt\src\random.c + + + ripemd.c + 1 + ..\..\..\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + ..\..\..\ctaocrypt\src\rsa.c + + + sha.c + 1 + ..\..\..\ctaocrypt\src\sha.c + + + sha256.c + 1 + ..\..\..\ctaocrypt\src\sha256.c + + + sha512.c + 1 + ..\..\..\ctaocrypt\src\sha512.c + + + tfm.c + 1 + ..\..\..\ctaocrypt\src\tfm.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Configuration + + + File_Config.c + 1 + ..\MDK-ARM\config\File_Config.c + + + Net_Config.c + 1 + ..\MDK-ARM\config\Net_Config.c + + + config.h + 5 + ..\MDK-ARM\CyaSSL\config.h + + + RTX_Conf_CM.c + 1 + ..\MDK-ARM\config\RTX_Conf_CM.c + + + Net_Debug.c + 1 + ..\MDK-ARM\config\Net_Debug.c + + + config-FS.h + 5 + ..\MDK-ARM\CyaSSL\config-FS.h + + + config-RTX-TCP-FS.h + 5 + ..\MDK-ARM\CyaSSL\config-RTX-TCP-FS.h + + + config-BARE-METAL.h + 5 + ..\MDK-ARM\CyaSSL\config-BARE-METAL.h + + + startup_LPC43xx.s + 2 + ..\LPC43xx\startup_LPC43xx.s + + + + + CyaSSL-MDK + + + cyassl_MDK_ARM.c + 1 + ..\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + + + Retarget.c + 1 + ..\MDK-ARM\CyaSSL\Retarget.c + + + time-LCP43xx.c + 1 + ..\LPC43xx\time-LCP43xx.c + + + + + + + MDK-FS + 0x4 + ARM-ADS + + + LPC4357 + NXP (founded by Philips) + IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code") + UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000) + 6414 + LPC43xx.H + + + + + + + + + + SFD\NXP\LPC43xx\LPC43xx.SFR + 0 + + + + NXP\LPC43xx\ + NXP\LPC43xx\ + + 0 + 0 + 0 + 0 + 1 + + .\Obj\ + SD_File + 1 + 0 + 0 + 1 + 1 + .\Lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + $K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000) + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 9 + + + + + + + + + + + + + ..\MDK-ARM\config\Dbg_Flash.ini + BIN\ULP2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + BIN\ULP2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 8 + 0 + 0 + 0 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+ 1 + ..\LPC43xx\Drivers\source\lpc43xx_timer.c + + + lpc43xx_cgu.c + 1 + ..\LPC43xx\Drivers\source\lpc43xx_cgu.c + + + lpc43xx_scu.c + 1 + ..\LPC43xx\Drivers\source\lpc43xx_scu.c + + + + + MDK-ARM + + + FS_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\FS_CM3.lib + + + RTX_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\\RTX_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + TCPD_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\TCPD_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + TCP_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\TCP_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + Serial.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\Serial.c + + + ETH_LPC43xx.c + 1 + C:\Keil\ARM\RL\TCPnet\Drivers\ETH_LPC43xx.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + SDIO_LPC43xx.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\SDIO_LPC43xx.c + + + system_LPC43xx.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\system_LPC43xx.c + + + + + CyaSSL Library + + + crl.c + 1 + ..\..\..\src\crl.c + + + internal.c + 1 + ..\..\..\src\internal.c + + + io.c + 1 + ..\..\..\src\io.c + + + keys.c + 1 + ..\..\..\src\keys.c + + + ocsp.c + 1 + ..\..\..\src\ocsp.c + + + sniffer.c + 1 + ..\..\..\src\sniffer.c + + + ssl.c + 1 + ..\..\..\src\ssl.c + + + tls.c + 1 + ..\..\..\src\tls.c + + + ssl-dummy.c + 1 + ..\MDK-ARM\CyaSSL\ssl-dummy.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Crypt/Cipher Library + + + aes.c + 1 + ..\..\..\ctaocrypt\src\aes.c + + + arc4.c + 1 + ..\..\..\ctaocrypt\src\arc4.c + + + asm.c + 1 + ..\..\..\ctaocrypt\src\asm.c + + + asn.c + 1 + ..\..\..\ctaocrypt\src\asn.c + + + camellia.c + 1 + ..\..\..\ctaocrypt\src\camellia.c + + + coding.c + 1 + ..\..\..\ctaocrypt\src\coding.c + + + des3.c + 1 + ..\..\..\ctaocrypt\src\des3.c + + + dh.c + 1 + ..\..\..\ctaocrypt\src\dh.c + + + dsa.c + 1 + ..\..\..\ctaocrypt\src\dsa.c + + + ecc.c + 1 + ..\..\..\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + ..\..\..\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + ..\..\..\ctaocrypt\src\error.c + + + hc128.c + 1 + ..\..\..\ctaocrypt\src\hc128.c + + + hmac.c + 1 + ..\..\..\ctaocrypt\src\hmac.c + + + integer.c + 1 + ..\..\..\ctaocrypt\src\integer.c + + + logging.c + 1 + ..\..\..\ctaocrypt\src\logging.c + + + md2.c + 1 + ..\..\..\ctaocrypt\src\md2.c + + + md4.c + 1 + ..\..\..\ctaocrypt\src\md4.c + + + md5.c + 1 + ..\..\..\ctaocrypt\src\md5.c + + + memory.c + 1 + ..\..\..\ctaocrypt\src\memory.c + + + misc.c + 1 + ..\..\..\ctaocrypt\src\misc.c + + + pwdbased.c + 1 + ..\..\..\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + ..\..\..\ctaocrypt\src\rabbit.c + + + random.c + 1 + ..\..\..\ctaocrypt\src\random.c + + + ripemd.c + 1 + ..\..\..\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + ..\..\..\ctaocrypt\src\rsa.c + + + sha.c + 1 + ..\..\..\ctaocrypt\src\sha.c + + + sha256.c + 1 + ..\..\..\ctaocrypt\src\sha256.c + + + sha512.c + 1 + ..\..\..\ctaocrypt\src\sha512.c + + + tfm.c + 1 + ..\..\..\ctaocrypt\src\tfm.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Configuration + + + File_Config.c + 1 + ..\MDK-ARM\config\File_Config.c + + + Net_Config.c + 1 + ..\MDK-ARM\config\Net_Config.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + config.h + 5 + ..\MDK-ARM\CyaSSL\config.h + + + RTX_Conf_CM.c + 1 + ..\MDK-ARM\config\RTX_Conf_CM.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + Net_Debug.c + 1 + ..\MDK-ARM\config\Net_Debug.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + config-FS.h + 5 + ..\MDK-ARM\CyaSSL\config-FS.h + + + config-RTX-TCP-FS.h + 5 + ..\MDK-ARM\CyaSSL\config-RTX-TCP-FS.h + + + config-BARE-METAL.h + 5 + ..\MDK-ARM\CyaSSL\config-BARE-METAL.h + + + startup_LPC43xx.s + 2 + ..\LPC43xx\startup_LPC43xx.s + + + + + CyaSSL-MDK + + + cyassl_MDK_ARM.c + 1 + ..\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + + + Retarget.c + 1 + ..\MDK-ARM\CyaSSL\Retarget.c + + + time-LCP43xx.c + 1 + ..\LPC43xx\time-LCP43xx.c + + + + + + + MDK-BARE-METAL + 0x4 + ARM-ADS + + + LPC4357 + NXP (founded by Philips) + IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code") + UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000) + 6414 + LPC43xx.H + + + + + + + + + + SFD\NXP\LPC43xx\LPC43xx.SFR + 0 + + + + NXP\LPC43xx\ + NXP\LPC43xx\ + + 0 + 0 + 0 + 0 + 1 + + .\Obj\ + SD_File + 1 + 0 + 0 + 1 + 1 + .\Lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + $K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000) + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 9 + + + + + + + + + + + + + ..\MDK-ARM\config\Dbg_Flash.ini + BIN\ULP2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + BIN\ULP2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 8 + 0 + 0 + 0 + 3 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 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+ + + FS_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\FS_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + RTX_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\\RTX_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + TCPD_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\TCPD_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + TCP_CM3.lib + 4 + c:\Keil\ARM\RV31\LIB\TCP_CM3.lib + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + + + Serial.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\Serial.c + + + ETH_LPC43xx.c + 1 + C:\Keil\ARM\RL\TCPnet\Drivers\ETH_LPC43xx.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + SDIO_LPC43xx.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\SDIO_LPC43xx.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + system_LPC43xx.c + 1 + C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\system_LPC43xx.c + + + + + CyaSSL Library + + + crl.c + 1 + ..\..\..\src\crl.c + + + internal.c + 1 + ..\..\..\src\internal.c + + + io.c + 1 + ..\..\..\src\io.c + + + keys.c + 1 + ..\..\..\src\keys.c + + + ocsp.c + 1 + ..\..\..\src\ocsp.c + + + sniffer.c + 1 + ..\..\..\src\sniffer.c + + + ssl.c + 1 + ..\..\..\src\ssl.c + + + tls.c + 1 + ..\..\..\src\tls.c + + + ssl-dummy.c + 1 + ..\MDK-ARM\CyaSSL\ssl-dummy.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Crypt/Cipher Library + + + aes.c + 1 + ..\..\..\ctaocrypt\src\aes.c + + + arc4.c + 1 + ..\..\..\ctaocrypt\src\arc4.c + + + asm.c + 1 + ..\..\..\ctaocrypt\src\asm.c + + + asn.c + 1 + ..\..\..\ctaocrypt\src\asn.c + + + camellia.c + 1 + ..\..\..\ctaocrypt\src\camellia.c + + + coding.c + 1 + ..\..\..\ctaocrypt\src\coding.c + + + des3.c + 1 + ..\..\..\ctaocrypt\src\des3.c + + + dh.c + 1 + ..\..\..\ctaocrypt\src\dh.c + + + dsa.c + 1 + ..\..\..\ctaocrypt\src\dsa.c + + + ecc.c + 1 + ..\..\..\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + ..\..\..\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + ..\..\..\ctaocrypt\src\error.c + + + hc128.c + 1 + ..\..\..\ctaocrypt\src\hc128.c + + + hmac.c + 1 + ..\..\..\ctaocrypt\src\hmac.c + + + integer.c + 1 + ..\..\..\ctaocrypt\src\integer.c + + + logging.c + 1 + ..\..\..\ctaocrypt\src\logging.c + + + md2.c + 1 + ..\..\..\ctaocrypt\src\md2.c + + + md4.c + 1 + ..\..\..\ctaocrypt\src\md4.c + + + md5.c + 1 + ..\..\..\ctaocrypt\src\md5.c + + + memory.c + 1 + ..\..\..\ctaocrypt\src\memory.c + + + misc.c + 1 + ..\..\..\ctaocrypt\src\misc.c + + + pwdbased.c + 1 + ..\..\..\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + ..\..\..\ctaocrypt\src\rabbit.c + + + random.c + 1 + ..\..\..\ctaocrypt\src\random.c + + + ripemd.c + 1 + ..\..\..\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + ..\..\..\ctaocrypt\src\rsa.c + + + sha.c + 1 + ..\..\..\ctaocrypt\src\sha.c + + + sha256.c + 1 + ..\..\..\ctaocrypt\src\sha256.c + + + sha512.c + 1 + ..\..\..\ctaocrypt\src\sha512.c + + + tfm.c + 1 + ..\..\..\ctaocrypt\src\tfm.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Configuration + + + File_Config.c + 1 + ..\MDK-ARM\config\File_Config.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + Net_Config.c + 1 + ..\MDK-ARM\config\Net_Config.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + config.h + 5 + ..\MDK-ARM\CyaSSL\config.h + + + RTX_Conf_CM.c + 1 + ..\MDK-ARM\config\RTX_Conf_CM.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + Net_Debug.c + 1 + ..\MDK-ARM\config\Net_Debug.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + config-FS.h + 5 + ..\MDK-ARM\CyaSSL\config-FS.h + + + config-RTX-TCP-FS.h + 5 + ..\MDK-ARM\CyaSSL\config-RTX-TCP-FS.h + + + config-BARE-METAL.h + 5 + ..\MDK-ARM\CyaSSL\config-BARE-METAL.h + + + startup_LPC43xx.s + 2 + ..\LPC43xx\startup_LPC43xx.s + + + + + CyaSSL-MDK + + + cyassl_MDK_ARM.c + 1 + ..\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + + + Retarget.c + 1 + ..\MDK-ARM\CyaSSL\Retarget.c + + + time-LCP43xx.c + 1 + ..\LPC43xx\time-LCP43xx.c + + + + + + + + diff --git a/ctaocrypt/src/random.c b/ctaocrypt/src/random.c index f76abf002..3518ab98c 100644 --- a/ctaocrypt/src/random.c +++ b/ctaocrypt/src/random.c @@ -23,8 +23,6 @@ #include #endif -#include - /* on HPUX 11 you may need to install /dev/random see http://h20293.www2.hp.com/portal/swdepot/displayProductInfo.do?productNumber=KRNG11I @@ -39,6 +37,7 @@ #ifdef NO_INLINE #include #else + #define MISC_DUMM_FUNC misc_dummy_random #include #endif #endif @@ -60,7 +59,6 @@ #endif #endif /* USE_WINDOWS_API */ -#if !defined( NO_CYASSL_RANDOM ) #ifdef NO_RC4 @@ -569,16 +567,20 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz) return 0; } - +#elif defined(CYASSL_LPC43xx) + #warning "write a real random seed!!!!, just for testing now" + int GenerateSeed(OS_Seed* os, byte* output, word32 sz) + { + int i; + for (i = 0; i < sz; i++ ) + output[i] = i; + return 0; + } + #elif defined(NO_DEV_RANDOM) #error "you need to write an os specific GenerateSeed() here" -/* -int GenerateSeed(OS_Seed* os, byte* output, word32 sz) -{ - return 0; -} -*/ +int GenerateSeed(OS_Seed* os, byte* output, word32 sz) { return(0) ; } #else /* !USE_WINDOWS_API && !THREADX && !MICRIUM && !NO_DEV_RANDOM */ @@ -622,4 +624,3 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz) #endif /* USE_WINDOWS_API */ -#endif /* NO_CYASSL_RANDOM */