mirror of https://github.com/wolfSSL/wolfBoot.git
Add TPM test (`RX: 0x1141105`).
David Garske
parent
0f110e4cd9
commit
23061c041c
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@ -32,10 +32,8 @@
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#define ENABLE_PCIE
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#define ENABLE_CPLD /* Board Configuration and Status Registers (BCSR) */
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#define ENABLE_CONF_IO
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#endif
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#ifdef WOLFBOOT_TPM
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#define ENABLE_ESPI
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#define ENABLE_ESPI /* TPM */
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#endif
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/* TODO */
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@ -45,13 +43,17 @@
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/* Tests */
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/* #define TEST_DDR */
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/* #define TEST_FLASH */
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/* #define TEST_TPM */
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#ifdef TEST_DDR
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#if defined(ENABLE_DDR) && defined(TEST_DDR)
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static int test_ddr(void);
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#endif
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#ifdef TEST_FLASH
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#if defined(ENABLE_ELBC) && defined(TEST_FLASH)
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static int test_flash(void);
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#endif
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#if defined(ENABLE_ESPI) && defined(TEST_TPM)
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static int test_tpm(void);
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#endif
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/* P1021 Platform */
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@ -406,6 +408,7 @@ enum elbc_amask_sizes {
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#define ESPI_SPCOM_RXSKIP(x) ((x) << 16) /* Number of characters skipped for reception from frame start */
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#define ESPI_SPCOM_TRANLEN(x) (((x) - 1) << 0) /* Transaction length */
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#define ESPI_SPIE_DON (1 << 14) /* Last character was transmitted */
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#define ESPI_SPIE_RNE (1 << 9) /* recevie not empty */
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#define ESPI_SPIE_TNF (1 << 8) /* transmit not full */
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@ -420,6 +423,18 @@ enum elbc_amask_sizes {
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#define ESPI_CSMODE_CSAFT(x) (((x) & 0xF) << 8) /* CS assertion time in bits after frame end */
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#define ESPI_CSMODE_CSCG(x) (((x) & 0xF) << 3) /* Clock gaps between transmitted frames according to this size */
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#if defined(ENABLE_ESPI) || defined(ENABLE_DDR)
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static void udelay(uint32_t delay_us)
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{
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uint32_t i;
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static const uint32_t oneus = (SYS_CLK / 1000000);
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delay_us *= oneus;
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for (i=0; i<delay_us; i++) {
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asm volatile("nop");
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}
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}
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#endif
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#ifdef ENABLE_ESPI
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void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode)
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{
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@ -445,6 +460,7 @@ void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode)
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}
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if (pm > 0)
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pm--;
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csmode |= ESPI_CSMODE_PM(pm);
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if (mode & 1)
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@ -455,6 +471,8 @@ void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode)
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/* configure CS */
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set32(ESPI_SPCSMODE(cs), csmode);
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}
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/* Note: This code assumes all input buffers are multiple of 4 */
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int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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{
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uint32_t reg, blks;
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@ -472,12 +490,16 @@ int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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reg = *((uint32_t*)tx);
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set32(ESPI_SPITF, reg);
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tx += 4;
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set32(ESPI_SPIE, ESPI_SPIE_TNF); /* clear event */
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udelay(5);
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/* wait till RX has data */
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while ((get32(ESPI_SPIE) & ESPI_SPIE_RNE) == 0);
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reg = get32(ESPI_SPIRF);
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*((uint32_t*)rx) = reg;
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rx += 4;
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set32(ESPI_SPIE, ESPI_SPIE_RNE); /* clear event */
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}
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/* toggle ESPI_SPMODE_EN - to deassert CS */
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@ -576,8 +598,6 @@ static void hal_flash_set_addr(int col, int page)
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/* calculate buffer for FCM - there are 8 1KB pages */
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flash_buf = (uint8_t*)(FLASH_BASE_ADDR + (buf_num * 1024));
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flash_idx = col;
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wolfBoot_printf("set addr %p, idx %d\r\n", flash_buf, flash_idx);
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}
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/* iswrite (read=0, write=1) */
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@ -752,7 +772,6 @@ static int hal_flash_init(void)
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void hal_ddr_init(void)
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{
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#ifdef ENABLE_DDR
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int i;
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uint32_t reg;
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/* Map LAW for DDR */
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@ -799,9 +818,7 @@ void hal_ddr_init(void)
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asm volatile("sync;isync");
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/* busy wait for ~500us */
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for (i=0; i<5000000; i++) {
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asm volatile("nop");
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}
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udelay(500);
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/* Enable controller */
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reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI;
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@ -811,9 +828,7 @@ void hal_ddr_init(void)
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/* Wait for data initialization to complete */
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while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) {
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/* busy wait loop - throttle polling */
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for (i=0; i<50000; i++) {
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asm volatile("nop");
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}
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udelay(1);
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}
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}
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@ -1066,17 +1081,23 @@ void hal_init(void)
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#endif
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hal_flash_init();
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#ifdef TEST_DDR
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#if defined(ENABLE_DDR) && defined(TEST_DDR)
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if (test_ddr() != 0) {
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wolfBoot_printf("DDR Test Failed!\r\n");
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}
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#endif
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#ifdef TEST_FLASH
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#if defined(ENABLE_ELBC) && defined(TEST_FLASH)
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if (test_flash() != 0) {
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wolfBoot_printf("Flash Test Failed!\r\n");
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}
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#endif
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#if defined(ENABLE_ESPI) && defined(TEST_TPM)
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if (test_tpm() != 0) {
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wolfBoot_printf("TPM Test Failed!\r\n");
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}
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#endif
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}
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int hal_flash_write(uint32_t address, const uint8_t *data, int len)
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@ -1378,11 +1399,11 @@ static int test_ddr(void)
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#endif
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/* #define TEST_FLASH_READONLY */
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static uint32_t pageData[FLASH_PAGE_SIZE/4]; /* force 32-bit alignment */
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static int test_flash(void)
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{
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int ret;
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uint32_t i;
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uint32_t pageData[FLASH_PAGE_SIZE/4]; /* force 32-bit alignment */
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#ifndef TEST_FLASH_READONLY
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/* Erase sector */
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@ -1416,3 +1437,22 @@ static int test_flash(void)
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return ret;
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}
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#endif /* ENABLE_ELBC && TEST_FLASH */
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#if defined(ENABLE_ESPI) && defined(TEST_TPM)
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#ifndef SPI_CS_TPM
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#define SPI_CS_TPM 2
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#endif
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int test_tpm(void)
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{
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/* Read 4 bytes at TIS addresss D40F00. Assumes 0 wait state on TPM */
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uint8_t tx[8] = {0x83, 0xD4, 0x0F, 0x00,
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0x00, 0x00, 0x00, 0x00};
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uint8_t rx[8] = {0};
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hal_espi_init(SPI_CS_TPM, 2000000, 0);
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hal_espi_xfer(SPI_CS_TPM, tx, rx, (uint32_t)sizeof(rx));
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wolfBoot_printf("RX: 0x%x\r\n", *((uint32_t*)&rx[4]));
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return rx[4] != 0xFF ? 0 : -1;
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}
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#endif
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@ -12,7 +12,10 @@ MEMORY
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LENGTH = 0x1FFFFFFF - @WOLFBOOT_STAGE1_LOAD_ADDR@
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/* L1 as SRAM (up to 16KB) */
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RAM (rwx) : ORIGIN = 0xFFD00000, LENGTH = 16K
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L1RAM (rwx) : ORIGIN = 0xFFD00000, LENGTH = 16K
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/* L2 as SRAM (up to 256KB) */
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L2RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 256K
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}
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SECTIONS
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@ -78,5 +81,9 @@ SECTIONS
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}
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PROVIDE(_start_heap = _end);
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PROVIDE(_end_stack = _end + HEAP_SIZE + STACK_SIZE );
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/* If relocated to DDR already then use stack end from DDR */
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/* If debugging and DDR is not ready, use L1 or L2 */
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PROVIDE(_end_stack = _end + HEAP_SIZE + STACK_SIZE );
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/* PROVIDE(_end_stack = ORIGIN(L1RAM) + (LENGTH(L1RAM)) ); */
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/* PROVIDE(_end_stack = ORIGIN(L2RAM) + (LENGTH(L2RAM)) ); */
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@ -2,6 +2,7 @@ OUTPUT_ARCH( "powerpc" )
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ENTRY( _reset )
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/* Adjust base address to 0xF8F80000 is debugging (run from L2 cache) */
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BASE_ADDR = @WOLFBOOT_STAGE1_BASE_ADDR@;
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/* for flashing to NAND it must be 4KB */
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