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Fixes for QSPI driver (CS is controller by QSPI). Fix little endian byte ordering for UART printf feature.

pull/264/head
David Garske 2022-12-20 15:00:26 -08:00
parent bf62ebe3fd
commit 26bed3e893
4 changed files with 33 additions and 30 deletions
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47
hal/spi/spi_drv_stm32.c
View File

@ -134,33 +134,33 @@ static void RAMFUNCTION stm_pins_setup(void)
#ifdef SPI_FLASH
#ifdef PLATFORM_stm32l0
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, GPIO_MODE_AF,
SPI_CLOCK_PIN_AF, 2, 3);
SPI_CLOCK_PIN_AF, 2, 3);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, GPIO_MODE_AF,
SPI_MOSI_PIN_AF, 2, 3);
SPI_MOSI_PIN_AF, 2, 3);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, GPIO_MODE_AF,
SPI_MISO_PIN_AF, 2, 3);
SPI_MISO_PIN_AF, 2, 3);
#else
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, GPIO_MODE_AF,
SPI_CLOCK_PIN_AF, 0, 3);
SPI_CLOCK_PIN_AF, 0, 3);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, GPIO_MODE_AF,
SPI_MOSI_PIN_AF, 0, 0);
SPI_MOSI_PIN_AF, 0, 0);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, GPIO_MODE_AF,
SPI_MISO_PIN_AF, 1, 0);
SPI_MISO_PIN_AF, 1, 0);
#endif
#endif
#ifdef QSPI_FLASH
stm_gpio_config(QSPI_CS_PIO_BASE, QSPI_CS_FLASH_PIN, GPIO_MODE_OUTPUT,
0, 1, 3);
stm_gpio_config(QSPI_CS_PIO_BASE, QSPI_CS_FLASH_PIN, GPIO_MODE_AF,
QSPI_CS_FLASH_AF, 1, 3);
stm_gpio_config(QSPI_CLOCK_PIO_BASE, QSPI_CLOCK_PIN, GPIO_MODE_AF,
QSPI_CLOCK_PIN_AF, 0, 3);
QSPI_CLOCK_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO0_PIO_BASE, QSPI_IO0_PIN, GPIO_MODE_AF,
QSPI_IO0_PIN_AF, 0, 3);
QSPI_IO0_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO1_PIO_BASE, QSPI_IO1_PIN, GPIO_MODE_AF,
QSPI_IO1_PIN_AF, 0, 3);
QSPI_IO1_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO2_PIO_BASE, QSPI_IO2_PIN, GPIO_MODE_AF,
QSPI_IO2_PIN_AF, 0, 3);
QSPI_IO2_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO3_PIO_BASE, QSPI_IO3_PIN, GPIO_MODE_AF,
QSPI_IO3_PIN_AF, 0, 3);
QSPI_IO3_PIN_AF, 0, 3);
#endif
}
@ -320,11 +320,13 @@ void RAMFUNCTION spi_init(int polarity, int phase)
/* Configure chip selects */
#ifdef SPI_FLASH
stm_gpio_config(SPI_CS_PIO_BASE, SPI_CS_FLASH, GPIO_MODE_OUTPUT, 0, 1, 3);
stm_gpio_config(SPI_CS_PIO_BASE, SPI_CS_FLASH, GPIO_MODE_OUTPUT,
0, 1, 3);
spi_cs_off(SPI_CS_PIO_BASE, SPI_CS_FLASH);
#endif
#ifdef WOLFBOOT_TPM
stm_gpio_config(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM, GPIO_MODE_OUTPUT, 0, 1, 3);
stm_gpio_config(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM, GPIO_MODE_OUTPUT,
0, 1, 3);
spi_cs_off(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM);
#endif
@ -336,13 +338,18 @@ void RAMFUNCTION spi_init(int polarity, int phase)
/* Wait till BUSY flag cleared */
while (QUADSPI_SR & QUADSPI_SR_BUSY) {};
/* Configure QSPI Clock Prescaler (240/X), Flash ID 0, Dual Flash=0, Sample Shift=None */
QUADSPI_CR &= ~(QUADSPI_CR_PRESCALER_MASK | QUADSPI_CR_FSEL | QUADSPI_CR_DFM | QUADSPI_CR_SSHIFT);
/* Configure QSPI Clock Prescaler (240/X), Flash ID 0, Dual Flash=0,
* Sample Shift=None */
QUADSPI_CR &= ~(QUADSPI_CR_PRESCALER_MASK | QUADSPI_CR_FSEL |
QUADSPI_CR_DFM | QUADSPI_CR_SSHIFT);
QUADSPI_CR |= (QUADSPI_CR_PRESCALER(HCLK3_MHZ/QSPI_CLOCK_MHZ));
/* Configure QSPI Flash Size (16MB), CS High Time (1 clock) and Clock Mode (0) */
QUADSPI_DCR &= ~(QUADSPI_DCR_FSIZE_MASK | QUADSPI_DCR_CSHT_MASK | QUADSPI_DCR_CKMODE_3);
QUADSPI_DCR |= (QUADSPI_DCR_FSIZE(22) | QUADSPI_DCR_CSHT(0) | QUADSPI_DCR_CKMODE_0);
/* Configure QSPI Flash Size (16MB), CS High Time (1 clock) and
* Clock Mode (0) */
QUADSPI_DCR &= ~(QUADSPI_DCR_FSIZE_MASK | QUADSPI_DCR_CSHT_MASK |
QUADSPI_DCR_CKMODE_3);
QUADSPI_DCR |= (QUADSPI_DCR_FSIZE(22) | QUADSPI_DCR_CSHT(0) |
QUADSPI_DCR_CKMODE_0);
#endif /* QSPI_FLASH */
#ifdef SPI_FLASH
/* Configure SPI1 for master mode */

6
hal/spi/spi_drv_stm32.h
View File

@ -281,6 +281,10 @@
#endif
#ifdef QSPI_FLASH
#ifndef QSPI_CS_FLASH_AF
#define QSPI_CS_FLASH_AF QSPI_PIN_AF
#endif
#ifndef QSPI_CLOCK_PIN_AF
#define QSPI_CLOCK_PIN_AF QSPI_PIN_AF
#endif
@ -358,7 +362,7 @@
#define QUADSPI_CCR (*(volatile uint32_t *)(QUADSPI_BASE + 0x14)) /* Communication Configuration register */
#define QUADSPI_AR (*(volatile uint32_t *)(QUADSPI_BASE + 0x18)) /* Address register */
#define QUADSPI_ABR (*(volatile uint32_t *)(QUADSPI_BASE + 0x1C)) /* Alternate Bytes register */
#define QUADSPI_DR (*(volatile uint8_t *)(QUADSPI_BASE + 0x23)) /* Data register */
#define QUADSPI_DR (*(volatile uint8_t *)(QUADSPI_BASE + 0x20)) /* Data register */
#define QUADSPI_PSMKR (*(volatile uint32_t *)(QUADSPI_BASE + 0x24)) /* Polling Status Mask register */
#define QUADSPI_PSMAR (*(volatile uint32_t *)(QUADSPI_BASE + 0x28)) /* Polling Status Match register */
#define QUADSPI_PIR (*(volatile uint32_t *)(QUADSPI_BASE + 0x2C)) /* Polling Interval register */

2
src/qspi_flash.c
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@ -136,7 +136,7 @@ static int qspi_flash_read_id(uint8_t* id, uint32_t idSz)
qspi_status((uint8_t*)&status);
#ifdef DEBUG_QSPI
wolfBoot_printf("Flash: Ret %d: ID: %x, Cmd %x, status %x\n",
ret, (uint32_t)data, FLASH_READ_CMD, status);
ret, *((uint32_t*)data), READ_ID_CMD, status);
#endif
/* optionally return id data */

8
src/string.c
View File

@ -261,26 +261,18 @@ void uart_writenum(int num, int base)
char buf[sizeof(int)*2+1];
const char* kDigitLut = "0123456789ABCDEF";
unsigned int val = (unsigned int)num;
#ifdef BIG_ENDIAN_ORDER
int sz = 0;
#endif
if (base == 10 && num < 0) { /* handle negative */
buf[i++] = '-';
val = -num;
}
do {
#ifdef BIG_ENDIAN_ORDER
buf[sizeof(buf)-sz-1] = kDigitLut[(val % base)];
sz++;
#else
buf[i++] = kDigitLut[(val % base)];
#endif
val /= base;
} while (val > 0U);
#ifdef BIG_ENDIAN_ORDER
memmove(&buf[i], &buf[sizeof(buf)-sz], sz);
i+=sz;
#endif
uart_write(buf, i);
}