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wolfBoot
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Code Issues Releases Wiki Activity

Don't update clock settings before staging. 

(mentioned in docs/Targets.md)
pull/44/head
Daniele Lacamera 2020-05-20 12:19:16 +02:00 committed by David Garske
parent 56d16f323c
commit 28e29cb20b
2 changed files with 5 additions and 1 deletions
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5
docs/Targets.md
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@ -573,6 +573,11 @@ wolfBoot uses the following components to access peripherals on the PSoC:
Cypress provides a [customized OpenOCD](https://github.com/cypresssemiconductorco/Openocd) for programming the flash and Cypress provides a [customized OpenOCD](https://github.com/cypresssemiconductorco/Openocd) for programming the flash and
debugging. debugging.
### Clock settings
wolfBoot configures PLL1 to run at 100 MHz and is driving `CLK_FAST`, `CLK_PERI`, and `CLK_SLOW` at that frequency.
#### Build configuration #### Build configuration
The following configuration has been tested on the PSoC CY8CKIT-62S2-43012: The following configuration has been tested on the PSoC CY8CKIT-62S2-43012:

1
hal/psoc6.c
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@ -98,7 +98,6 @@ void hal_init(void)
void hal_prepare_boot(void) void hal_prepare_boot(void)
{ {
/* TODO: how to restore boot-default clock speed? */
} }
#endif #endif