mirror of https://github.com/wolfSSL/wolfBoot.git
Fixed STM32L5 TRNG driver + simplified GTZC and SAU setup
Daniele Lacamera
parent
426d0346ad
commit
80f881dab5
1
Makefile
1
Makefile
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@ -139,6 +139,7 @@ wolfboot.bin: wolfboot.elf
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$(Q)$(SIZE) wolfboot.elf
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@echo
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test-app/image.bin: wolfboot.elf
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$(Q)$(MAKE) -C test-app WOLFBOOT_ROOT="$(WOLFBOOT_ROOT)"
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$(Q)$(SIZE) test-app/image.elf
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158
hal/stm32l5.c
158
hal/stm32l5.c
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@ -22,7 +22,6 @@
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#include <stdint.h>
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#include <image.h>
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#include <string.h>
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#include "stm32l5_partition.h"
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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@ -116,6 +115,9 @@
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98))
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#define RCC_CRRCR_HSI48ON (1 << 0)
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#define RCC_CRRCR_HSI48RDY (1 << 1)
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/*** PWR ***/
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/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
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@ -241,12 +243,8 @@
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#define TRNG_AHB2_CLOCK_ER (1 << 18)
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#define SCS_BASE (0xE000E000UL)
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#define SCB_BASE (SCS_BASE + 0x0D00UL)
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#define SCB_SHCSR (*(volatile uint32_t *)(SCB_BASE + 0x24))
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#define SCB_SHCSR (*(volatile uint32_t *)(0xE000ED24))
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#define SCB_SHCSR_SECUREFAULT_EN (1<<19)
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#endif
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static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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@ -393,9 +391,6 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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flash_wait_complete(0);
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@ -409,8 +404,6 @@ void RAMFUNCTION hal_flash_unlock(void)
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}
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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flash_wait_complete(0);
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@ -600,44 +593,90 @@ static void clock_pll_on(int powersave)
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DMB();
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}
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static void hsi48_on(void)
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{
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RCC_CRRCR |= RCC_CRRCR_HSI48ON;
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while(RCC_CRRCR & RCC_CRRCR_HSI48RDY)
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;
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}
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/* SAU registers, used to define memory mapped regions */
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#define SAU_CTRL (*(volatile uint32_t *)(0xE000EDD0))
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#define SAU_RNR (*(volatile uint32_t *)(0xE000EDD8)) /** SAU_RNR - region number register **/
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#define SAU_RBAR (*(volatile uint32_t *)(0xE000EDDC)) /** SAU_RBAR - region base address register **/
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#define SAU_RLAR (*(volatile uint32_t *)(0xE000EDE0)) /** SAU_RLAR - region limit address register **/
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#define SAU_REGION_MASK 0x000000FF
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#define SAU_ADDR_MASK 0xFFFFFFE0 /* LS 5 bit are reserved or used for flags */
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/* Flag for the SAU region limit register */
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#define SAU_REG_ENABLE (1 << 0) /* Indicates that the region is enabled. */
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#define SAU_REG_SECURE (1 << 1) /* When on, the region is S or NSC */
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#define SAU_INIT_CTRL_ENABLE (1 << 0)
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#define SAU_INIT_CTRL_ALLNS (1 << 1)
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static void sau_init_region(uint32_t region, uint32_t start_addr,
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uint32_t end_addr, int secure)
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{
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uint32_t secure_flag = 0;
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if (secure)
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secure_flag = SAU_REG_SECURE;
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SAU_RNR = region & SAU_REGION_MASK;
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SAU_RBAR = start_addr & SAU_ADDR_MASK;
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SAU_RLAR = (end_addr & SAU_ADDR_MASK)
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| secure_flag | SAU_REG_ENABLE;
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}
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static void tz_sau_init(void)
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{
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/* Non-secure callable: NSC functions area */
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sau_init_region(0, 0x0C020000, 0x0C040000, 1);
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/* Non-secure: application flash area */
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sau_init_region(1, 0x08040000, 0x0804FFFF, 0);
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/* Non-secure RAM region in SRAM1 */
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sau_init_region(2, 0x20018000, 0x2002FFFF, 0);
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/* Non-secure: internal peripherals */
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sau_init_region(3, 0x40000000, 0x4FFFFFFF, 0);
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/* Enable SAU */
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SAU_CTRL = SAU_INIT_CTRL_ENABLE;
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/* Enable securefault handler */
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SCB_SHCSR |= SCB_SHCSR_SECUREFAULT_EN;
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}
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#define GTZC_MPCBB1_S_BASE (0x50032C00)
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#define GTZC_MPCBB1_S_VCTR_BASE (GTZC_MPCBB1_S_BASE + 0x100)
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#define GTZC_MPCBB2_S_BASE (0x50033000)
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#define GTZC_MPCBB2_S_VCTR_BASE (GTZC_MPCBB2_S_BASE + 0x100)
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#define SET_GTZC_MPCBBx_S_VCTR(bank,n,val) \
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(*((volatile uint32_t *)(GTZC_MPCBB##bank##_S_VCTR_BASE ) + n ))= val
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static void gtzc_init(void)
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{
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/*configure SRAM1 */
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SET_GTZC_MPCBBx_S_VCTR(1,0);
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SET_GTZC_MPCBBx_S_VCTR(1,1);
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SET_GTZC_MPCBBx_S_VCTR(1,2);
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SET_GTZC_MPCBBx_S_VCTR(1,3);
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SET_GTZC_MPCBBx_S_VCTR(1,4);
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SET_GTZC_MPCBBx_S_VCTR(1,5);
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SET_GTZC_MPCBBx_S_VCTR(1,6);
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SET_GTZC_MPCBBx_S_VCTR(1,7);
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SET_GTZC_MPCBBx_S_VCTR(1,8);
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SET_GTZC_MPCBBx_S_VCTR(1,9);
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SET_GTZC_MPCBBx_S_VCTR(1,10);
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SET_GTZC_MPCBBx_S_VCTR(1,11);
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SET_GTZC_MPCBBx_S_VCTR(1,12);
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SET_GTZC_MPCBBx_S_VCTR(1,13);
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SET_GTZC_MPCBBx_S_VCTR(1,14);
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SET_GTZC_MPCBBx_S_VCTR(1,15);
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SET_GTZC_MPCBBx_S_VCTR(1,16);
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SET_GTZC_MPCBBx_S_VCTR(1,17);
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SET_GTZC_MPCBBx_S_VCTR(1,18);
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SET_GTZC_MPCBBx_S_VCTR(1,19);
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SET_GTZC_MPCBBx_S_VCTR(1,20);
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SET_GTZC_MPCBBx_S_VCTR(1,21);
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SET_GTZC_MPCBBx_S_VCTR(1,22);
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SET_GTZC_MPCBBx_S_VCTR(1,23);
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/*configure SRAM2 */
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SET_GTZC_MPCBBx_S_VCTR(2,0);
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SET_GTZC_MPCBBx_S_VCTR(2,1);
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SET_GTZC_MPCBBx_S_VCTR(2,2);
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SET_GTZC_MPCBBx_S_VCTR(2,3);
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SET_GTZC_MPCBBx_S_VCTR(2,4);
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SET_GTZC_MPCBBx_S_VCTR(2,5);
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SET_GTZC_MPCBBx_S_VCTR(2,6);
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SET_GTZC_MPCBBx_S_VCTR(2,7);
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int i;
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/* Configure lower half of SRAM1 as secure */
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for (i = 0; i < 12; i++) {
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SET_GTZC_MPCBBx_S_VCTR(1, i, 0xFFFFFFFF);
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}
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/* Configure upper half of SRAM1 as non-secure */
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for (i = 12; i < 24; i++) {
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SET_GTZC_MPCBBx_S_VCTR(1, i, 0x0);
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}
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/* Configure SRAM2 as secure */
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for (i = 0; i < 8; i++) {
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SET_GTZC_MPCBBx_S_VCTR(2, i, 0xFFFFFFFF);
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}
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}
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@ -707,18 +746,19 @@ static void RAMFUNCTION fork_bootloader(void)
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void hal_init(void)
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{
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TZ_SAU_Setup();
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#if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
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if ((FLASH_OPTR & (FLASH_OPTR_SWAP_BANK | FLASH_OPTR_DBANK)) == FLASH_OPTR_DBANK)
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fork_bootloader();
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#endif
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clock_pll_on(0);
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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/* Enable SecureFault handler (HardFault is default) */
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SCB_SHCSR |= SCB_SHCSR_SECUREFAULT_EN;
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tz_sau_init();
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gtzc_init();
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#endif
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clock_pll_on(0);
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}
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@ -739,11 +779,31 @@ void hal_prepare_boot(void)
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#define TRNG_SR_DRDY (1 << 0)
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#define TRNG_CR_RNGEN (1 << 2)
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#define TRNG_CR_CONFIG3_SHIFT (8)
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#define TRNG_CR_CONFIG2_SHIFT (13)
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#define TRNG_CR_CLKDIV_SHIFT (16)
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#define TRNG_CR_CONFIG1_SHIFT (20)
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#define TRNG_CR_CONDRST (1 << 30)
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void hal_trng_init(void)
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{
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uint32_t reg_val;
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hsi48_on();
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RCC_AHB2_CLOCK_ER |= TRNG_AHB2_CLOCK_ER;
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TRNG_CR |= TRNG_CR_RNGEN;
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reg_val = TRNG_CR;
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reg_val &= ~(0x1F << TRNG_CR_CONFIG1_SHIFT);
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reg_val &= ~(0x7 << TRNG_CR_CLKDIV_SHIFT);
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reg_val &= ~(0x3 << TRNG_CR_CONFIG2_SHIFT);
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reg_val &= ~(0x7 << TRNG_CR_CONFIG3_SHIFT);
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reg_val |= 0x0F << TRNG_CR_CONFIG1_SHIFT;
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reg_val |= 0x0D << TRNG_CR_CONFIG3_SHIFT;
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TRNG_CR = TRNG_CR_CONDRST | reg_val;
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while ((TRNG_CR & TRNG_CR_CONDRST) == 0)
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;
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TRNG_CR = reg_val | TRNG_CR_RNGEN;
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while ((TRNG_SR & TRNG_SR_DRDY) == 0)
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;
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}
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@ -21,8 +21,6 @@
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#include <stdint.h>
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#include <image.h>
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#include "stm32l5_partition.h"
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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#define ISB() __asm__ volatile ("isb")
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@ -1,443 +0,0 @@
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/* stm32l5_partition.h
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*
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* Copyright (C) 2021 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef STM32L5_PARTITION_H
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#define STM32L5_PARTITION_H
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#define SCS_BASE (0xE000E000UL)
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#define SCB_BASE (SCS_BASE + 0x0D00UL)
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#define SAU_BASE (SCS_BASE + 0x0DD0UL)
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#define FPU_BASE (SCS_BASE + 0x0F30UL)
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#define NVIC_BASE (SCS_BASE + 0x0100UL)
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#define SAU_CTRL (*(volatile uint32_t *)(SAU_BASE + 0x00))
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#define SAU_RNR (*(volatile uint32_t *)(SAU_BASE + 0x08))
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#define SAU_RBAR (*(volatile uint32_t *)(SAU_BASE + 0x0C))
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#define SAU_RLAR (*(volatile uint32_t *)(SAU_BASE + 0x10))
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#define SCB_NSACR (*(volatile uint32_t *)(SCB_BASE + 0x8C))
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#define FPU_FPCCR (*(volatile uint32_t *)(FPU_BASE + 0x04))
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/* SAU Control Register Definitions */
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#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
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#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
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#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
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#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
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/* SAU Type Register Definitions */
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#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
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#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
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/* SAU Region Number Register Definitions */
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#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
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#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
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/* SAU Region Base Address Register Definitions */
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#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
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#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
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/* SAU Region Limit Address Register Definitions */
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#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
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#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
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#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
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#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
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#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
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#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
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/* SCB Non-Secure Access Control Register Definitions */
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#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
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#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
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#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
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#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
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#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
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#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
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#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
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#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
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#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
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#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
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#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
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#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
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/*
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// <q> Enable SAU
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// <i> Value for SAU_CTRL register bit ENABLE
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*/
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#define SAU_INIT_CTRL_ENABLE 1
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/*
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// <o> When SAU is disabled
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// <0=> All Memory is Secure
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// <1=> All Memory is Non-Secure
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// <i> Value for SAU_CTRL register bit ALLNS
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// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
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*/
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#define SAU_INIT_CTRL_ALLNS 0
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/*
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// <h>Initialize Security Attribution Unit (SAU) Address Regions
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// <i>SAU configuration specifies regions to be one of:
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// <i> - Secure and Non-Secure Callable
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// <i> - Non-Secure
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// <i>Note: All memory regions not configured by SAU are Secure
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*/
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#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
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/*
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// <e>Initialize SAU Region 0
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// <i> Setup SAU Region 0 memory attributes
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*/
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#define SAU_INIT_REGION0 1
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC0 1
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/*
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// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x20018000 /* start address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
|
||||
// <e>Setup behaviour of Floating Point Unit
|
||||
|
||||
#define TZ_FPU_NS_USAGE 1
|
||||
|
||||
/*
|
||||
// <o>Floating Point Unit usage
|
||||
// <0=> Secure state only
|
||||
// <3=> Secure and Non-Secure state
|
||||
// <i> Value for SCB_NSACR register bits CP10, CP11
|
||||
*/
|
||||
#define SCB_NSACR_CP10_11_VAL 3
|
||||
|
||||
/*
|
||||
// <o>Treat floating-point registers as Secure
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU_FPCCR register bit TS
|
||||
*/
|
||||
#define FPU_FPCCR_TS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear on return (CLRONRET) accessibility
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for FPU_FPCCR register bit CLRONRETS
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRETS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear floating-point caller saved registers on exception return
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU_FPCCR register bit CLRONRET
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRET_VAL 1
|
||||
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU_RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU_RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU_RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
|
||||
#define GTZC_MPCBB1_S_BASE (0x50032C00)
|
||||
#define GTZC_MPCBB1_S_CR (*(volatile uint32_t *)(GTZC_MPCBB1_S_BASE + 0x00))
|
||||
#define GTZC_MPCBB1_S_LCKVTR1 (*(volatile uint32_t *)(GTZC_MPCBB1_S_BASE + 0x10))
|
||||
#define GTZC_MPCBB1_S_LCKVTR2 (*(volatile uint32_t *)(GTZC_MPCBB1_S_BASE + 0x14))
|
||||
#define GTZC_MPCBB1_S_VCTR_BASE (GTZC_MPCBB1_S_BASE + 0x100)
|
||||
|
||||
#define GTZC_MPCBB2_S_BASE (0x50033000)
|
||||
#define GTZC_MPCBB2_S_CR (*(volatile uint32_t *)(GTZC_MPCBB2_S_BASE + 0x00))
|
||||
#define GTZC_MPCBB2_S_LCKVTR1 (*(volatile uint32_t *)(GTZC_MPCBB2_S_BASE + 0x10))
|
||||
#define GTZC_MPCBB2_S_LCKVTR2 (*(volatile uint32_t *)(GTZC_MPCBB2_S_BASE + 0x14))
|
||||
#define GTZC_MPCBB2_S_VCTR_BASE (GTZC_MPCBB2_S_BASE + 0x100)
|
||||
|
||||
#define SET_GTZC_MPCBBx_S_VCTR(x,n) \
|
||||
(*((volatile uint32_t *)(GTZC_MPCBB##x##_S_VCTR_BASE ) + n ))= GTZC_MPCBB##x##_S_VCTR##n##_VAL
|
||||
|
||||
/*SRAM1*/
|
||||
#define GTZC_MPCBB1_S_VCTR0_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR1_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR2_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR3_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR4_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR5_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR6_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR7_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR8_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR9_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR10_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR11_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR12_VAL (0xFFFFFFFF)
|
||||
#define GTZC_MPCBB1_S_VCTR13_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR14_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR15_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR16_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR17_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR18_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR19_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR20_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR21_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR22_VAL (0x00000000)
|
||||
#define GTZC_MPCBB1_S_VCTR23_VAL (0x00000000)
|
||||
|
||||
/*SRAM2*/
|
||||
#define GTZC_MPCBB2_S_VCTR0_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR1_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR2_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR3_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR4_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR5_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR6_VAL (0x00000000)
|
||||
#define GTZC_MPCBB2_S_VCTR7_VAL (0x00000000)
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
static __inline void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
SAU_CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
|
||||
#if defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
|
||||
|
||||
SCB_NSACR = (SCB_NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
|
||||
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
|
||||
|
||||
FPU_FPCCR = (FPU_FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
|
||||
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
|
||||
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
|
||||
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* STM32L5_PARTITION_H */
|
||||
|
|
@ -113,6 +113,7 @@ int main(void)
|
|||
#endif
|
||||
wolfBoot_start();
|
||||
|
||||
|
||||
/* wolfBoot_start should never return. */
|
||||
wolfBoot_panic();
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include "system.h"
|
||||
#include "hal.h"
|
||||
#include "wolfboot/wolfboot.h"
|
||||
#include "wolfboot/wc_secure.h"
|
||||
|
||||
#define LED_BOOT_PIN (12) //PG12 - Discovery - Green Led
|
||||
#define LED_USR_PIN (3) //PD3 - Discovery - Red Led
|
||||
|
|
@ -54,9 +55,6 @@
|
|||
#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
|
||||
#define PWR_CR2_IOSV (1 << 9)
|
||||
|
||||
int wcs_get_random(unsigned char *rand,
|
||||
uint32_t size);
|
||||
|
||||
static void boot_led_on(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
|
@ -104,7 +102,7 @@ void main(void)
|
|||
uint32_t rand;
|
||||
uint32_t i;
|
||||
wcs_get_random((void*)&rand, 4);
|
||||
for (i = 0; i < rand; i++)
|
||||
for (i = 0; i < (rand / 100000000); i++)
|
||||
;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue