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wolfBoot
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Peer review cleanups and added CI test.

pull/381/head
David Garske 2023-10-12 14:30:24 -07:00 committed by Daniele Lacamera
parent a6fc952328
commit 8d882bc898
3 changed files with 15 additions and 24 deletions
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6
.github/workflows/test-configs.yml vendored
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@ -138,6 +138,12 @@ jobs:
# TODO: SP math with small stack has issues
stm32c0:
uses: ./.github/workflows/test-build.yml
with:
arch: arm
config-file: ./config/examples/stm32c0.config
stm32f4_small_blocks_uart_update_test:
uses: ./.github/workflows/test-build.yml
with:

31
hal/stm32c0.c
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@ -36,11 +36,10 @@
/*** RCC ***/
#define RCC_BASE (0x40021000)
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0444 - 5.4.1 */
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) /* RM0444 - 5.4.3 */
#define APB1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x3C))
#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x40))
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0490 - 5.4.1 */
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) /* RM0490 - 5.4.3 */
#define APB1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x3C)) /* RM0490 - 5.4.13 */
#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x40)) /* RM0490 - 5.4.14 */
#define RCC_CR_HSIRDY (1 << 10)
#define RCC_CR_HSION (1 << 8)
@ -56,20 +55,14 @@
#define RCC_CR_HSIDIV_64 (6ul << RCC_CR_HSIDIV_SHIFT)
#define RCC_CR_HSIDIV_128 (7ul << RCC_CR_HSIDIV_SHIFT)
#define RCC_CFGR_SW_HSISYS 0x0
#define RCC_CFGR_SW_PLL 0x2
#define RCC_PLLCFGR_PLLR_EN (1 << 28) /* RM0444 - 5.4.3 */
#define RCC_PLLCFGR_PLLSRC_HSI16 2
/*** APB PRESCALER ***/
#define RCC_PRESCALER_DIV_NONE 0
/*** FLASH ***/
#define PWR_APB1_CLOCK_ER_VAL (1 << 28)
#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* RM0444 - 5.4.15 - RCC_APBENR2 - SYSCFGEN */
#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* RM0490 - 5.4.14 - RCC_APBENR2 - SYSCFGEN */
#define FLASH_BASE (0x40022000) /*FLASH_R_BASE = 0x40000000UL + 0x00020000UL + 0x00002000UL */
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) /* RM0490 - 3.7.1 - FLASH_ACR */
@ -230,26 +223,18 @@ static void clock_pll_off(void)
DMB();
}
/* This implementation will setup HSI RC 48 MHz as System Clock Source, set
* flash wait state to 1, and set all peripherals to 16MHz (div4)
*/
/* This implementation will setup HSI RC 48 MHz as System Clock Source and set
* flash wait state to 1 */
static void clock_pll_on(int powersave)
{
uint32_t reg32;
uint32_t cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, ppre, flash_waitstates;
uint32_t cpu_freq, flash_waitstates;
/* Enable Power controller */
APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL;
/* Select clock parameters (CPU Speed = 48MHz) */
cpu_freq = 48000000;
pllm = 4;
plln = 80;
pllp = 10;
pllq = 5;
pllr = 5;
hpre = RCC_PRESCALER_DIV_NONE;
ppre = RCC_PRESCALER_DIV_NONE;
flash_waitstates = 1;
flash_set_waitstates(flash_waitstates);

2
hal/stm32c0.ld
View File

@ -1,7 +1,7 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K-1
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K
}
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