mirror of https://github.com/wolfSSL/wolfBoot.git
SAMA5D3: Hal fixes, add DBGU, enable ARM_ASM
Daniele Lacamera
parent
07bdae680a
commit
95d58244a9
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@ -5,17 +5,16 @@ HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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EXT_FLASH?=1
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NAND_FLASH?=1
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SPI_FLASH?=0
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V?=0
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SPMATH?=1
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WOLFBOOT_PARTITION_SIZE?=0x1000000
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WOLFBOOT_PARTITION_SIZE?=0x8000000
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WOLFBOOT_NO_PARTITIONS=0
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_LOAD_ADDRESS=0x20100800
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WOLFBOOT_LOAD_DTS_ADDRESS=0x21100800
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WOLFBOOT_LOAD_ADDRESS=0x20100000
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WOLFBOOT_LOAD_DTS_ADDRESS=0x21100000
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WOLFBOOT_PARTITION_BOOT_ADDRESS=0x400000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x800000
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WOLFBOOT_PARTITION_SWAP_ADDRESS=0x0
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@ -666,7 +666,7 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
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return len;
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}
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void pit_init(void)
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static void pit_init(void)
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{
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uint32_t pmc_pcr;
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@ -697,6 +697,29 @@ void sleep_us(uint32_t usec)
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} while (current < delay);
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}
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/* Set up DBGU.
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* Assume baud rate is correcly set by RomBoot
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*/
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static void dbgu_init(void) {
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/* Set up pins */
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PMC_CLOCK_EN(GPIOB_PMCID);
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/* Disable Pull */
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GPIO_PPUDR(DBGU_GPIO) = (1 << DBGU_PIN_TX) | (1 << DBGU_PIN_RX);
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GPIO_PPDDR(DBGU_GPIO) = (1 << DBGU_PIN_TX) | (1 << DBGU_PIN_RX);
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/* Set "Peripheral A" */
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GPIO_ASR(DBGU_GPIO) = (1 << DBGU_PIN_TX) | (1 << DBGU_PIN_RX);
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/* Enable the peripheral clock for the DBGU */
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PMC_CLOCK_EN(DBGU_PMCID);
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/* Enable the transmitter and receiver */
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DBGU_CR = DBGU_CR_TXEN | DBGU_CR_RXEN;
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}
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int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
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{
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/* TODO */
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@ -742,6 +765,7 @@ void hal_init(void)
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pit_init();
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watchdog_disable();
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ddr_init();
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dbgu_init();
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nand_read_info();
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}
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@ -93,8 +93,6 @@
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#define PMC_PCR_DIV_SHIFT 13
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#define PMC_PCR_DIV_MASK (0x3 << PMC_PCR_DIV_SHIFT)
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/* Specific configuration for 264/132/12 MHz */
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#define PLL_PCK (((CRYSTAL_FREQ * (PLLA_MULA + 1)) / 2))
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@ -110,23 +108,33 @@
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#define PLLICPR_CONFIG (0x0 << PMC_PLLICPR_ICPPLLA_SHIFT | 0x3 << PMC_PLLICPR_IPLLA_SHIFT)
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/* DBGU
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*
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*/
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#define DBGU_BASE 0xFFFFEE00
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#define DBGU_CR *(volatile uint32_t *)(DBGU_BASE + 0x00)
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#define DBGU_BRGR *(volatile uint32_t *)(DBGU_BASE + 0x20)
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#define DBGU_CR_RXEN (1 << 4)
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#define DBGU_CR_TXEN (1 << 6)
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#define DBGU_PMCID 0x02 /* dec: 2 for SAMA5D3 */
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/* Associated pins : GPIOB 30 - 31*/
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#define DBGU_PIN_RX 30
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#define DBGU_PIN_TX 31
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#define DBGU_GPIO GPIOB
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/* PIT
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*
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*/
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#define PIT_BASE 0xFFFFFE30
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#define PIT_MR *(volatile uint32_t *)(PIT_BASE + 0x00)
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#define PIT_SR *(volatile uint32_t *)(PIT_BASE + 0x04)
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#define PIT_PIVR *(volatile uint32_t *)(PIT_BASE + 0x08)
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#define PIT_PIIR *(volatile uint32_t *)(PIT_BASE + 0x0C)
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/* DRAM setup
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*
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*/
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#define MPDDRC_BASE 0xFFFFEA00
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#define MPDDRC_MR *(volatile uint32_t *)(MPDDRC_BASE + 0x00) /* Mode Register */
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#define MPDDRC_RTR *(volatile uint32_t *)(MPDDRC_BASE + 0x04) /* Refresh Timer Register */
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@ -159,7 +167,6 @@
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#define MPDDRC_WPMR *(volatile uint32_t *)(MPDDRC_BASE + 0xE4) /* Write Protection Mode Register */
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#define MPDDRC_WPSR *(volatile uint32_t *)(MPDDRC_BASE + 0xE8) /* Write Protection Status Register */
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/* MPDDRC_CR: shift, mask, values */
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#define MPDDRC_NC_SHIFT 0 /* Number of Column Bits */
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#define MPDDRC_NC_MASK (0x3 << MPDDRC_NC_SHIFT)
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@ -285,8 +292,6 @@
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#define GPIOD_PMCID 0x09
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#define GPIOE_PMCID 0x0A
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struct dram {
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struct dram_timing {
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uint32_t tras;
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@ -310,6 +315,7 @@ struct dram {
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};
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/* Watchdog
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*
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*/
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#define WDT_BASE 0xFFFFFD40
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#define WDT_CR *(volatile uint32_t *)(WDT_BASE + 0x00)
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@ -435,7 +441,6 @@ extern void *kernel_addr, *update_addr, *dts_addr;
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#define MAX_ECC_BYTES 8
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#endif
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#define GPIOB 0xFFFFF400
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#define GPIOC 0xFFFFF600
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#define GPIOE 0xFFFFFA00
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@ -454,6 +459,7 @@ extern void *kernel_addr, *update_addr, *dts_addr;
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#define GPIO_MDDR(base) *(volatile uint32_t *)(base + 0x54)
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#define GPIO_PPUDR(base) *(volatile uint32_t *)(base + 0x60)
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#define GPIO_PPUER(base) *(volatile uint32_t *)(base + 0x64)
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#define GPIO_ASR(base) *(volatile uint32_t *)(base + 0x70)
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#define GPIO_PPDDR(base) *(volatile uint32_t *)(base + 0x90)
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@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
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MEMORY
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{
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DDR_MEM(rwx): ORIGIN = 0x20100800, LENGTH = 0x100000
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DDR_MEM(rwx): ORIGIN = 0x20100000, LENGTH = 0x100000
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STACK_MEM(rw): ORIGIN = 0x20000000, LENGTH = 0x00100000
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}
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