mirror of https://github.com/wolfSSL/wolfBoot.git
STM32C0 support
Bill Phipps
Daniele Lacamera
parent
f4ea7784bf
commit
a1d584b838
11
arch.mk
11
arch.mk
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@ -83,6 +83,17 @@ ifeq ($(ARCH),ARM)
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CORTEX_M0=1
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SPI_TARGET=stm32
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endif
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ifeq ($(TARGET),stm32c0)
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CORTEX_M0=1
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ARCH_FLASH_OFFSET=0x08000000
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# Enable this feature for secure memory support
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# Makes the flash sectors for the bootloader unacessible from the application
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# Requires using the STM32CubeProgrammer to set FLASH_SECR -> SEC_SIZE pages
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CFLAGS+=-DFLASH_SECURABLE_MEMORY_SUPPORT
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endif
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ifeq ($(TARGET),stm32g0)
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CORTEX_M0=1
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ARCH_FLASH_OFFSET=0x08000000
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@ -0,0 +1,34 @@
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ARCH?=ARM
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TARGET?=stm32c0
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SIGN?=ED25519
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#Using SHA384 with ED25519 saves about 2kB without SHA256 code
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HASH?=SHA384
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DEBUG?=0
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VTOR?=1
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CORTEX_M0?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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#Max APP size is 4kB
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WOLFBOOT_PARTITION_SIZE?=0x2000
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WOLFBOOT_SECTOR_SIZE?=0x800
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#Max WOLFBOOT size is 14kB. Currently only 10kB
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08003800
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08005800
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08007800
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#For a debug/not size optimized layout:
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#DEBUG?=1
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#WOLFBOOT_PARTITION_SIZE?=0x1000
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#WOLFBOOT_SECTOR_SIZE?=0x800
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#WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08005800
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#WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08006800
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#WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08007800
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@ -19,7 +19,7 @@ and RAM boundaries.
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## Supported platforms
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The following platforms are supported in the current version:
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- STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0
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- STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0, STM32C0
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- nRF52
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- Atmel samR21
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- TI cc26x2
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@ -21,6 +21,7 @@ This README describes configuration of supported targets.
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* [STM32L4](#stm32l4)
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* [STM32L5](#stm32l5)
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* [STM32G0](#stm32g0)
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* [STM32C0](#stm32c0)
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* [STM32H7](#stm32h7)
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* [STM32U5](#stm32u5)
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* [STM32WB55](#stm32wb55)
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@ -424,6 +425,82 @@ add-symbol-file test-app/image.elf 0x08008100
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mon reset init
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```
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## STM32C0
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Supports STM32C0x0/STM32C0x1.
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Example and instructions are for the STM Nucleo-C031C6 dev board using the
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STM32Cube
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Example 32KB partitioning on STM32-G070:
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- Sector size: 2KB
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- Wolfboot partition size: 14KB
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- Application partition size: 8 KB
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- Swap size 2KB
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```C
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#define WOLFBOOT_SECTOR_SIZE 0x800 /* 2 KB */
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x08004000 /* offset 16kB to 24kB */
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#define WOLFBOOT_PARTITION_SIZE 0x2000 /* 8 KB */
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x08006000 /* offset 24kB to 32kB */
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x08003800 /* offset 14kB to 16kB */
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```
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### Building STM32C0
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xxx
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Reference configuration (see [/config/examples/stm32g0.config](/config/examples/stm32g0.config)).
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You can copy this to wolfBoot root as `.config`: `cp ./config/examples/stm32g0.config .config`.
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To build you can use `make`.
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The TARGET for this is `stm32g0`: `make TARGET=stm32g0`.
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The option `CORTEX_M0` is automatically selected for this target.
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The option `NVM_FLASH_WRITEONCE=1` is mandatory on this target, since the IAP driver does not support
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multiple writes after each erase operation.
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This target also supports secure memory protection on the bootloader region
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using the `FLASH_CR:SEC_PROT` and `FLASH_SECT:SEC_SIZE` registers. This is the
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number of 2KB pages to block access to from the 0x8000000 base address.
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```
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STM32_Programmer_CLI -c port=swd mode=hotplug -ob SEC_SIZE=0x10
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```
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For RAMFUNCTION support (required for SEC_PROT) make sure `RAM_CODE=1`.
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### STM32C0 Programming
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xxx
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Compile requirements: `make TARGET=stm32g0 NVM_FLASH_WRITEONCE=1`
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The output is a single `factory.bin` that includes `wolfboot.bin` and `test-app/image_v1_signed.bin` combined together.
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This should be programmed to the flash start address `0x08000000`.
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Flash using the STM32CubeProgrammer CLI:
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```
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STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000
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```
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### STM32C0 Debugging
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xxx
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Use `make DEBUG=1` and program firmware again.
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Start GDB server on port 3333:
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```
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ST-LINK_gdbserver -d -e -r 1 -p 3333
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OR
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st-util -p 3333
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```
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wolfBoot has a .gdbinit to configure GDB
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```
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arm-none-eabi-gdb
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add-symbol-file test-app/image.elf 0x08008100
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mon reset init
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```
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## STM32WB55
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@ -0,0 +1,373 @@
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/* stm32c0.c
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <image.h>
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#ifndef NVM_FLASH_WRITEONCE
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# error "wolfBoot STM32C0 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
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#endif
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/* XXX Debug only! */
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#define NO_FLASH_SEC_SIZE_CHECK 1
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/* STM32 C0 register configuration */
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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#define ISB() __asm__ volatile ("isb")
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#define DSB() __asm__ volatile ("dsb")
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/*** RCC ***/
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#define RCC_BASE (0x40021000)
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0444 - 5.4.1 */
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#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) /* RM0444 - 5.4.3 */
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#define APB1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x3C))
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x40))
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#define RCC_CR_HSIRDY (1 << 10)
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#define RCC_CR_HSION (1 << 8)
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#define RCC_CR_HSIDIV_SHIFT 11
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#define RCC_CR_HSIDIV_MASK 0x7
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#define RCC_CR_HSIDIV_1 (0ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_2 (1ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_4 (2ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_8 (3ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_16 (4ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_32 (5ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_64 (6ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CR_HSIDIV_128 (7ul << RCC_CR_HSIDIV_SHIFT)
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#define RCC_CFGR_SW_HSISYS 0x0
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#define RCC_CFGR_SW_PLL 0x2
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#define RCC_PLLCFGR_PLLR_EN (1 << 28) /* RM0444 - 5.4.3 */
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#define RCC_PLLCFGR_PLLSRC_HSI16 2
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/*** APB PRESCALER ***/
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#define RCC_PRESCALER_DIV_NONE 0
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/*** FLASH ***/
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#define PWR_APB1_CLOCK_ER_VAL (1 << 28)
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#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* RM0444 - 5.4.15 - RCC_APBENR2 - SYSCFGEN */
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#define FLASH_BASE (0x40022000) /*FLASH_R_BASE = 0x40000000UL + 0x00020000UL + 0x00002000UL */
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) /* RM0490 - 3.7.1 - FLASH_ACR */
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#define FLASH_KEY (*(volatile uint32_t *)(FLASH_BASE + 0x08)) /* RM0490 - 3.7.2 - FLASH_KEYR */
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#define FLASH_OPTKEY (*(volatile uint32_t *)(FLASH_BASE + 0x0C)) /* RM0490 - 3.7.3 - FLASH_OPTKEYR */
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x14)) /* RM0490 - 3.7.5 - FLASH_CR */
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#define FLASH_SECR (*(volatile uint32_t *)(FLASH_BASE + 0x80)) /* RM0490 - 3.7.13 - FLASH_SECR */
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#define FLASHMEM_ADDRESS_SPACE (0x08000000)
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#define FLASH_PAGE_SIZE (0x800) /* 2KB */
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#define FLASH_PAGE_SIZE_SHIFT 11 /* (1 << FLASH_PAGE_SIZE_SHIFT) == FLASH_PAGE_SIZE*/
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/* Register values */
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#define FLASH_ACR_LAT_SHIFT 0 /* RM0490 - 3.7.1 -FLASH_ACT */
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#define FLASH_ACR_LAT_MASK 0x01 /* RM0490 - 3.7.1 -FLASH_ACT */
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#define FLASH_SR_BSY1 (1 << 16) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_SR_SIZERR (1 << 6) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_SR_PGAERR (1 << 5) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_SR_WRPERR (1 << 4) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_SR_PROGERR (1 << 3) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_SR_EOP (1 << 0) /* RM0490 - 3.7.4 - FLASH_SR */
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#define FLASH_CR_LOCK (1 << 31) /* RM0490 - 3.7.5 - FLASH_CR */
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#define FLASH_CR_STRT (1 << 16) /* RM0490 - 3.7.5 - FLASH_CR */
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#define FLASH_CR_PER (1 << 1) /* RM0490 - 3.7.5 - FLASH_CR */
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#define FLASH_CR_PG (1 << 0) /* RM0490 - 3.7.5 - FLASH_CR */
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#define FLASH_CR_SEC_PROT (1 << 28) /* RM0490 - 3.7.5 - FLASH_CR */
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#define FLASH_CR_PNB_SHIFT 3 /* RM0490 - 3.7.5 - FLASH_CR - PNB bits 8:3 */
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#define FLASH_CR_PNB_MASK 0x3f /* RM0490 - 3.7.5 - FLASH_CR - PNB bits 8:3 - 6 bits */
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#define FLASH_SECR_SEC_SIZE_POS (0U)
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#define FLASH_SECR_SEC_SIZE_MASK (0xFF)
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#define FLASH_KEY1 (0x45670123)
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#define FLASH_KEY2 (0xCDEF89AB)
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#define FLASH_OPTKEY1 (0x08192A3B)
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#define FLASH_OPTKEY2 (0x4C5D6E7F)
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static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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{
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uint32_t reg, mask_val, set_val;
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reg = FLASH_ACR;
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mask_val = FLASH_ACR_LAT_MASK << FLASH_ACR_LAT_SHIFT;
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set_val = (waitstates << FLASH_ACR_LAT_SHIFT) & mask_val;
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if ((reg & mask_val) != set_val)
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FLASH_ACR = (reg & ~mask_val) | set_val;
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}
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static RAMFUNCTION void flash_wait_complete(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY1) == FLASH_SR_BSY1)
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;
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}
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static void RAMFUNCTION flash_clear_errors(void)
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{
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/* Consider only writing here as there is no reason to read first (rc_w1),
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* unless other error bits are set*/
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/* FLASH_SR = (FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR |
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FLASH_SR_PROGERR); */
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FLASH_SR |= (FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR |
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FLASH_SR_PROGERR);
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}
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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int i = 0;
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uint32_t *src, *dst;
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flash_clear_errors();
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FLASH_CR |= FLASH_CR_PG;
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while (i < len) {
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flash_clear_errors();
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if ((len - i > 3) && ((((address + i) & 0x07) == 0) &&
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((((uint32_t)data) + i) & 0x07) == 0)) {
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src = (uint32_t *)data;
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dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE);
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flash_wait_complete();
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dst[i >> 2] = src[i >> 2];
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dst[(i >> 2) + 1] = src[(i >> 2) + 1];
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flash_wait_complete();
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i+=8;
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} else {
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uint32_t val[2];
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uint8_t *vbytes = (uint8_t *)(val);
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int off = (address + i) - (((address + i) >> 3) << 3);
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uint32_t base_addr = address & (~0x07); /* aligned to 64 bit */
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int u32_idx = (i >> 2);
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dst = (uint32_t *)(base_addr);
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val[0] = dst[u32_idx];
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val[1] = dst[u32_idx + 1];
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while ((off < 8) && (i < len))
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vbytes[off++] = data[i++];
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dst[u32_idx] = val[0];
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dst[u32_idx + 1] = val[1];
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flash_wait_complete();
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}
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}
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if ((FLASH_SR & FLASH_SR_EOP) == FLASH_SR_EOP)
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FLASH_SR |= FLASH_SR_EOP;
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FLASH_CR &= ~FLASH_CR_PG;
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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flash_wait_complete();
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if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
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FLASH_KEY = FLASH_KEY1;
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DMB();
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FLASH_KEY = FLASH_KEY2;
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DMB();
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while ((FLASH_CR & FLASH_CR_LOCK) != 0)
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;
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}
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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flash_wait_complete();
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if ((FLASH_CR & FLASH_CR_LOCK) == 0)
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FLASH_CR |= FLASH_CR_LOCK;
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}
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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int start = -1, end = -1;
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uint32_t end_address;
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uint32_t p;
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if (len == 0)
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return -1;
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end_address = address + len - 1;
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for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
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uint32_t reg = FLASH_CR & (~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT));
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FLASH_CR = reg | ((p >> FLASH_PAGE_SIZE_SHIFT) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER;
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DMB();
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FLASH_CR |= FLASH_CR_STRT;
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flash_wait_complete();
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FLASH_CR &= ~FLASH_CR_PER;
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}
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return 0;
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}
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static void clock_pll_off(void)
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{
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uint32_t reg32;
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/* Select HSISYS as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
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DMB();
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#if 0
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/* Turn off PLL */
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RCC_CR &= ~RCC_CR_PLLON;
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DMB();
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#endif
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}
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/* This implementation will setup HSI RC 48 MHz as System Clock Source, set
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* flash wait state to 2, and set all peripherals to 16MHz (div4)
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*
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* */
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static void clock_pll_on(int powersave)
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{
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uint32_t reg32;
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uint32_t cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, ppre, flash_waitstates;
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/* Enable Power controller */
|
||||
APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL;
|
||||
|
||||
/* Select clock parameters (CPU Speed = 48MHz) */
|
||||
cpu_freq = 48000000;
|
||||
pllm = 4;
|
||||
plln = 80;
|
||||
pllp = 10;
|
||||
pllq = 5;
|
||||
pllr = 5;
|
||||
hpre = RCC_PRESCALER_DIV_NONE;
|
||||
ppre = RCC_PRESCALER_DIV_NONE;
|
||||
flash_waitstates = 1;
|
||||
|
||||
flash_set_waitstates(flash_waitstates);
|
||||
|
||||
/* Enable internal high-speed oscillator. */
|
||||
RCC_CR |= RCC_CR_HSION;
|
||||
DMB();
|
||||
while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
|
||||
|
||||
/* Select HSISYS as SYSCLK source. */
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
|
||||
DMB();
|
||||
|
||||
#if 0
|
||||
/* Disable PLL */
|
||||
RCC_CR &= ~RCC_CR_PLLON;
|
||||
|
||||
/* Set prescalers for AHB, ADC, ABP1, ABP2. */
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(0xF0); /* don't change bits [0-3] that were previously set */
|
||||
RCC_CFGR = (reg32 | (hpre << 8)); /* RM0444 - 5.4.3 - RCC_CFGR */
|
||||
DMB();
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(0x1C00); /* don't change bits [0-14] */
|
||||
RCC_CFGR = (reg32 | (ppre << 12)); /* RM0444 - 5.4.3 - RCC_CFGR */
|
||||
DMB();
|
||||
|
||||
/* Set PLL config */
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 |= RCC_PLLCFGR_PLLSRC_HSI16;
|
||||
reg32 |= ((pllm - 1) << 4);
|
||||
reg32 |= plln << 8;
|
||||
reg32 |= ((pllp - 1) << 17);
|
||||
reg32 |= ((pllr - 1) << 29);
|
||||
RCC_PLLCFGR = reg32;
|
||||
|
||||
DMB();
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
RCC_PLLCFGR |= RCC_PLLCFGR_PLLR_EN;
|
||||
RCC_CR |= RCC_CR_PLLON;
|
||||
DMB();
|
||||
while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
|
||||
DMB();
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
|
||||
#endif
|
||||
/* SYSCFG, COMP and VREFBUF clock enable */
|
||||
APB2_CLOCK_ER |= SYSCFG_APB2_CLOCK_ER_VAL;
|
||||
}
|
||||
|
||||
void hal_init(void)
|
||||
{
|
||||
clock_pll_on(0);
|
||||
}
|
||||
|
||||
#ifdef FLASH_SECURABLE_MEMORY_SUPPORT
|
||||
static void RAMFUNCTION do_secure_boot(void)
|
||||
{
|
||||
uint32_t sec_size = (FLASH_SECR & FLASH_SECR_SEC_SIZE_MASK);
|
||||
|
||||
/* The "SEC_SIZE" is the number of pages (2KB) to extend from base 0x8000000
|
||||
* and it is programmed using the STM32CubeProgrammer option bytes.
|
||||
* Example: STM32_Programmer_CLI -c port=swd mode=hotplug -ob SEC_SIZE= */
|
||||
#ifndef NO_FLASH_SEC_SIZE_CHECK
|
||||
/* Make sure at least the first sector is protected and the size is not
|
||||
* larger than boot partition */
|
||||
if (sec_size <= 1 ||
|
||||
sec_size > (WOLFBOOT_PARTITION_BOOT_ADDRESS / WOLFBOOT_SECTOR_SIZE)) {
|
||||
/* panic: invalid sector size */
|
||||
while(1)
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* TODO: Add checks for WRP, RDP and BootLock. Add warning to help lock down
|
||||
* target in production */
|
||||
|
||||
/* unlock flash to access FLASH_CR write */
|
||||
hal_flash_unlock();
|
||||
|
||||
ISB();
|
||||
|
||||
/* Activate secure user memory */
|
||||
/* secure code to make sure SEC_PROT gets set (based on reference code) */
|
||||
do {
|
||||
FLASH_CR |= FLASH_CR_SEC_PROT;
|
||||
} while ((FLASH_CR & FLASH_CR_SEC_PROT) == 0);
|
||||
|
||||
DSB();
|
||||
}
|
||||
#endif
|
||||
|
||||
void RAMFUNCTION hal_prepare_boot(void)
|
||||
{
|
||||
#ifdef SPI_FLASH
|
||||
spi_flash_release();
|
||||
#endif
|
||||
clock_pll_off();
|
||||
#ifdef FLASH_SECURABLE_MEMORY_SUPPORT
|
||||
do_secure_boot();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002FFF
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_start_text = .;
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
_end_text = .;
|
||||
} > FLASH
|
||||
|
||||
.edidx :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.exidx*)
|
||||
} > FLASH
|
||||
|
||||
_stored_data = .;
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > RAM
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_start_bss = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
__bss_end__ = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
. = ALIGN(4);
|
||||
}
|
||||
|
||||
END_STACK = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K /* Run in lowmem */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_start_text = .;
|
||||
KEEP(*(.isr_vector))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
*(.text*)
|
||||
KEEP(*(.rodata*))
|
||||
. = ALIGN(4);
|
||||
_end_text = .;
|
||||
} > FLASH
|
||||
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
_start_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
}
|
||||
|
||||
_wolfboot_partition_boot_address = @WOLFBOOT_PARTITION_BOOT_ADDRESS@;
|
||||
_wolfboot_partition_size = @WOLFBOOT_PARTITION_SIZE@;
|
||||
_wolfboot_partition_update_address = @WOLFBOOT_PARTITION_UPDATE_ADDRESS@;
|
||||
_wolfboot_partition_swap_address = @WOLFBOOT_PARTITION_SWAP_ADDRESS@;
|
||||
|
||||
PROVIDE(_start_heap = _end);
|
||||
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));
|
||||
|
|
@ -119,6 +119,10 @@ ifeq ($(TARGET),stm32h7)
|
|||
LSCRIPT_TEMPLATE=ARM-stm32h7.ld
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),stm32c0)
|
||||
LSCRIPT_TEMPLATE=ARM-stm32c0.ld
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),stm32l4)
|
||||
APP_OBJS+=$(STM32CUBE)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o
|
||||
APP_OBJS+=$(STM32CUBE)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
/* main.c
|
||||
*
|
||||
* Test bare-metal boot-led-on application
|
||||
*
|
||||
* Copyright (C) 2023 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "led.h"
|
||||
#include "wolfboot/wolfboot.h"
|
||||
|
||||
#ifdef PLATFORM_stm32c0
|
||||
|
||||
void main(void) {
|
||||
boot_led_on();
|
||||
/* Wait for reboot */
|
||||
while(1)
|
||||
;
|
||||
}
|
||||
#endif /* PLATFORM_stm32c0 */
|
||||
|
||||
|
|
@ -146,6 +146,43 @@ void boot_led_on(void)
|
|||
|
||||
#endif /** PLATFORM_stm32g0 **/
|
||||
|
||||
#ifdef PLATFORM_stm32c0
|
||||
#include <stdint.h>
|
||||
#include "wolfboot/wolfboot.h"
|
||||
|
||||
|
||||
/*GPIOA5 on Nucleo C031C6*/
|
||||
#define RCC_IOPENR (*(volatile uint32_t *)(0x40021034)) // 40021034
|
||||
#define RCC_IOPENR_GPIOAEN (1 << 0)
|
||||
|
||||
#define GPIOA_BASE 0x50000000
|
||||
#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
|
||||
#define GPIOA_OTYPE (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
|
||||
#define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
|
||||
#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c))
|
||||
#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
|
||||
#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
|
||||
#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
|
||||
#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
|
||||
#define LED_PIN (5)
|
||||
#define LED_BOOT_PIN (5)
|
||||
#define GPIO_OSPEED_100MHZ (0x03)
|
||||
|
||||
void boot_led_on(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t pin = LED_BOOT_PIN;
|
||||
RCC_IOPENR |= RCC_IOPENR_GPIOAEN;
|
||||
reg = GPIOA_MODE & ~(0x03 << (pin * 2));
|
||||
GPIOA_MODE = reg | (1 << (pin * 2)); // general purpose output mode
|
||||
reg = GPIOA_PUPD & ~(0x03 << (pin * 2));
|
||||
GPIOA_PUPD = reg | (1 << (pin * 2)); // pull-up
|
||||
GPIOA_BSRR |= (1 << pin); // set pin
|
||||
}
|
||||
|
||||
#endif /** PLATFORM_stm32c0 **/
|
||||
|
||||
|
||||
#ifdef PLATFORM_stm32wb
|
||||
#define LED_BOOT_PIN (0)
|
||||
#define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(0x5800004C))
|
||||
|
|
|
|||
Loading…
Reference in New Issue