mirror of https://github.com/wolfSSL/wolfBoot.git
Allow build-time adjustment of QSPI reference clock and divisor. Eliminate `ZCU102` macro (not needed). Add QSPI init message with ref clock, divisor, bus and IO mode (Poll or DMA).
David Garske
Daniele Lacamera
parent
fb08f0788c
commit
b8a23b1f81
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@ -3,9 +3,6 @@ TARGET?=zynq
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WOLFBOOT_VERSION?=0
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# Default to ZCU102 as hardware platform (QSPI sizes)
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CFLAGS_EXTRA+=-DZCU102
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# RSA 4096-bit with SHA3-384
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SIGN?=RSA4096
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HASH?=SHA3
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@ -80,7 +77,10 @@ CROSS_COMPILE=aarch64-none-elf-
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# Speed up reads from flash by using larger blocks
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CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
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# QSPI Clock at 0=150MHz, 1=75MHz, 2=37.5MHz (default)
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# QSPI Reference Clock: Ref (125MHz default)
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#CFLAGS_EXTRA+=-DGQSPI_CLK_REF=300000000
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# QSPI Bus Divisor: (2 << div) = BUS (0=div2, 1=div4, 2=div8)
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#CFLAGS_EXTRA+=-DGQSPI_CLK_DIV=0
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# QSPI force IO mode (default is faster DMA mode)
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21
hal/zynq.c
21
hal/zynq.c
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@ -44,7 +44,7 @@
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/* Xilinx BSP Driver */
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#include "xqspipsu.h"
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#ifndef QSPI_DEVICE_ID
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#define QSPI_DEVICE_ID XPAR_XQSPIPSU_0_DEVICE_ID
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#define QSPI_DEVICE_ID XPAR_XQSPIPSU_0_DEVICE_ID
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#endif
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#ifndef QSPI_CLK_PRESACALE
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#define QSPI_CLK_PRESACALE XQSPIPSU_CLK_PRESCALE_8
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@ -104,7 +104,7 @@ void uart_init(void)
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ZYNQMP_UART_RXTOUT = 0;
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/* baud (115200) = master clk / (BR_GEN * (BR_DIV + 1)) */
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ZYNQMP_UART_BR_GEN = UART_MASTER_CLOCK / (DEBUG_UART_BAUD * (DEBUG_UART_DIV+1));
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ZYNQMP_UART_BR_GEN = UART_CLK_REF / (DEBUG_UART_BAUD * (DEBUG_UART_DIV+1));
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ZYNQMP_UART_BR_DIV = DEBUG_UART_DIV;
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/* Reset TX/RX */
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@ -843,6 +843,16 @@ void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
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}
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#else
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/* QSPI bare-metal driver */
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wolfBoot_printf("QSPI Init: Ref=%dMHz, Div=%d, Bus=%d, IO=%s\n",
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GQSPI_CLK_REF/1000000,
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(2 << GQSPI_CLK_DIV),
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(GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)),
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#ifdef GQSPI_MODE_IO
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"Poll"
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#else
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"DMA"
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#endif
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);
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/* Disable Linear Mode in case FSBL enabled it */
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LQSPI_EN = 0;
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@ -872,21 +882,20 @@ void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
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reg_cfg &= ~(GQSPI_CFG_CLK_POL | GQSPI_CFG_CLK_PH); /* Use POL=0,PH=0 */
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GQSPI_CFG = reg_cfg;
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#if GQSPI_CLK_DIV >= 1 /* 125/4=31.25MHz */
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#if (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)) <= 40000000 /* 40MHz */
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/* At <40 MHz, the Quad-SPI controller should be in non-loopback mode with
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* the clock and data tap delays bypassed. */
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IOU_TAPDLY_BYPASS |= IOU_TAPDLY_BYPASS_LQSPI_RX;
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GQSPI_LPBK_DLY_ADJ = 0;
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GQSPI_DATA_DLY_ADJ = 0;
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#elif GQSPI_CLK_DIV >= 0 /* 125/2 = 62.5MHz */
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#elif (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)) <= 100000000 /* 100MHz */
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/* At <100 MHz, the Quad-SPI controller should be in clock loopback mode
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* with the clock tap delay bypassed, but the data tap delay enabled. */
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IOU_TAPDLY_BYPASS |= IOU_TAPDLY_BYPASS_LQSPI_RX;
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GQSPI_LPBK_DLY_ADJ = GQSPI_LPBK_DLY_ADJ_USE_LPBK;
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GQSPI_DATA_DLY_ADJ = (GQSPI_DATA_DLY_ADJ_USE_DATA_DLY |
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GQSPI_DATA_DLY_ADJ_DATA_DLY_ADJ(2));
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#endif
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#if 0
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#elif (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)) <= 150000000 /* 150MHz */
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/* At <150 MHz, only the generic controller can be used.
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* The generic controller should be in clock loopback mode and the clock
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* tap delay enabled, but the data tap delay disabled. */
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46
hal/zynq.h
46
hal/zynq.h
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@ -51,15 +51,10 @@
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#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
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#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
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/* Clocking */
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#define CORTEXA53_0_CPU_CLK_FREQ_HZ 1199880127
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#define CORTEXA53_0_TIMESTAMP_CLK_FREQ 99990005
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#define UART_MASTER_CLOCK 99990005
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#define GQSPI_CLK_FREQ_HZ 124987511
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/* IOP System-level Control */
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#define IOU_SLCR_BASSE 0xFF180000
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#define IOU_TAPDLY_BYPASS (*((volatile uint32_t*)(IOU_SLCR_BASSE + 0x390)))
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#define IOU_TAPDLY_BYPASS_ADDR (IOU_SLCR_BASSE + 0x390)
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#define IOU_TAPDLY_BYPASS (*((volatile uint32_t*)IOU_TAPDLY_BYPASS_ADDR))
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#define IOU_TAPDLY_BYPASS_LQSPI_RX (1UL << 2) /* LQSPI Tap Delay Enable on Rx Clock signal. 0: enable. 1: disable (bypass tap delay). */
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/* QSPI bare-metal driver */
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@ -186,8 +181,12 @@
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#define GQSPIDMA_ISR_ALL_MASK 0xFEU
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/* QSPI Configuration (bare-metal only) */
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#ifndef GQSPI_CLK_REF
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#define GQSPI_CLK_REF 125000000 /* QSPI Reference Clock */
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#endif
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#ifndef GQSPI_CLK_DIV
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#define GQSPI_CLK_DIV 2 /* (CLK (300MHz) / (2 << DIV) = BUS): 0=DIV2, 1=DIV4, 2=DIV8 */
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#define GQSPI_CLK_DIV 2 /* (QSPI_REF_CLK (125MHZ) / (2 << DIV) = BUS): 0=DIV2, 1=DIV4, 2=DIV8 */
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#endif
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#define GQSPI_CS_ASSERT_CLOCKS 5 /* CS Setup Time (tCSS) - num of clock cycles foes in IMM */
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#define GQSPI_FIFO_WORD_SZ 4
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@ -221,29 +220,20 @@
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/* Flash Parameters:
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* Micron Serial NOR Flash Memory 64KB Sector Erase MT25QU512ABB
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* Stacked device (two 512Mb (64MB))
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* Dual Parallel so total addressable size is double
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* Micron Serial NOR Flash Memory 4K Sector Erase MT25QU512ABB
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* ZCU102 uses dual Parallel (stacked device 2*64MB)
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* MT25QU512 - Read FlashID: 20 BB 20 (64MB)
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* MT25QU01G - Read FlashID: 20 BB 21 (128MB)
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* MT25QU02G - Read FlashID: 20 BB 22 (256MB)
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*/
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#ifndef FLASH_DEVICE_SIZE
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#ifdef ZCU102
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/* 64*2 (dual parallel) = 128MB */
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#define FLASH_DEVICE_SIZE (2 * 64 * 1024 * 1024) /* MT25QU512ABB */
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#else
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/* 128*2 (dual parallel) = 256MB */
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#define FLASH_DEVICE_SIZE (2 * 128 * 1024 * 1024) /* MT25QU01GBBB */
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#endif
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#endif
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#ifndef FLASH_PAGE_SIZE
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#ifdef ZCU102
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/* MT25QU512ABB - Read FlashID: 20 BB 20 */
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#define FLASH_PAGE_SIZE 256
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#else
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/* MT25QU01GBBB - Read FlashID: 20 BB 21 */
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#if defined(GQPI_USE_DUAL_PARALLEL) && GQPI_USE_DUAL_PARALLEL == 1
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/* each flash page size is 256 bytes, for dual parallel double it */
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#define FLASH_PAGE_SIZE 512
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#else
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#define FLASH_PAGE_SIZE 256
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#endif
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#endif
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#define FLASH_NUM_SECTORS (FLASH_DEVICE_SIZE/WOLFBOOT_SECTOR_SIZE)
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/* Flash Commands */
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@ -370,6 +360,10 @@
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#define DEBUG_UART_BASE ZYNQMP_UART0_BASE
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#endif
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#ifndef UART_CLK_REF
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#define UART_CLK_REF 100000000
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#endif
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#ifndef DEBUG_UART_BAUD
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#define DEBUG_UART_BAUD 115200
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#define DEBUG_UART_DIV 6
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