mirror of https://github.com/wolfSSL/wolfBoot.git
PR cleanups based on peer review. Fixes to support < 10KB wolfBoot for either RSA2048 or ED25519. Partition scheme allows 10KB application partition or (6KB actual due to NVM write once). Made space using NO_MPU=1, RAM_CODE=0, USE_SLOW_SHA256 and !FLASH_SECURABLE_MEMORY_SUPPORT.
David Garske
Daniele Lacamera
parent
a1d584b838
commit
c4dfa3f986
7
arch.mk
7
arch.mk
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@ -87,11 +87,6 @@ ifeq ($(ARCH),ARM)
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ifeq ($(TARGET),stm32c0)
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CORTEX_M0=1
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ARCH_FLASH_OFFSET=0x08000000
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# Enable this feature for secure memory support
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# Makes the flash sectors for the bootloader unacessible from the application
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# Requires using the STM32CubeProgrammer to set FLASH_SECR -> SEC_SIZE pages
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CFLAGS+=-DFLASH_SECURABLE_MEMORY_SUPPORT
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endif
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ifeq ($(TARGET),stm32g0)
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@ -99,7 +94,7 @@ ifeq ($(ARCH),ARM)
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ARCH_FLASH_OFFSET=0x08000000
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# Enable this feature for secure memory support
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# Makes the flash sectors for the bootloader unacessible from the application
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# Makes the flash sectors for the bootloader unaccessible from the application
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# Requires using the STM32CubeProgrammer to set FLASH_SECR -> SEC_SIZE pages
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CFLAGS+=-DFLASH_SECURABLE_MEMORY_SUPPORT
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endif
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@ -1,12 +1,13 @@
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ARCH?=ARM
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TARGET?=stm32c0
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SIGN?=ED25519
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#Using SHA384 with ED25519 saves about 2kB without SHA256 code
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HASH?=SHA384
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#Supports ED25519/SHA384 or RSA2048/SHA256
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SIGN?=RSA2048
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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CORTEX_M0?=1
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NO_ASM?=0
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NO_MPU?=1
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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@ -14,21 +15,33 @@ NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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#Max APP size is 4kB
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# Enable this to support wolfBoot self-update
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RAM_CODE?=0
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# Use slightly smaller SHA2-256
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CFLAGS_EXTRA+=-DUSE_SLOW_SHA256
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# Enable this feature for secure memory support
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# Makes the flash sectors for the bootloader unaccessible from the application
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# Requires using the STM32CubeProgrammer to set FLASH_SECR -> SEC_SIZE pages
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#CFLAGS_EXTRA+=-DFLASH_SECURABLE_MEMORY_SUPPORT
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#Partition: Boot: 10KB, App, 10KB
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WOLFBOOT_PARTITION_SIZE?=0x2000
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WOLFBOOT_SECTOR_SIZE?=0x800
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#Max WOLFBOOT size is 14kB. Currently only 10kB
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08003800
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08005800
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#Max WOLFBOOT size is 10KB
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08002800
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08005000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08007800
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#For a debug/not size optimized layout:
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#Example debugging partition for larger wolfBoot
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#Partition: Boot: 22KB, App, 4K
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#DEBUG?=1
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#WOLFBOOT_PARTITION_SIZE?=0x1000
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#WOLFBOOT_SECTOR_SIZE?=0x800
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#WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08005800
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#WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08006800
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#WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08007800
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@ -19,7 +19,7 @@ and RAM boundaries.
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## Supported platforms
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The following platforms are supported in the current version:
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- STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0, STM32C0
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- STM32C0, STM32F4, STM32F7, STM32G0, STM32H7, STM32L5, STM32L0, STM32U5, STM32WB55
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- nRF52
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- Atmel samR21
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- TI cc26x2
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@ -427,50 +427,46 @@ mon reset init
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## STM32C0
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Supports STM32C0x0/STM32C0x1.
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Supports STM32C0x0/STM32C0x1. Instructions are for the STM Nucleo-C031C6 dev board.
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Example and instructions are for the STM Nucleo-C031C6 dev board using the
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STM32Cube
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Tested build configurations:
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* With RSA2048 and SHA2-256 the code size is 9724 and it boots in under 1 second.
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* With ED25519 and SHA2-384 the code size is 10024 and takes about 10 seconds for the LED to turn on.
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Example 32KB partitioning on STM32-G070:
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- Sector size: 2KB
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- Wolfboot partition size: 14KB
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- Application partition size: 8 KB
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- Wolfboot partition size: 10KB
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- Application partition size: 10 KB
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- Swap size 2KB
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```C
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#define WOLFBOOT_SECTOR_SIZE 0x800 /* 2 KB */
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x08004000 /* offset 16kB to 24kB */
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#define WOLFBOOT_PARTITION_SIZE 0x2000 /* 8 KB */
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x08006000 /* offset 24kB to 32kB */
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x08003800 /* offset 14kB to 16kB */
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x08002800 /* at 10KB */
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#define WOLFBOOT_PARTITION_SIZE 0x2800 /* 10 KB */
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x08005000 /* at 20KB */
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x08007800 /* at 30KB */
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```
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### Building STM32C0
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xxx
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Reference configuration (see [/config/examples/stm32g0.config](/config/examples/stm32g0.config)).
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You can copy this to wolfBoot root as `.config`: `cp ./config/examples/stm32g0.config .config`.
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Reference configuration (see [/config/examples/stm32c0.config](/config/examples/stm32c0.config)).
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You can copy this to wolfBoot root as `.config`: `cp ./config/examples/stm32c0.config .config`.
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To build you can use `make`.
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The TARGET for this is `stm32g0`: `make TARGET=stm32g0`.
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The TARGET for this is `stm32c0`: `make TARGET=stm32c0`.
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The option `CORTEX_M0` is automatically selected for this target.
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The option `NVM_FLASH_WRITEONCE=1` is mandatory on this target, since the IAP driver does not support
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multiple writes after each erase operation.
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This target also supports secure memory protection on the bootloader region
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using the `FLASH_CR:SEC_PROT` and `FLASH_SECT:SEC_SIZE` registers. This is the
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number of 2KB pages to block access to from the 0x8000000 base address.
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```
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STM32_Programmer_CLI -c port=swd mode=hotplug -ob SEC_SIZE=0x10
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```
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For RAMFUNCTION support (required for SEC_PROT) make sure `RAM_CODE=1`.
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### STM32C0 Programming
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xxx
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Compile requirements: `make TARGET=stm32g0 NVM_FLASH_WRITEONCE=1`
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Compile requirements: `make TARGET=stm32c0 NVM_FLASH_WRITEONCE=1`
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The output is a single `factory.bin` that includes `wolfboot.bin` and `test-app/image_v1_signed.bin` combined together.
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This should be programmed to the flash start address `0x08000000`.
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@ -482,7 +478,7 @@ STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000
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```
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### STM32C0 Debugging
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xxx
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Use `make DEBUG=1` and program firmware again.
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Start GDB server on port 3333:
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@ -26,9 +26,6 @@
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# error "wolfBoot STM32C0 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
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#endif
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/* XXX Debug only! */
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#define NO_FLASH_SEC_SIZE_CHECK 1
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/* STM32 C0 register configuration */
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/* Assembly helpers */
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@ -138,8 +135,6 @@ static void RAMFUNCTION flash_clear_errors(void)
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{
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/* Consider only writing here as there is no reason to read first (rc_w1),
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* unless other error bits are set*/
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/* FLASH_SR = (FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR |
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FLASH_SR_PROGERR); */
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FLASH_SR |= (FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR |
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FLASH_SR_PROGERR);
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}
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@ -233,17 +228,11 @@ static void clock_pll_off(void)
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
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DMB();
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#if 0
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/* Turn off PLL */
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RCC_CR &= ~RCC_CR_PLLON;
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DMB();
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#endif
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}
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/* This implementation will setup HSI RC 48 MHz as System Clock Source, set
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* flash wait state to 2, and set all peripherals to 16MHz (div4)
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*
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* */
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* flash wait state to 1, and set all peripherals to 16MHz (div4)
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*/
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static void clock_pll_on(int powersave)
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{
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uint32_t reg32;
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@ -276,45 +265,6 @@ static void clock_pll_on(int powersave)
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
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DMB();
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#if 0
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/* Disable PLL */
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RCC_CR &= ~RCC_CR_PLLON;
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/* Set prescalers for AHB, ADC, ABP1, ABP2. */
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reg32 = RCC_CFGR;
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reg32 &= ~(0xF0); /* don't change bits [0-3] that were previously set */
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RCC_CFGR = (reg32 | (hpre << 8)); /* RM0444 - 5.4.3 - RCC_CFGR */
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(0x1C00); /* don't change bits [0-14] */
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RCC_CFGR = (reg32 | (ppre << 12)); /* RM0444 - 5.4.3 - RCC_CFGR */
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DMB();
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/* Set PLL config */
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reg32 = RCC_PLLCFGR;
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reg32 |= RCC_PLLCFGR_PLLSRC_HSI16;
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reg32 |= ((pllm - 1) << 4);
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reg32 |= plln << 8;
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reg32 |= ((pllp - 1) << 17);
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reg32 |= ((pllr - 1) << 29);
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RCC_PLLCFGR = reg32;
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DMB();
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/* Enable PLL oscillator and wait for it to stabilize. */
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RCC_PLLCFGR |= RCC_PLLCFGR_PLLR_EN;
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RCC_CR |= RCC_CR_PLLON;
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DMB();
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while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
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/* Select PLL as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
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DMB();
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/* Wait for PLL clock to be selected. */
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
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#endif
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/* SYSCFG, COMP and VREFBUF clock enable */
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APB2_CLOCK_ER |= SYSCFG_APB2_CLOCK_ER_VAL;
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}
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@ -1,7 +1,7 @@
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002FFF
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K-1
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}
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SECTIONS
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@ -267,6 +267,9 @@ endif
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ifeq ($(TARGET),stm32g0)
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CFLAGS+=-DNVM_FLASH_WRITEONCE=1
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endif
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ifeq ($(TARGET),stm32c0)
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CFLAGS+=-DNVM_FLASH_WRITEONCE=1
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endif
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ifeq ($(TARGET),hifive1.freedom)
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CFLAGS+=-I$(FREEDOM_E_SDK)/freedom-metal/ -D__METAL_MACHINE_HEADER=\"$(FREEDOM_E_SDK)/bsp/sifive-hifive1/metal.h\"
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@ -1,4 +1,4 @@
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/* main.c
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/* app_stm32c0.c
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*
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* Test bare-metal boot-led-on application
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*
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@ -36,4 +36,3 @@ void main(void) {
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;
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}
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#endif /* PLATFORM_stm32c0 */
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@ -110,13 +110,9 @@ void boot_led_off(void)
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#endif /* PLATFORM_stm32l0 */
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#ifdef PLATFORM_stm32g0
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#include <stdint.h>
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#include "wolfboot/wolfboot.h"
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/*GPIOA5*/
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#define RCC_IOPENR (*(volatile uint32_t *)(0x40021034)) // 40021034
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#if defined(PLATFORM_stm32g0) || defined(PLATFORM_stm32c0)
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/* GPIOA5 */
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#define RCC_IOPENR (*(volatile uint32_t *)(0x40021034))
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#define RCC_IOPENR_GPIOAEN (1 << 0)
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#define GPIOA_BASE 0x50000000
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@ -138,50 +134,13 @@ void boot_led_on(void)
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uint32_t pin = LED_BOOT_PIN;
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RCC_IOPENR |= RCC_IOPENR_GPIOAEN;
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reg = GPIOA_MODE & ~(0x03 << (pin * 2));
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GPIOA_MODE = reg | (1 << (pin * 2)); // general purpose output mode
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GPIOA_MODE = reg | (1 << (pin * 2)); /* general purpose output mode */
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reg = GPIOA_PUPD & ~(0x03 << (pin * 2));
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GPIOA_PUPD = reg | (1 << (pin * 2)); // pull-up
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GPIOA_BSRR |= (1 << pin); // set pin
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GPIOA_PUPD = reg | (1 << (pin * 2)); /* pull-up */
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GPIOA_BSRR |= (1 << pin); /* set pin */
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}
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#endif /** PLATFORM_stm32g0 **/
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#ifdef PLATFORM_stm32c0
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#include <stdint.h>
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#include "wolfboot/wolfboot.h"
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/*GPIOA5 on Nucleo C031C6*/
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#define RCC_IOPENR (*(volatile uint32_t *)(0x40021034)) // 40021034
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#define RCC_IOPENR_GPIOAEN (1 << 0)
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#define GPIOA_BASE 0x50000000
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#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_OTYPE (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
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#define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
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#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c))
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#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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#define LED_PIN (5)
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#define LED_BOOT_PIN (5)
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#define GPIO_OSPEED_100MHZ (0x03)
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void boot_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_BOOT_PIN;
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RCC_IOPENR |= RCC_IOPENR_GPIOAEN;
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reg = GPIOA_MODE & ~(0x03 << (pin * 2));
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GPIOA_MODE = reg | (1 << (pin * 2)); // general purpose output mode
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reg = GPIOA_PUPD & ~(0x03 << (pin * 2));
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GPIOA_PUPD = reg | (1 << (pin * 2)); // pull-up
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GPIOA_BSRR |= (1 << pin); // set pin
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}
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#endif /** PLATFORM_stm32c0 **/
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#endif /* PLATFORM_stm32g0 || PLATFORM_stm32c0 */
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#ifdef PLATFORM_stm32wb
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#define LED_BOOT_PIN (0)
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Loading…
Reference in New Issue