PSoC6 support: updated configuration, docs added to Targets.md, revert

custom NVM_CACHE_SIZE

Makefile

@@ -141,9 +141,6 @@ endif
 
 ifeq ($(NVM_FLASH_WRITEONCE),1)
   CFLAGS+= -DNVM_FLASH_WRITEONCE
-  ifneq ($(NVM_CACHE_SIZE),)
-    CFLAGS+= -DNVM_CACHE_SIZE=$(NVM_CACHE_SIZE)
-  endif
 endif
 
 

arch.mk

@@ -165,7 +165,7 @@ ifeq ($(TARGET),psoc6)
 					 $(CYPRESS_PDL)/drivers/source/cy_wdt.o \
 					 $(CYPRESS_PDL)/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.o \
 					 $(CYPRESS_PDL)/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.o
-    PKA_EXTRA_CFLAGS+=-I$(CYPRESS_PDL)/drivers/include/ \
+    CFLAGS+=-I$(CYPRESS_PDL)/drivers/include/ \
 		-I$(CYPRESS_PDL)/devices/include \
 		-I$(CYPRESS_PDL)/cmsis/include \
 		-I$(CYPRESS_TARGET_LIB) \

docs/Targets.md

@@ -552,3 +552,87 @@ make CROSS_COMPILE=aarch64-unknown-nto-qnx7.0.0-
 #### Signing
 
 `tools/keytools/sign.py --rsa4096 --sha3 /srv/linux-rpi4/vmlinux.bin rsa4096.der 1`
+
+## Cypress PSoC-62S2 (CY8CKIT-062S2)
+
+The Cypress PSoC 62S2 is a dual-core Cortex-M4 & Cortex-M0+ MCU. The secure boot process is managed by the M0+.
+WolfBoot can be compiled as second stage flash bootloader to manage application verification and firmware updates.
+
+### Building
+
+The following configuration has been tested using PSoC 62S2 Wi-Fi BT Pioneer Kit (CY8CKIT-052S2-43012).
+
+#### Target specific requirements
+
+wolfBoot uses the following components to access peripherals on the PSoC:
+
+  * [Cypress Core Library](https://github.com/cypresssemiconductorco/core-lib)
+  * [PSoC 6 Peripheral Driver Library](https://github.com/cypresssemiconductorco/psoc6pdl)
+  * [CY8CKIT-062S2-43012 BSP](https://github.com/cypresssemiconductorco/TARGET_CY8CKIT-062S2-43012)
+
+Cypress provides a [customized OpenOCD](https://github.com/cypresssemiconductorco/Openocd) for programming the flash and
+debugging.
+
+#### Build configuration
+
+The following configuration has been tested on the PSoC CY8CKIT-62S2-43012:
+
+```
+make TARGET=psoc6
+    NVM_FLASH_WRITEONCE=1
+    CYPRESS_PDL=/home/dan/src/psoc6pdl
+    CYPRESS_TARGET_LIB=/home/dan/src/TARGET_CY8CKIT-062S2-43012
+    CYPRESS_CORE_LIB=/home/dan/src/core-lib
+    WOLFBOOT_SECTOR_SIZE=4096
+```
+
+#### OpenOCD installation
+
+Compile and install the customized OpenOCD.
+
+Use the following configuration file when running `openocd` to connect to the PSoC6 board:
+
+```
+# openocd.cfg for PSoC-62S2
+
+source [find interface/kitprog3.cfg]
+transport select swd
+adapter speed 1000
+source [find target/psoc6_2m.cfg]
+init
+reset init
+```
+
+### Loading the firmware
+
+To upload `factory.bin` to the device with OpenOCD, connect the device,
+run OpenOCD with the configuration from the previous section, then connect
+to the local openOCD server running on TCP port 4444 using `telnet localhost 4444`.
+
+From the telnet console, type:
+
+`program factory.bin 0x10000000`
+
+When the transfer is finished, you can either close openOCD or start a debugging session.
+
+### Debugging
+
+Debugging with OpenOCD:
+
+Use the OpenOCD configuration from the previous sections to run OpenOCD.
+
+From another console, connect using gdb, e.g.:
+
+```
+arm-none-eabi-gdb
+(gdb) target remote:3333
+```
+
+To reset the board to start from the M0+ flash bootloader position (wolfBoot reset handler), use
+the monitor command sequence below:
+
+```
+(gdb) mon init
+(gdb) mon reset init
+(gdb) mon psoc6 reset_halt
+```

hal/psoc6.c

@@ -44,10 +44,6 @@ uint8_t psoc6_write_buffer[ROW_SIZE];
 #   error "wolfBoot psoc6 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
 #endif
 
-#if (NVM_CACHE_SIZE != ROW_SIZE)
-#   error "Wrong NVM_CACHE_SIZE specified for this platform. Please set NVM_CACHE_SIZE to match ROW_SIZE"
-#endif
-
 #ifdef __WOLFBOOT
 /* Replace Cy_SysLib_DelayUs with a custom call that does not use SysTick
  * (required by Cy_SysClk_PllEnable)
@@ -129,7 +125,7 @@ void hal_prepare_boot(void)
 int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
 {
     const uint8_t *src = data;
-    if (len < NVM_CACHE_SIZE)
+    if (len < ROW_SIZE)
         return -1;
     if ((((uint32_t)data) & FLASH_BASE_ADDRESS) == FLASH_BASE_ADDRESS) {
         if (len != ROW_SIZE) {
@@ -140,8 +136,8 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
     }
     while (len) {
         Cy_Flash_ProgramRow(address, (const uint32_t *) src);
-        len -= NVM_CACHE_SIZE;
-        if ((len > 0) && (len < NVM_CACHE_SIZE))
+        len -= ROW_SIZE;
+        if ((len > 0) && (len < ROW_SIZE))
             return -1;
     }
     return 0;
@@ -163,12 +159,9 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
     if (len == 0)
         return -1;
     end_address = address + len;
-    /* Assume NVM_CACHE_SIZE is always defined for this platform 
-     * (see #error statements above)
-     * */
-    while ((end_address - p) >= NVM_CACHE_SIZE) {
+    while ((end_address - p) >= ROW_SIZE) {
         Cy_Flash_EraseRow(p);
-        p += NVM_CACHE_SIZE;
+        p += ROW_SIZE;
     }
     return 0;
 }

include/wolfboot/wolfboot.h

@@ -35,7 +35,7 @@
 #define IMAGE_HEADER_OFFSET (2 * sizeof(uint32_t))
 
 #ifdef NVM_FLASH_WRITEONCE
-#   define FLASHBUFFER_SIZE NVM_CACHE_SIZE
+#   define FLASHBUFFER_SIZE WOLFBOOT_SECTOR_SIZE 
 #else
 #   define FLASHBUFFER_SIZE IMAGE_HEADER_SIZE
 #endif

src/libwolfboot.c

@@ -39,10 +39,7 @@ uint32_t ext_cache;
 #define PART_UPDATE_ENDFLAGS ((WOLFBOOT_PARTITION_UPDATE_ADDRESS + WOLFBOOT_PARTITION_SIZE) - TRAILER_SKIP)
 
 #ifdef NVM_FLASH_WRITEONCE
-
-#ifndef NVM_CACHE_SIZE
-    #error "Please define NVM_CACHE_SIZE for this flash model"
-#endif
+#define NVM_CACHE_SIZE WOLFBOOT_SECTOR_SIZE
 
 #include <stddef.h>
 extern void *memcpy(void *dst, const void *src, size_t n);

tools/config.mk

@@ -23,7 +23,6 @@ ifeq ($(ARCH),)
   UART_FLASH?=0
   ALLOW_DOWNGRADE?=0
   NVM_FLASH_WRITEONCE?=0
-  NVM_CACHE_SIZE=512
   WOLFBOOT_VERSION?=0
   V?=0
   SPMATH?=1
@@ -47,7 +46,7 @@ endif
 CONFIG_VARS:= ARCH TARGET SIGN HASH MCUXPRESSO MCUXPRESSO_CPU MCUXPRESSO_DRIVERS \
 	MCUXPRESSO_CMSIS FREEDOM_E_SDK STM32CUBE CYPRESS_PDL CYPRESS_CORE_LIB CYPRESS_TARGET_LIB DEBUG VTOR \
 	CORTEX_M0 NO_ASM EXT_FLASH SPI_FLASH NO_XIP UART_FLASH ALLOW_DOWNGRADE NVM_FLASH_WRITEONCE \
-	NVM_CACHE_SIZE WOLFBOOT_VERSION V \
+	WOLFBOOT_VERSION V \
 	SPMATH RAM_CODE DUALBANK_SWAP IMAGE_HEADER_SIZE PKA WOLFTPM \
 	WOLFBOOT_PARTITION_SIZE WOLFBOOT_SECTOR_SIZE  \
 	WOLFBOOT_PARTITION_BOOT_ADDRESS WOLFBOOT_PARTITION_UPDATE_ADDRESS \