9 Commits (lpc_fix)

Author	SHA1	Message	Date
Chris Conlon	1f57ad9f39	update copyright to 2020	2020-01-03 15:36:00 -08:00
David Garske	0f00f8e700	SiFive HiFive (FE310) RISC-V support ... * HiFive1 HAL Support for PLL Clock, UART, RTC and Flash QSPI Erase/Write. * HiFive1 update demo application for accepting firmware updates over UART. * Added test-update-server application for pushing firmware image over UART. * Fixes for building with `make SIGN=ECC256`. * Improvements to wolfCrypt `user_settings.h`. * General library cleanup (license headers and formatting) * Updated the wolfSSL submodule to latest. * Documentation updates including new `Targets.md` section for hardare instructions.	2019-06-07 13:08:15 -07:00
Daniele Lacamera	937e9d46fb	Introducing RAMCODE tag to transfer functions to RAM ... - Moved functions in the flash write path to RAM, so their execution does not depend on flash access - RAMCODE can be enabled via "make RAM_CODE=1"	2019-04-29 20:32:04 +02:00
Daniele Lacamera	ab35c7f8fe	Fixed image swap, tested fail-recovery from interrupted update	2018-11-28 21:37:39 +01:00
Daniele Lacamera	1f196bd64c	Major bug fixes in new update code	2018-11-27 07:37:40 +01:00
Daniele Lacamera	24f8c091ac	Fixed nrf52 hal for unaligned byte write operations	2018-11-22 18:52:13 +01:00
Daniele Lacamera	c5f644f97e	Fixed nrf52 flash access	2018-10-25 08:19:54 +02:00
Daniele Lacamera	7f02df51c9	Added SWAP=0 option, fixed some warnings	2018-10-21 10:04:50 +02:00
Daniele Lacamera	ec66c47375	First version of the bootloader	2018-10-11 12:23:58 +02:00