5 Commits (master)

Author	SHA1	Message	Date
David Garske	322d1b3a36	Refactor DDR law setup for use with stage 2 as stack.	2023-10-06 15:28:16 +02:00
David Garske	b3e2fb9ddd	NXP T1024 wolfBoot support: ... * Added DDR4 w/ECC. * Added L2 and L2 CPC SRAM support * Added platform SRAM 160KB support * Added support for core timers (timebase) and platform clock. * Added IFC driver with erase/write * Added stage 1 loader to relocate wolfBoot to DDR * Added CPLD, QUICC, FMAN and MP drivers * Added eSPI driver for TPM. * Added hal_early_init instead of calling ddr_init directly. * Fixes for device tree (DTB) loading with update_ram and PPC boot. * Fixes for relocating CCSRBAR to upper. * Fixes for interrupt offsets.	2023-10-06 15:28:16 +02:00
David Garske	69ca95eb94	Adds `factory_wstage1.bin` option to include first stage loader. Fix test-app verbose issue.	2023-04-21 16:41:00 +02:00
David Garske	553ec760fd	NXP QorIQ refactor for shared PPC (e500 / e6500) registers ... * Fixes for e500 L1/L2 cache. * Fixes for eLBC and DDR3 drivers on P1021. * Fixes for LAW and TLB for P1021. * Fix for the e500v2 core peripheral issues with data barrier / coherency safety. * Support for SP math all (`SPMATHALL=1`). * Support for stage 1 loader (`make stage1`).	2023-04-21 16:41:00 +02:00
David Garske	e88a7dcae3	Progress on DDR support for QorIQ. Refactor the platform to use "nxp_".	2022-12-29 18:27:40 +01:00